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ARM64-SVE: gathervector #103159

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Merged
merged 10 commits into from
Jun 12, 2024
Merged

ARM64-SVE: gathervector #103159

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7ed74a3
ARM64-SVE: gathervector
a74nh Jun 3, 2024
c7d4fc4
HW_Flag_LowMaskedOperation
a74nh Jun 7, 2024
42dc35c
Remove HW_Flag_BaseTypeFromFirstArg and add asserts
a74nh Jun 7, 2024
f3c5eb4
Add invalid testing
a74nh Jun 10, 2024
60dc92f
Add conditional select testing
a74nh Jun 10, 2024
747aa17
Use LSL_N for 64bit address variants
a74nh Jun 11, 2024
1942bde
Remove 32bit address base variants from API
a74nh Jun 11, 2024
d41d2c2
re-add commented out 32bit APIs
a74nh Jun 12, 2024
8066bbb
Add comment on commented out methods
a74nh Jun 12, 2024
5a62f7e
Replace triple quotes with doubles
a74nh Jun 12, 2024
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Use LSL_N for 64bit address variants
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@a74nh
a74nh committed Jun 11, 2024
commit 747aa1763bd4013b461f210d7b6a4440d6d1228f
22 changes: 11 additions & 11 deletions src/coreclr/jit/hwintrinsiccodegenarm64.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -1852,29 +1852,29 @@ void CodeGen::genHWIntrinsic(GenTreeHWIntrinsic* node)
// GatherVector(Vector<T> mask, T* address, Vector<T2> indices)

assert(intrin.numOperands == 3);
emitAttr baseSize = emitActualTypeSize(intrin.baseType);

var_types auxType = node->GetAuxiliaryType();
emitAttr auxSize = emitActualTypeSize(auxType);

if (auxSize == EA_8BYTE)
if (baseSize == EA_8BYTE)
{
opt = varTypeIsUnsigned(auxType) ? INS_OPTS_SCALABLE_D_UXTW : INS_OPTS_SCALABLE_D_SXTW;
// Index is multiplied by 8
GetEmitter()->emitIns_R_R_R_R(ins, emitSize, targetReg, op1Reg, op2Reg, op3Reg, opt,
INS_SCALABLE_OPTS_LSL_N);
}
else
{
assert(auxSize == EA_4BYTE);
opt = varTypeIsUnsigned(auxType) ? INS_OPTS_SCALABLE_S_UXTW : INS_OPTS_SCALABLE_S_SXTW;
// Index is sign or zero extended to 64bits, then multiplied by 4
assert(baseSize == EA_4BYTE);
opt = varTypeIsUnsigned(node->GetAuxiliaryType()) ? INS_OPTS_SCALABLE_S_UXTW
: INS_OPTS_SCALABLE_S_SXTW;
GetEmitter()->emitIns_R_R_R_R(ins, emitSize, targetReg, op1Reg, op2Reg, op3Reg, opt,
INS_SCALABLE_OPTS_MOD_N);
}

GetEmitter()->emitIns_R_R_R_R(ins, emitSize, targetReg, op1Reg, op2Reg, op3Reg, opt,
INS_SCALABLE_OPTS_MOD_N);
}
else
{
// GatherVector(Vector<T> mask, Vector<T2> addresses)

assert(intrin.numOperands == 2);

GetEmitter()->emitIns_R_R_R_I(ins, emitSize, targetReg, op1Reg, op2Reg, 0, opt);
}

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