JIT: Add morphing to LE_UN/GT_UN(expr, uint.MaxValue) (dotnet#76525) #113037

shunkino · 2025-03-02T00:09:59Z

Add morphing for comparison between uint.MaxValue and a ulong value.

Contribute to: #76525

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dotnet-policy-service · 2025-03-02T00:10:34Z

Tagging subscribers to this area: @JulieLeeMSFT, @jakobbotsch
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shunkino · 2025-03-02T00:13:10Z

@dotnet-policy-service agree company="Microsoft"

src/coreclr/jit/morph.cpp

EgorBo · 2025-03-02T04:39:38Z

Seems like CI failed with

 ISSUE: <ASSERT> #263216 D:\a\_work\1\s\src\coreclr\jit\codegenxarch.cpp (4912) - Assertion failed 'operandReg != REG_RCX' in 'bug.Program:TestEntryPoint():int' during 'Generate code' (IL size 42; hash 0x8feb9733; FullOpts)

EgorBo · 2025-03-02T04:43:01Z

src/coreclr/jit/morph.cpp

+                GenTreeOp* shiftNode = gtNewOperNode(GT_RSZ, TYP_LONG, op1, icon32);
+                shiftNode->SetMorphed(this); 
+
+                cmp->gtOp1 = shiftNode;            


EQ/NE(RSZ(expr, 32), 0).

I don't see where that 0 is set here, what is cmp->gtOp2 at this point?

I believe this line sets op2 to 0. All other morphing done in fgOptimizeRelationalComparisonWithConst also don't set 0 explicitly.

runtime/src/coreclr/jit/morph.cpp

Line 9400 in 63a3a5f

op2->SetIntegralValue(0);

jakobbotsch · 2025-03-15T11:27:50Z

Seems like CI failed with

 ISSUE: <ASSERT> #263216 D:\a\_work\1\s\src\coreclr\jit\codegenxarch.cpp (4912) - Assertion failed 'operandReg != REG_RCX' in 'bug.Program:TestEntryPoint():int' during 'Generate code' (IL size 42; hash 0x8feb9733; FullOpts)

That's probably because this PR isn't handling the things pointed out here: #76525 (comment)

shunkino · 2025-03-16T09:02:39Z

Seems like CI failed with
 ISSUE: <ASSERT> #263216 D:\a\_work\1\s\src\coreclr\jit\codegenxarch.cpp (4912) - Assertion failed 'operandReg != REG_RCX' in 'bug.Program:TestEntryPoint():int' during 'Generate code' (IL size 42; hash 0x8feb9733; FullOpts)
That's probably because this PR isn't handling the things pointed out here: #76525 (comment)

Thank you for pointing it out. Will check the issue comment and fix.

shunkino · 2025-03-26T02:06:01Z

src/coreclr/jit/lower.cpp

+#ifdef TARGET_XARCH
+        // Do not optimize, BMI2 shrx does not set zero flag
+        if (op1->OperIs(GT_RSZ) && !op1->AsOp()->gtGetOp2()->OperIsConst())
+        {
+            return cmp;
+        }
+#endif // TARGET_XARCH


Seems like CI failed with

ISSUE: <ASSERT> #263216 D:\a\_work\1\s\src\coreclr\jit\codegenxarch.cpp (4912) - Assertion failed 'operandReg != REG_RCX' in 'bug.Program:TestEntryPoint():int' during 'Generate code' (IL size 42; hash 0x8feb9733; FullOpts)

That's probably because this PR isn't handling the things pointed out here: #76525 (comment)

@jakobbotsch I've implemented the exclusion logic based on your comment. Can you check this? I've thought of checking op2 in LowerShift() and set the flag which tells OptimizeConstCompare() not to optimize, but I think that's redundant and went for directly checking op2 of GT_RSZ here.

jakobbotsch · 2025-03-26T09:48:52Z

src/coreclr/jit/lower.cpp

@@ -4181,6 +4181,13 @@ GenTree* Lowering::OptimizeConstCompare(GenTree* cmp)
    if (cmp->OperIs(GT_EQ, GT_NE) && op2->IsIntegralConst(0) && op1->SupportsSettingZeroFlag() &&
        BlockRange().TryGetUse(cmp, &use))
    {
+#ifdef TARGET_XARCH
+        // Do not optimize, BMI2 shrx does not set zero flag
+        if (op1->OperIs(GT_RSZ) && !op1->AsOp()->gtGetOp2()->OperIsConst())


Can you introduce a function like IsProfitableToSetZeroFlag and put this in there, and check it from the if above? Mainly in case more optimizations get added in the future which we would not want to skip for RSZ.

Also, I think SupportsSettingZeroFlag can work for all shifts and rotations and this profitability check should also happen for those (at the minimum this should also check GT_RSH).

@jakobbotsch
Moved this logic to IsProfitableToSetZeroFlag function. Also, added several operations to SupportsSettingZeroFlag for future optimizations.

jakobbotsch · 2025-03-26T09:49:32Z

There are some cases in the diffs where the optimization is not kicking in:

Can you check why?

jakobbotsch · 2025-03-26T10:19:04Z

I just noticed that the above was a tier 0 method. It looks like fgOptimizeRelationalComparisonWithConst runs even in tier 0.
Can you add an OptimizationEnabled check to the case you are introducing in fgOptimizeRelationalComparisonWithConst since it relies on further optimizations in the backend to happen?

* Add morphing for comparison between uint.MaxValue and a ulong value. * Remove assertions, which no longer is relevant. * Add a check to lsra to only use BMI2 if zero flag will not be set. * Add a profitability check to optimize EQ/NE(op, 0) only if op has constant operand.

shunkino · 2025-04-01T00:30:41Z

src/coreclr/jit/lower.cpp

+bool Lowering::IsProfitableToSetZeroFlag(GenTree* op) const
+{
+#ifdef TARGET_XARCH
+    if (op->OperIs(GT_LSH, GT_RSH, GT_RSZ, GT_ROR))


I've listed all ops that might set zero flag (GT_LSH, GT_RSH, GT_RSZ, GT_ROL, GT_ROR) in SupportsSettingZeroFlag, and filter it here to check if BMI2 version exists.

Is it missing GT_ROL?

As far as I was able to search, there seems to be no operation for shift left on BMI2. So, I droped it from this if statement.
https://en.wikipedia.org/wiki/X86_instruction_listings

RORX reg,r/m,imm8 VEX.LZ.F2.0F3A F0 /r ib Rotate right by immediate without affecting flags.

SARX ra,r/m,rb VEX.LZ.F3.0F38 F7 /r Arithmetic shift right without updating flags.For SARX, SHRX and SHLX, the shift-amount specified in rb is masked to 5 bits for 32-bit operand size and 6 bits for 64-bit operand size.

SHRX ra,r/m,rb VEX.LZ.F2.0F38 F7 /r Logical shift right without updating flags.

SHLX ra,r/m,rb VEX.LZ.66.0F38 F7 /r Shift left without updating flags.

We use rorx for GT_ROL under the same conditions we would use it for GT_ROR.

runtime/src/coreclr/jit/codegenxarch.cpp

Lines 4905 to 4912 in cc2406f

// There is no 'rolx', so for rol, we use rorx with the shift value adjusted.

if (tree->OperIs(GT_ROL))

{

shiftByValue &= (size * BITS_PER_BYTE - 1);

shiftByValue = (size * BITS_PER_BYTE - shiftByValue);

}

inst_RV_TT_IV(INS_rorx, size, tree->GetRegNum(), operand, shiftByValue, INS_OPTS_NONE);

Thank you for pointing this out. I'll put GT_ROL to the criteria.

jakobbotsch · 2025-04-08T05:54:45Z

/azp run Fuzzlyn

azure-pipelines · 2025-04-08T05:54:59Z

Azure Pipelines successfully started running 1 pipeline(s).

shunkino · 2025-04-16T14:16:10Z

Hi @jakobbotsch, I tried to review the Fuzzlyn results, but there are many errors that I’m having trouble interpreting. Sorry to bother you, but could you help me understand what they mean or guide me on how to proceed? Thanks in advance!

jakobbotsch · 2025-04-17T09:43:20Z

I think the Fuzzlyn found issues are unrelated to this PR. I need to take another look, but I don't think anything more is needed from your side.

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src/coreclr/jit/morph.cpp Show resolved Hide resolved

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shunkino force-pushed the jit-uint-maxvalue-compare-76525 branch 2 times, most recently from 4fe1edc to 907e97c Compare March 25, 2025 05:09

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System.Net.Quic tests timeout #107761

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shunkino force-pushed the jit-uint-maxvalue-compare-76525 branch from 907e97c to 440adf9 Compare March 31, 2025 15:58

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JIT: Add morphing to LE_UN/GT_UN(expr, uint.MaxValue) (dotnet#76525) #113037

JIT: Add morphing to LE_UN/GT_UN(expr, uint.MaxValue) (dotnet#76525) #113037

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RORX reg,r/m,imm8	VEX.LZ.F2.0F3A F0 /r ib	Rotate right by immediate without affecting flags.
SARX ra,r/m,rb	VEX.LZ.F3.0F38 F7 /r	Arithmetic shift right without updating flags.For SARX, SHRX and SHLX, the shift-amount specified in rb is masked to 5 bits for 32-bit operand size and 6 bits for 64-bit operand size.
SHRX ra,r/m,rb	VEX.LZ.F2.0F38 F7 /r	Logical shift right without updating flags.
SHLX ra,r/m,rb	VEX.LZ.66.0F38 F7 /r	Shift left without updating flags.

	// There is no 'rolx', so for rol, we use rorx with the shift value adjusted.
	if (tree->OperIs(GT_ROL))
	{
	shiftByValue &= (size * BITS_PER_BYTE - 1);
	shiftByValue = (size * BITS_PER_BYTE - shiftByValue);
	}

	inst_RV_TT_IV(INS_rorx, size, tree->GetRegNum(), operand, shiftByValue, INS_OPTS_NONE);

JIT: Add morphing to LE_UN/GT_UN(expr, uint.MaxValue) (dotnet#76525) #113037

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JIT: Add morphing to LE_UN/GT_UN(expr, uint.MaxValue) (dotnet#76525) #113037

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