Thanks to visit codestin.com
Credit goes to github.com

Skip to content

[RISC-V] Introduce Zbs #115335

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Jump to bottom
Draft
wants to merge 4 commits into
base: main
Choose a base branch
from
Draft

[RISC-V] Introduce Zbs #115335

wants to merge 4 commits into from
+299 −18

Conversation

tomeksowi
Copy link
Contributor

@tomeksowi tomeksowi commented May 6, 2025 •
edited
Loading

Single-bit instructions

WiP: more lowerings

Part of #84834, cc @dotnet/samsung

@dotnet-issue-labeler dotnet-issue-labeler bot added the area-CodeGen-coreclr CLR JIT compiler in src/coreclr/src/jit and related components such as SuperPMI label May 6, 2025
@dotnet-policy-service dotnet-policy-service bot added the community-contribution Indicates that the PR has been added by a community member label May 6, 2025
@dotnet-policy-service Dotnet Policy Service
Copy link
Contributor

Tagging subscribers to this area: @JulieLeeMSFT, @jakobbotsch
See info in area-owners.md if you want to be subscribed.

@am11 am11 added the arch-riscv Related to the RISC-V architecture label May 6, 2025
am11
am11 reviewed May 6, 2025
View reviewed changes
src/coreclr/inc/jiteeversionguid.h
0x4506,
0x4fac,
{0x97, 0x35, 0xd0, 0x3b, 0xe1, 0xe7, 0xe9, 0x10}
};
Copy link
Member

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

nit: extra whitespace. Please run src/coreclr/tools/Common/JitInterface/ThunkGenerator/gen.sh per the comment above, it keeps things in sync.

@risc-vv
Copy link

risc-vv commented May 6, 2025 •
edited
Loading

RISC-V Release-CLR-QEMU: 9064 / 9094 (99.67%) 
=======================
      passed: 9064
      failed: 2
     skipped: 597
      killed: 28
------------------------
 TOTAL tests: 9691
VIRTUAL time: 29h 37min 35s 909ms
   REAL time: 42min 51s 362ms
=======================

report.xml, report.md, failures.xml, testclr_details.tar.zst

Build information and commands

GIT: 2eb54ac5eb825abb358b05a8147a6cd44a0c6f7f
CI: fb90762a15dc605159873a3c1988381b6a288350
REPO: tomeksowi/runtime
BRANCH: zbs
CONFIG: Release
LIB_CONFIG: Release

RISC-V Release-FX-QEMU: 284444 / 285527 (99.62%) 
=======================
      passed: 284444
      failed: 1077
     skipped: 38
      killed: 6
------------------------
 TOTAL tests: 285565
VIRTUAL time: 26h 15min 16s 695ms
   REAL time: 1h 10min 48s 483ms
=======================

report.xml, report.md, failures.xml, testclr_details.tar.zst

Build information and commands

GIT: 2eb54ac5eb825abb358b05a8147a6cd44a0c6f7f
CI: fb90762a15dc605159873a3c1988381b6a288350
REPO: tomeksowi/runtime
BRANCH: zbs
CONFIG: Release
LIB_CONFIG: Release

RISC-V Release-CLR-VF2: 9063 / 9093 (99.67%) 
=======================
      passed: 9063
      failed: 2
     skipped: 597
      killed: 28
------------------------
 TOTAL tests: 9690
VIRTUAL time: 10h 35min 3s 934ms
   REAL time: 47min 4s 120ms
=======================

report.xml, report.md, failures.xml, testclr_details.tar.zst

Build information and commands

GIT: 2eb54ac5eb825abb358b05a8147a6cd44a0c6f7f
CI: fb90762a15dc605159873a3c1988381b6a288350
REPO: tomeksowi/runtime
BRANCH: zbs
CONFIG: Release
LIB_CONFIG: Release

This was referenced May 6, 2025
Open
Open
Open
Open
rhuijben
rhuijben reviewed May 6, 2025
View reviewed changes
src/coreclr/tools/Common/Compiler/HardwareIntrinsicHelpers.cs
@@ -339,13 +339,16 @@ private static class RiscV64IntrinsicConstants
{
public const int Zba = 0x0001;
public const int Zbb = 0x0002;
public const int Zbs = 0x0003;
Copy link

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

This looks like an unlikely value? 0x0004 would check the next bit. Now you just check if one of the above values or both are set.

Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment
Reviewers

@rhuijben rhuijben rhuijben left review comments

@am11 am11 am11 left review comments

@MichalStrehovsky MichalStrehovsky Awaiting requested review from MichalStrehovsky MichalStrehovsky will be requested when the pull request is marked ready for review MichalStrehovsky is a code owner

At least 1 approving review is required to merge this pull request.

Assignees
No one assigned
Labels
arch-riscv Related to the RISC-V architecture area-CodeGen-coreclr CLR JIT compiler in src/coreclr/src/jit and related components such as SuperPMI community-contribution Indicates that the PR has been added by a community member
Projects
None yet
Milestone
No milestone
Development

Successfully merging this pull request may close these issues.
4 participants
@tomeksowi @risc-vv @rhuijben @am11