Reuse AlignLoops flag for dynamic loop alignment

dotnet · kunalspathak · Jan 12, 2021 · Oct 8, 2020 · Oct 9, 2020 · Oct 9, 2020
commit a51759af6c6d327309736c029d7da22e8931e23f
diff --git a/src/coreclr/jit/codegenlinear.cpp b/src/coreclr/jit/codegenlinear.cpp
@@ -311,13 +311,6 @@ void CodeGen::genCodeForBBlist()
 
         genUpdateCurrentFunclet(block);
 
-#ifdef TARGET_XARCH
-        if (ShouldAlignLoops() && block->bbFlags & BBF_LOOP_HEAD)
-        {
-            GetEmitter()->emitLoopAlign();
-        }
-#endif
-
         genLogLabel(block);
 
         // Tell everyone which basic block we're working on
@@ -750,13 +743,17 @@ void CodeGen::genCodeForBBlist()
                 break;
         }
 
-        if ((block != nullptr) && (block->bbNext != nullptr) && (block->bbNext->bbFlags & BBF_FIRST_BLOCK_IN_INNERLOOP))
+        if (ShouldAlignLoops())
         {
-            if (verbose)
+            if ((block->bbNext != nullptr) && (block->bbNext->bbFlags & BBF_FIRST_BLOCK_IN_INNERLOOP))
             {
-                printf("To align next block, add padding.\n");
+                if (verbose)
+                {
+                    printf("To align next block, add padding.\n");
+                }
+                //GetEmitter()->emitIns_Nop(10);
+                GetEmitter()->emitLoopAlign();
             }
-            GetEmitter()->emitIns_Nop(10);
         }
 
 #if defined(DEBUG) && defined(USING_VARIABLE_LIVE_RANGE)

diff --git a/src/coreclr/jit/emitarm.cpp b/src/coreclr/jit/emitarm.cpp
@@ -1473,13 +1473,11 @@ void emitter::emitIns(instruction ins)
  *  Add a NOP instructions to pad the instruction stream by (size / 4) bytes.
  */
 
-void emitter::emitIns_Nop(unsigned size)
+void emitter::emitLoopAlign()
 {
-    assert(size > 0);
     // Max out at 28 bytes of nop...
     // 32 is the largest method entry alignment we support.
-    size = size % 32; // TODO: should be different for arm64?
-    for (unsigned i = 0; i < size / 4; i++)
+    for (unsigned i = 0; i < 4; i++)
     {
         emitIns(INS_nop);
     }

diff --git a/src/coreclr/jit/emitarm.h b/src/coreclr/jit/emitarm.h
@@ -215,7 +215,7 @@ static bool emitIns_valid_imm_for_vldst_offset(int imm);
 
 void emitIns(instruction ins);
 
-void emitIns_Nop(unsigned size);
+void emitLoopAlign();
 
 void emitIns_I(instruction ins, emitAttr attr, target_ssize_t imm);
 

diff --git a/src/coreclr/jit/emitarm64.cpp b/src/coreclr/jit/emitarm64.cpp
@@ -3630,13 +3630,11 @@ void emitter::emitIns(instruction ins)
  *  Add a NOP instructions to pad the instruction stream by (size / 4) bytes.
  */
 
-void emitter::emitIns_Nop(unsigned size)
+void emitter::emitLoopAlign()
 {
-    assert(size > 0);
     // Max out at 28 bytes of nop...
     // 32 is the largest method entry alignment we support.
-    size = size % 32; //TODO: should be different for arm64?
-    for (unsigned i = 0; i < size / 4; i++)
+    for (unsigned i = 0; i < 4; i++)
     {
         emitIns(INS_nop);
     }

diff --git a/src/coreclr/jit/emitarm64.h b/src/coreclr/jit/emitarm64.h
@@ -723,7 +723,7 @@ inline static ssize_t computeRelPageAddr(size_t dstAddr, size_t srcAddr)
 public:
 void emitIns(instruction ins);
 
-void emitIns_Nop(unsigned size);
+void emitLoopAlign();
 
 void emitIns_I(instruction ins, emitAttr attr, ssize_t imm);