Thanks to visit codestin.com
Credit goes to github.com

Skip to content

[Arm64] Use SIMD register to zero init frame #46609

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Merged
merged 14 commits into from
Jan 26, 2021
Merged

[Arm64] Use SIMD register to zero init frame #46609

Changes from 1 commit
Commits
Show all changes
14 commits
Select commit Hold shift + click to select a range
990e727
Refactor CodeGen::genZeroInitFrame in src/coreclr/jit/codegencommon.cpp
echesakov Jan 6, 2021
4450dfe
Use stp q9, q9, <addr-reg> for zeroing a frame in CodeGen::genZeroIni…
echesakov Jan 6, 2021
6c30e8c
Fix comment for CodeGen::genInstrWithConstant in src/coreclr/jit/code…
echesakov Jan 7, 2021
085a1c5
Leave the TARGET_ARM implementation of CodeGen::genZeroInitFrame asid…
echesakov Jan 7, 2021
4e6f31b
Format comment in CodeGen::genZeroInitFrame in src/coreclr/jit/codege…
echesakov Jan 7, 2021
c7e3936
Re-implement CodeGen::genZeroInitFrame() in src/coreclr/jit/codegenco…
echesakov Jan 8, 2021
a675e99
Implement GetDataCacheZeroIDReg() helper and use it to set Instructio…
echesakov Jan 20, 2021
062664e
Add InstructionSet_Dczva in src/coreclr/inc/corinfoinstructionset.h s…
echesakov Jan 20, 2021
5d10b15
Implement DC ZVA instruction in coreclr/jit/emitarm64.cpp src/coreclr…
echesakov Jan 20, 2021
527a5fc
Allow second operand of BFM instruction to be XZR or WZR in src/corec…
echesakov Jan 20, 2021
520e6db
Use DC ZVA for regions >= 320 bytes in src/coreclr/jit/codegencommon.…
echesakov Jan 20, 2021
7568476
Use DC ZVA for memory regions >= 256 bytes in src/coreclr/jit/codegen…
echesakov Jan 21, 2021
b472cc9
Update comment in CodeGen::genZeroInitFrame in src/coreclr/jit/codege…
echesakov Jan 26, 2021
2352f16
Update JIT/EE interface GUID in jiteeversionguid.h
echesakov Jan 26, 2021
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
Prev Previous commit
Next Next commit
Update comment in CodeGen::genZeroInitFrame in src/coreclr/jit/codege… 
…ncommon.cpp
  • Loading branch information
@echesakov
echesakov committed Jan 26, 2021
commit b472cc9714d542f0dbe80b9b70706665a842a848
2 changes: 1 addition & 1 deletion src/coreclr/jit/codegencommon.cpp
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -6308,7 +6308,7 @@ void CodeGen::genZeroInitFrame(int untrLclHi, int untrLclLo, regNumber initReg,
{
// Generates the following code:
//
// When the size of the region is greater than or equal to 320 bytes
// When the size of the region is greater than or equal to 256 bytes
// **and** DC ZVA instruction use is permitted
// **and** the instruction block size is configured to 64 bytes:
//
Expand Down