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5f12506
Fixed improper peephole zero-extension removal when cdq/cdqe/cwde ins…
TIHan Feb 27, 2023
cf0bdf2
Update regression test
TIHan Feb 27, 2023
697dfdc
Formatting
TIHan Feb 27, 2023
f78c28d
Handle cdq differently
TIHan Feb 27, 2023
b6467cb
Handle cdq differently
TIHan Feb 27, 2023
334fc46
Handle cdq differently
TIHan Feb 27, 2023
47eb762
Initial commit to eliminate redundant 'cmp' instructions
TIHan Feb 28, 2023
ef8688b
Take into account cmpxchg
TIHan Feb 28, 2023
2184607
Take into account cmpxchg
TIHan Feb 28, 2023
25ac969
Feedback
TIHan Feb 28, 2023
2cc3541
Temporarily disable cmp opt if we encounter a mov
TIHan Mar 1, 2023
1013666
Merge remote-tracking branch 'upstream/main' into redundant-cmp-opt
TIHan Mar 1, 2023
15e6462
Merge branch 'redundant-cmp-opt' of https://github.com/TIHan/runtime …
TIHan Mar 1, 2023
3218581
Allow checking for mov
TIHan Mar 1, 2023
e5e2599
Allow regardless of targetReg
TIHan Mar 1, 2023
baee67f
Allow regardless of targetReg
TIHan Mar 1, 2023
0827dc3
Merge branch 'zero-extend-fix' into redundant-cmp-opt
TIHan Mar 1, 2023
03e4f8b
Checking if an instruction resets a flag.
TIHan Mar 1, 2023
5058e59
Remove useless comment
TIHan Mar 1, 2023
0ba01ef
Minor fix
TIHan Mar 1, 2023
8d8485e
Abort are checking cmp
TIHan Mar 2, 2023
49b6f27
Some refactoring. Taking into account any instruction that modifies f…
TIHan Mar 3, 2023
49a8043
Minor cleanup
TIHan Mar 3, 2023
ee0cd47
Remove function from header
TIHan Mar 3, 2023
91c1054
Quick fix
TIHan Mar 3, 2023
1c5f518
Sync
TIHan Mar 4, 2023
f74a895
Merge
TIHan Mar 6, 2023
61ee9da
Merge remote-tracking branch 'upstream/main' into redundant-cmp-opt
TIHan Apr 3, 2023
4d4e059
Formatting
TIHan Apr 3, 2023
03d9ab3
Only look for 'cmp reg, reg'
TIHan Apr 5, 2023
51c70a7
Added comment
TIHan Apr 5, 2023
3dd723f
Update src/coreclr/jit/emitxarch.cpp
TIHan Apr 5, 2023
0cb00b4
Update src/coreclr/jit/emitxarch.cpp
TIHan Apr 5, 2023
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Quick fix
  • Loading branch information
TIHan committed Mar 3, 2023
commit 91c1054aa7c3a5d732ddcf5bed85d3536cd33757
153 changes: 19 additions & 134 deletions src/coreclr/jit/emitxarch.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -504,157 +504,42 @@ bool emitter::AreUpper32BitsZero(regNumber reg)

bool result = false;

emitPeepholeIterateLastInstrs([&](instrDesc* id) {
switch ((ID_OPS)emitFmtToOps[id->idInsFmt()])
{
// This is conservative.
case ID_OP_CALL:
return PEEPHOLE_ABORT;

default:
break;
}

// This is a special case for idiv, div, imul, and mul.
// They always write to RAX and RDX.
if (instrHasImplicitRegPairDest(id->idIns()))
{
if (reg == REG_RAX || reg == REG_RDX)
{
result = (id->idOpSize() == EA_4BYTE);
return PEEPHOLE_ABORT;
}
}

// This is a special case for cdq/cwde/cmpxchg.
if (instrHasImplicitRegSingleDest(id->idIns()))
emitPeepholeIterateLastInstrs(
[&](instrDesc* id)
{
switch (id->idIns())
if (emitIsInstrWritingToReg(id, reg))
{
case INS_cwde:
case INS_cmpxchg:
switch (id->idIns())
{
if (reg == REG_RAX)
{
// Conservative.
case INS_call:
return PEEPHOLE_ABORT;
}
break;
}

case INS_cdq:
{
if (reg == REG_RDX)
{
// These instructions sign-extend.
case INS_cwde:
case INS_cdq:
case INS_movsx:
case INS_movsxd:
return PEEPHOLE_ABORT;
}
break;
}

default:
break;
}
}

switch (id->idInsFmt())
{
case IF_RWR:
case IF_RRW:

case IF_RWR_CNS:
case IF_RRW_CNS:
case IF_RRW_SHF:

case IF_RWR_RRD:
case IF_RRW_RRD:
case IF_RRW_RRW:
case IF_RRW_RRW_CNS:

case IF_RWR_RRD_RRD:
case IF_RWR_RRD_RRD_CNS:

case IF_RWR_RRD_RRD_RRD:

case IF_RWR_MRD:
case IF_RRW_MRD:
case IF_RRW_MRD_CNS:

case IF_RWR_RRD_MRD:
case IF_RWR_MRD_CNS:
case IF_RWR_RRD_MRD_CNS:
case IF_RWR_RRD_MRD_RRD:
case IF_RWR_MRD_OFF:

case IF_RWR_SRD:
case IF_RRW_SRD:
case IF_RRW_SRD_CNS:

case IF_RWR_RRD_SRD:
case IF_RWR_SRD_CNS:
case IF_RWR_RRD_SRD_CNS:
case IF_RWR_RRD_SRD_RRD:

case IF_RWR_ARD:
case IF_RRW_ARD:
case IF_RRW_ARD_CNS:

case IF_RWR_RRD_ARD:
case IF_RWR_ARD_CNS:
case IF_RWR_ARD_RRD:
case IF_RWR_RRD_ARD_CNS:
case IF_RWR_RRD_ARD_RRD:
{
if (id->idReg1() != reg)
{
switch (id->idInsFmt())
{
// Handles instructions who write to two registers.
case IF_RRW_RRW:
case IF_RRW_RRW_CNS:
{
if (id->idReg2() == reg)
{
result = (id->idOpSize() == EA_4BYTE);
return PEEPHOLE_ABORT;
}
break;
}

default:
break;
}

return PEEPHOLE_CONTINUE;
}

// movsx always sign extends to 8 bytes.
if (id->idIns() == INS_movsx)
{
return PEEPHOLE_ABORT;
}

if (id->idIns() == INS_movsxd)
{
return PEEPHOLE_ABORT;
}
// movzx always zeroes the upper 32 bits.
case INS_movzx:
result = true;
return PEEPHOLE_ABORT;

// movzx always zeroes the upper 32 bits.
if (id->idIns() == INS_movzx)
{
result = true;
return PEEPHOLE_ABORT;
default:
break;
}

// otherwise rely on operation size.
result = (id->idOpSize() == EA_4BYTE);
return PEEPHOLE_ABORT;
}

default:
else
{
return PEEPHOLE_CONTINUE;
}
}
});
});

return result;
}
Expand Down