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24 changes: 24 additions & 0 deletions src/coreclr/jit/emitxarch.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -6081,6 +6081,30 @@ bool emitter::IsJmpInstruction(instruction ins)
return (ins == INS_i_jmp) || (ins == INS_jmp) || (ins == INS_l_jmp) || (ins == INS_tail_i_jmp);
}

//------------------------------------------------------------------------
// IsBitwiseInstruction: Determine if an instruction is a bit-wise instruction.
//
// Arguments:
// ins -- The instruction being checked
//
// Return Value:
// true if the instruction qualifies; otherwise, false
//
bool emitter::IsBitwiseInstruction(instruction ins)
{
switch (ins)
{
case INS_pand:
case INS_pandn:
case INS_por:
case INS_pxor:
return true;

default:
return false;
}
}

// TODO-XArch-CQ: There are places where the fact that an instruction zero-extends
// is not an important detail, such as when "regular" floating-point code is generated
//
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1 change: 1 addition & 0 deletions src/coreclr/jit/emitxarch.h
Original file line number Diff line number Diff line change
Expand Up @@ -145,6 +145,7 @@ bool IsRedundantStackMov(instruction ins, insFormat fmt, emitAttr size, regNumbe

static bool IsJccInstruction(instruction ins);
static bool IsJmpInstruction(instruction ins);
static bool IsBitwiseInstruction(instruction ins);

#ifdef TARGET_64BIT
bool AreUpperBitsZero(regNumber reg, emitAttr size);
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