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volatile int x;

void Test() => x = 42;

; Assembly listing for method Program:Test()
            stp     fp, lr, [sp, #-0x10]!
            mov     fp, sp
            mov     w1, #42
-           dmb     ish
-           str     w1, [x0, #0x08]
+           stlur   w1, [x0, #0x08]
            ldp     fp, lr, [sp], #0x10
            ret     lr

@TIHan @dotnet/jit-contrib PTAL, it's a follow-up to #89681 but for stores.

TLDR: on arm64-v8.4 we can use stlur instead of strl or str+dmb because the former now supports IMM offsets. stlur, just like ldapur, has acquire-release semantics which matches our memory model expectations.

also, cc @VSadov

Will this need a fix similar to #91668?

Will this need a fix similar to #91668?

I'd guess - yes? since it's the same ISA.

//  stlur  1X011001000iiiii iiii00nnnnnttttt  9900 0000   [Xn imm(-256..+255)] ARMv8.4 RCPC2
//  stlurb 00011001000iiiii iiii00nnnnnttttt  1900 0000   [Xn imm(-256..+255)] ARMv8.4 RCPC2
//  stlurh 01011001000iiiii iiii00nnnnnttttt  5900 0000   [Xn imm(-256..+255)] ARMv8.4 RCPC2

doc: https://developer.arm.com/documentation/ddi0602/2023-06/Base-Instructions/STLUR--Store-Release-Register--unscaled--?lang=en

can you add them as well?

doc: https://developer.arm.com/documentation/ddi0602/2023-06/Base-Instructions/STLUR--Store-Release-Register--unscaled--?lang=en

can you add them as well?

Done (but untested)

@BruceForstall PTAL refactored changes