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ARM64: Enable jumptable to BT optimization #91811

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Merged
merged 5 commits into from
Sep 9, 2023
Merged

ARM64: Enable jumptable to BT optimization #91811

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9094b6a
Enable TryLowerSwitchToBitTest for arm64
EgorBo Sep 8, 2023
9e41c62
Code format
EgorBo Sep 8, 2023
5aa7025
Fix build on arm32
EgorBo Sep 8, 2023
b062f63
test
EgorBo Sep 8, 2023
c125033
Clean up
EgorBo Sep 9, 2023
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31 changes: 19 additions & 12 deletions src/coreclr/jit/lower.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -1150,10 +1150,6 @@ GenTree* Lowering::LowerSwitch(GenTree* node)
bool Lowering::TryLowerSwitchToBitTest(
BasicBlock* jumpTable[], unsigned jumpCount, unsigned targetCount, BasicBlock* bbSwitch, GenTree* switchValue)
{
#ifndef TARGET_XARCH
// Other architectures may use this if they substitute GT_BT with equivalent code.
return false;
#else
assert(jumpCount >= 2);
assert(targetCount >= 2);
assert(bbSwitch->bbJumpKind == BBJ_SWITCH);
Expand Down Expand Up @@ -1223,7 +1219,7 @@ bool Lowering::TryLowerSwitchToBitTest(
return false;
}

#ifdef TARGET_64BIT
#if defined(TARGET_64BIT) && defined(TARGET_XARCH)
//
// See if we can avoid a 8 byte immediate on 64 bit targets. If all upper 32 bits are 1
// then inverting the bit table will make them 0 so that the table now fits in 32 bits.
Expand Down Expand Up @@ -1270,20 +1266,31 @@ bool Lowering::TryLowerSwitchToBitTest(
comp->fgAddRefPred(bbCase1, bbSwitch);
}

var_types bitTableType = (bitCount <= (genTypeSize(TYP_INT) * 8)) ? TYP_INT : TYP_LONG;
GenTree* bitTableIcon = comp->gtNewIconNode(bitTable, bitTableType);

#ifdef TARGET_XARCH
//
// Append BT(bitTable, switchValue) and JCC(condition) to the switch block.
//

var_types bitTableType = (bitCount <= (genTypeSize(TYP_INT) * 8)) ? TYP_INT : TYP_LONG;
GenTree* bitTableIcon = comp->gtNewIconNode(bitTable, bitTableType);
GenTree* bitTest = comp->gtNewOperNode(GT_BT, TYP_VOID, bitTableIcon, switchValue);
GenTree* bitTest = comp->gtNewOperNode(GT_BT, TYP_VOID, bitTableIcon, switchValue);
bitTest->gtFlags |= GTF_SET_FLAGS;
GenTreeCC* jcc = comp->gtNewCC(GT_JCC, TYP_VOID, bbSwitchCondition);

LIR::AsRange(bbSwitch).InsertAfter(switchValue, bitTableIcon, bitTest, jcc);

#else // TARGET_XARCH
//
// Fallback to AND(RSZ(bitTable, switchValue), 1)
//
GenTree* tstCns = comp->gtNewIconNode(bbSwitch->bbNext != bbCase0 ? 0 : 1, bitTableType);
GenTree* shift = comp->gtNewOperNode(GT_RSZ, bitTableType, bitTableIcon, switchValue);
GenTree* one = comp->gtNewIconNode(1, bitTableType);
GenTree* andOp = comp->gtNewOperNode(GT_AND, bitTableType, shift, one);
GenTree* cmp = comp->gtNewOperNode(GT_EQ, TYP_INT, andOp, tstCns);
GenTree* jcc = comp->gtNewOperNode(GT_JTRUE, TYP_VOID, cmp);
LIR::AsRange(bbSwitch).InsertAfter(switchValue, bitTableIcon, shift, tstCns, one);
LIR::AsRange(bbSwitch).InsertAfter(one, andOp, cmp, jcc);
#endif // !TARGET_XARCH
Comment on lines +1272 to +1292
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Why do we still need the xarch special case? Does OptimzeConstCompare not handle the case? Ideally we would teach it about the missing opportunity so that everyone benefits instead of special casing it here

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@EgorBo EgorBo Sep 9, 2023 •
edited
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I thought about it, but I'd like to leave it for a future follow up since it involves more work to add that peephole and I was mainly interested in improving arm64

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Ah, you mean that the peephole already exists?

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Ok, sounds fine to me. I would personally expect x & (1 << y) to be quite common, and it looks like we are missing this opportunity for arm64 (TEST_EQ/TEST_NE(x, LSH(1, y)) => TEST_EQ/TEST_NE(RSZ(x, y), 1)). Then this transform could produce EQ/NE(AND(x, LSH(1, y)))

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I don't think it exists, but it seems like adding it here would be straightforward:

runtime/src/coreclr/jit/lower.cpp

Lines 3596 to 3621 in e04c75e

#ifdef TARGET_XARCH
if (cmp->OperIs(GT_TEST_EQ, GT_TEST_NE))
{
//
// Transform TEST_EQ|NE(x, LSH(1, y)) into BT(x, y) when possible. Using BT
// results in smaller and faster code. It also doesn't have special register
// requirements, unlike LSH that requires the shift count to be in ECX.
// Note that BT has the same behavior as LSH when the bit index exceeds the
// operand bit size - it uses (bit_index MOD bit_size).
//
GenTree* lsh = cmp->gtGetOp2();
if (lsh->OperIs(GT_LSH) && varTypeIsIntOrI(lsh->TypeGet()) && lsh->gtGetOp1()->IsIntegralConst(1))
{
cmp->SetOper(cmp->OperIs(GT_TEST_EQ) ? GT_BITTEST_EQ : GT_BITTEST_NE);
cmp->AsOp()->gtOp2 = lsh->gtGetOp2();
cmp->gtGetOp2()->ClearContained();
BlockRange().Remove(lsh->gtGetOp1());
BlockRange().Remove(lsh);
return cmp->gtNext;
}
}
#endif // TARGET_XARCH

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Of course we could also teach it about TEST_EQ/TEST_NE(RSZ(x, y), 1) => BT(x, y) on x64/x86, but I guess this is a less common pattern

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Anyway I'm ok with keeping this PR as is.

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@jakobbotsch ok let's then keep as is and I'll file a "good-first-issue" to recognize BT pattern (or will work myself when I have time)

return true;
#endif // TARGET_XARCH
}

void Lowering::ReplaceArgWithPutArgOrBitcast(GenTree** argSlot, GenTree* putArgOrBitcast)
Expand Down