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045be18
[mono][interp] Preliminary phases for SSA computation
BrzVlad Nov 6, 2023
37d98ea
[mono][interp] Insert phi nodes
BrzVlad Nov 6, 2023
909d2d9
[mono][interp] Implement renaming of vars
BrzVlad Nov 7, 2023
96e92f9
[mono][interp] Re-enable bblock optimizations
BrzVlad Nov 7, 2023
d7804e4
[mono][interp] Add liveness computation so we can generate pruned SSA
BrzVlad Nov 8, 2023
45dd009
[mono][interp] Reduce number of fixed ssa vars
BrzVlad Nov 8, 2023
00a772d
[mono][interp] Add more stats tracking compilation time
BrzVlad Nov 8, 2023
7366107
[mono][interp] Compute live end limit for fixed ssa vars
BrzVlad Nov 8, 2023
4104c95
[mono][interp] Ensure all vars have a definition
BrzVlad Nov 8, 2023
09b629f
[mono][interp] Resurrect cprop, cfold and some other small optimizations
BrzVlad Nov 8, 2023
d053d1c
[mono][interp] Bring back deadce
BrzVlad Nov 9, 2023
c210c2f
[mono][interp] Resurrect super instruction pass
BrzVlad Nov 9, 2023
ca9094b
[mono][interp] Redo bblock opt pass after other optimizations
BrzVlad Nov 9, 2023
5ab1755
[mono][interp] Re-enable MINT_INTRINS_MARVIN_BLOCK intrinsic
BrzVlad Nov 9, 2023
b5d3bdd
[mono][interp] Bring back reverse propagation of dreg
BrzVlad Nov 9, 2023
1eb1627
[mono][interp] Fix SSA form for vt field stores
BrzVlad Nov 10, 2023
c88eeae
[mono][interp] Redo optimizations if a var is no longer indirect
BrzVlad Nov 13, 2023
6004987
[mono][interp] Disable ssa optimizations for methods with bad cfg str…
BrzVlad Nov 22, 2023
0422ae5
[mono][interp] Scan also bblocks reachable from EH
BrzVlad Nov 22, 2023
5498668
[mono][interp] Mark vars used inside handlers so they are not transfo…
BrzVlad Nov 14, 2023
df43e38
[mono][interp] Bring back optimizations for variables that are not in…
BrzVlad Nov 27, 2023
b312bb8
[mono][interp] Proper support for ssa disabled
BrzVlad Nov 29, 2023
c30c8d5
[mono][interp] Enable cprop dreg optimization for no-ssa vars
BrzVlad Dec 1, 2023
c9d086f
[mono][interp] Fix handling of BBs with patchpoint data during optimi…
BrzVlad Dec 5, 2023
4ccb8be
[mono][interp] Fix diverging var offsets between tiered and untiered …
BrzVlad Dec 6, 2023
82e5124
[mono][interp] Retry instruction during cprop when replacing with MOV
BrzVlad Dec 13, 2023
0c576b8
[mono][interp] Rename get_local_offset to get_var_offset
BrzVlad Dec 13, 2023
5d47373
[mono][interp] Squash multiple INITLOCAL into single INITLOCALS
BrzVlad Dec 13, 2023
80e189b
[mono][interp] Fix cprop dreg with newobj
BrzVlad Dec 14, 2023
c34c1d9
[mono][interp] Fix u1 narrow simd intrinsic
BrzVlad Dec 20, 2023
ec7b3a2
[mono][interp] Attempt to remove bblocks from EH
BrzVlad Dec 20, 2023
cc660c4
[mono][interp] Remove bblock count limit for optimization support
BrzVlad Dec 21, 2023
3e2ee71
[mono][interp] Improve native offset estimation
BrzVlad Dec 25, 2023
10851ef
[mono][interp] Fix live limit bblocks computation for fixed ssa vars
BrzVlad Dec 23, 2023
0ab313b
[mono][interp] Reduce number of renamable vars
BrzVlad Dec 27, 2023
3fcf0db
[mono][interp] Remove MINT_NOPS after each round of optimizations
BrzVlad Dec 28, 2023
22b6444
[mono][interp] Optimize generation of MINT_DEAD_PHI
BrzVlad Dec 28, 2023
fcb91d0
[mono][interp] Disable SSA for first optimization iteration of huge m…
BrzVlad Dec 28, 2023
f462966
[mono][interp] Fix adding of super instructions
BrzVlad Jan 9, 2024
4f776d3
[mono][interp] Refactor dfs traversal to be iterative
BrzVlad Jan 9, 2024
ff8ef69
[mono][interp] Make rename vars pass non-recursive
BrzVlad Jan 10, 2024
ee0e148
[mono][interp] Make use of dfs_index in more places
BrzVlad Jan 10, 2024
0b9ad9e
[mono][interp] Don't run any optimizations if we have cprop disabled
BrzVlad Jan 11, 2024
67b089a
[mono][interp] Reduce max memory usage during interp compilation
BrzVlad Jan 12, 2024
ad70884
PR review
BrzVlad Jan 26, 2024
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[mono][interp] Enable cprop dreg optimization for no-ssa vars
This works in a limited fashion, only if the definition and the move are adjacent, as it was working before the SSA change. This is intended to improve codegen quality inside finally blocks.
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BrzVlad committed Jan 31, 2024
commit c30c8d5f5bd8c0a824906d965a2071a68e1e3cdd
112 changes: 69 additions & 43 deletions src/mono/mono/mini/interp/transform-opt.c
Original file line number Diff line number Diff line change
Expand Up @@ -2466,6 +2466,50 @@ cprop_svar (TransformData *td, InterpInst *ins, int *pvar, guint32 current_liven
}
}

static gboolean
can_cprop_dreg (TransformData *td, InterpInst *mov_ins)
{
int dreg = mov_ins->dreg;
int sreg = mov_ins->sregs [0];

// sreg = def
// mov sreg -> dreg

InterpVarValue *sreg_val = get_var_value (td, sreg);
if (!sreg_val)
return FALSE;
// We only apply this optimization if the definition is in the same bblock as this use
if ((sreg_val->liveness >> INTERP_LIVENESS_INS_INDEX_BITS) != td->cbb->index)
return FALSE;
if (td->var_values [sreg].def->opcode == MINT_DEF_ARG)
return FALSE;
// reordering moves might break conversions
if (td->vars [dreg].mt != td->vars [sreg].mt)
return FALSE;

if (var_is_ssa_form (td, sreg)) {
// check if dreg is a renamed ssa fixed var (likely to remain alive)
if (td->vars [dreg].renamed_ssa_fixed && !td->vars [sreg].renamed_ssa_fixed) {
int last_use_liveness = td->renamable_vars [td->renamed_fixed_vars [td->vars [dreg].ext_index].renamable_var_ext_index].last_use_liveness;
if ((last_use_liveness >> INTERP_LIVENESS_INS_INDEX_BITS) != td->cbb->index ||
sreg_val->liveness >= last_use_liveness) {
// No other conflicting renamed fixed vars (of dreg) are used in this bblock, or their
// last use predates the definition. This means we can tweak def of sreg to store directly
// into dreg and patch all intermediary instructions to use dreg instead.
return TRUE;
}
}
} else if (!var_is_ssa_form (td, dreg)) {
// Neither sreg nor dreg are in SSA form. IL globals are likely to remain alive
// We ensure that stores to no SSA vars, that are il globals, are not reordered.
// For simplicity, we apply the optimization only if the def and move are adjacent.
if (td->vars [dreg].il_global && !td->vars [sreg].il_global && mov_ins == interp_next_ins (sreg_val->def))
return TRUE;
}

return FALSE;
}

static void
interp_cprop (TransformData *td)
{
Expand Down Expand Up @@ -2574,50 +2618,32 @@ interp_cprop (TransformData *td)
g_print ("cprop loc %d -> ct :\n\t", sreg);
interp_dump_ins (ins, td->data_items);
}
} else if (td->vars [dreg].renamed_ssa_fixed && !td->vars [sreg].renamed_ssa_fixed &&
var_is_ssa_form (td, sreg) &&
td->vars [dreg].mt == td->vars [sreg].mt && // reordering moves might break conversions
td->var_values [sreg].def->opcode != MINT_DEF_ARG &&
(td->var_values [sreg].liveness >> INTERP_LIVENESS_INS_INDEX_BITS) == bb->index) {
// dreg is a renamed ssa fixed var (likely to remain alive) and the definition of sreg
// is in this current bblock.
int last_use_liveness = td->renamable_vars [td->renamed_fixed_vars [td->vars [dreg].ext_index].renamable_var_ext_index].last_use_liveness;
if ((last_use_liveness >> INTERP_LIVENESS_INS_INDEX_BITS) != bb->index ||
td->var_values [sreg].liveness >= last_use_liveness) {
// No other conflicting renamed fixed vars are used in this bblock, or their last use
// predates the definition. This means we can tweak def of sreg to store directly
// into dreg and patch all intermediary instructions to use dreg instead.
int dreg_ref_count = td->var_values [dreg].ref_count;
td->var_values [dreg] = td->var_values [sreg];
td->var_values [dreg].ref_count = dreg_ref_count;
td->var_values [dreg].def->dreg = dreg;
} else if (can_cprop_dreg (td, ins)) {
int dreg_ref_count = td->var_values [dreg].ref_count;
td->var_values [dreg] = td->var_values [sreg];
td->var_values [dreg].ref_count = dreg_ref_count;
td->var_values [dreg].def->dreg = dreg;

if (td->verbose_level) {
g_print ("cprop fixed dreg %d:\n\t", dreg);
interp_dump_ins (td->var_values [dreg].def, td->data_items);
}
// Overwrite all uses of sreg with dreg up to this point
replace_svar_uses (td, td->var_values [dreg].def->next, ins, sreg, dreg);

// Transform `mov dreg <- sreg` into `mov sreg <- dreg` in case sreg is still used
ins->dreg = sreg;
ins->sregs [0] = dreg;
td->var_values [dreg].ref_count++;
td->var_values [sreg].ref_count--;

td->var_values [sreg].def = ins;
td->var_values [sreg].type = VAR_VALUE_OTHER_VAR;
td->var_values [sreg].var = dreg;
td->var_values [sreg].liveness = current_liveness;
if (td->verbose_level) {
g_print ("\t");
interp_dump_ins (ins, td->data_items);
}
} else {
if (td->verbose_level)
g_print ("local copy %d <- %d\n", dreg, sreg);
td->var_values [dreg].type = VAR_VALUE_OTHER_VAR;
td->var_values [dreg].var = sreg;
if (td->verbose_level) {
g_print ("cprop fixed dreg %d:\n\t", dreg);
interp_dump_ins (td->var_values [dreg].def, td->data_items);
}
// Overwrite all uses of sreg with dreg up to this point
replace_svar_uses (td, td->var_values [dreg].def->next, ins, sreg, dreg);

// Transform `mov dreg <- sreg` into `mov sreg <- dreg` in case sreg is still used
ins->dreg = sreg;
ins->sregs [0] = dreg;
td->var_values [dreg].ref_count++;
td->var_values [sreg].ref_count--;

td->var_values [sreg].def = ins;
td->var_values [sreg].type = VAR_VALUE_OTHER_VAR;
td->var_values [sreg].var = dreg;
td->var_values [sreg].liveness = current_liveness;
if (td->verbose_level) {
g_print ("\t");
interp_dump_ins (ins, td->data_items);
}
} else {
if (td->verbose_level)
Expand Down