verif_utils

Verification utilities that should help with Pre-Silicon Testbench development are listed below. Click on the links to get the details:

1. User Data from File
   At the start of the verification process, before scoreboards are established, a fixed incremental data pattern is often used as a stimulus for the design. This approach aids in debugging if any issues arise. The data typically consists of a stream of bytes, which can become complex when multiple streams, channels, or ports require unique identifiers within the pattern.

   

   The User Data From File verification utility simplifies this process by allowing users to input a text file as the stimulus for the design. Users can create or provide a text or log file as input to the design, and the output can similarly be converted into a human-readable format.

2. Clock Gate Checker
   A generic clock gate checker that can scale to accommodate any number of clocks. Once the clock gates are activated, the checker monitors for any toggling of the clocks and reports such occurrences as errors.

3. Memory Interface Checker
   A generic memory interface checker that can support any address or data width. Checkers are implemented for Single and Dual port RAMs with configurable read latencies.