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Odroidx next #3

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377cf9c
ODROID-X: hkdk4412: Add new hardware based on Exynos4412
Jul 30, 2012
f55cc8b
ARM: EXYNOS: Enable multiple cores on Exynos4
Jul 24, 2012
75c46fc
ARM: EXYNOS: Add gpio functions for Exynos4412
Jul 13, 2012
6a590ab
ARM: EXYNOS: Add USB HSIC device
Jul 28, 2012
b9df846
USB: misc: Add USB3503 High-Speed Hub Controller
Jul 27, 2012
c391264
ODROID-X: usb: Add USB3503 platform device
Jul 29, 2012
d56d9ef
ODROID-X: lcd: ADD LG LP101WH1 LCD
Jul 27, 2012
5827ac1
ODROID-X: lcd: Remove vertical lines of LP101WH1
Aug 6, 2012
4dcbdb2
ODROID-X: Add power-off callback
Jul 29, 2012
35497c6
ODROID-X: power: Add power POWERKEY event
Aug 5, 2012
6c33b79
Revert "PM / Domains: Allow device callbacks to be added at any time"
Aug 1, 2012
4c2b709
Revert "PM / Domains: Add device domain data reference counter"
Jul 29, 2012
1c9e121
s5p-tv: hdmi: Hack for fixing system-hang during S2RAM
trbehera Mar 15, 2012
55533d6
media: s5p-tv: Add audio support
trbehera May 2, 2012
29fc034
media: s5p-tv: Enable HDMI mode to support audio output
trbehera May 2, 2012
4075c17
HACK: media: s5p-tv: Temporary HDMI color hack
Apr 27, 2012
9f81f21
s5p-tv: Fix compiler warning in mixer_video.c file
Apr 3, 2012
0c4ff03
media: s5p-hdmi: add support for frame buffer emulator
mszyprow Mar 28, 2011
320b774
media: s5p-tv: Set 1080p output as default preset
trbehera Jun 20, 2012
4e7390d
media: vb2: add frame buffer emulator for video output devices
mszyprow Mar 29, 2011
32a9451
video: s3c-fb: Add device tree support
Mar 30, 2012
c86bfde
video: s3c-fb: Fix compile error/warning if CONFIG_OF is not selected
Aug 2, 2012
0b458a7
video: s3c-fb: Add Overlay Support
May 3, 2012
ca69f13
video: s3c-fb: Implement release function
May 4, 2012
4192e50
video: s3c-fb: Add open functionality
May 11, 2012
99113a2
ARM: SAMSUNG: Add API to set platform data for s5p-tv driver
trbehera Apr 5, 2012
81182db
ARM: EXYNOS: Add HDMIPHY I2C adaptor
Jul 27, 2012
716575f
ODROID-X: hdmi: Add HDMI platform device
Aug 6, 2012
392533c
ODROID-X: hdmi: Add HDMI driver for Exynos4212
Aug 6, 2012
d376a5d
ODROID-X: hdmi: Change HDMIPHY PLL config table
Aug 6, 2012
2c9dda2
ODROID-X: config: Add odroidx_defconfig
Jul 27, 2012
3b0da99
ODROIDX: board: Change regulator's visual names
Aug 12, 2012
244f1d8
ODROID-X: hsmmc: Remove unnecessary HSMMC3
Aug 12, 2012
e80dad8
ODROID-X: hsmmc: Remove hsmmc3 platform data
Aug 13, 2012
3ed84a5
mmc: dw_mmc: lookup for optional biu and ciu clocks
Jul 17, 2012
3d07c66
ODROID-X: dw_mmc: Exynos4 speicific code change
Aug 12, 2012
1a8a0cf
ARM: EXYNOS: Add DWMCI device
Aug 12, 2012
3efa0e5
ODROID-X: board: Add eMMC device support
Aug 13, 2012
4cc4db2
ODROID-X: config: Enable eMMC kernel config
Aug 13, 2012
bfc181d
ODROID-X: config: Enable Exynos4 CPU_FREQ driver
Aug 12, 2012
da91bde
ARM: EXYNOS: Remove unnecessary clock 'sclk_dwmmc'.
Aug 13, 2012
782a45c
ARM: EXYNOS: Add audio I2S clock control
Aug 13, 2012
3417d71
ASoC: Add max98090 CODEC driver
Aug 11, 2012
264d9fd
ASoC: HKDK: Add audio layer for ODROID
Aug 11, 2012
aaae637
ODROID-X: board: Add MAX98090 audio codec device
Aug 13, 2012
1b15681
ODROID-X: config: Enables MAX98090 audio codec
Aug 13, 2012
69957fb
Merge remote-tracking branch 'origin/odroidx-next' into odroidx-v3.6-rc2
Aug 17, 2012
aba5097
ODROID-X: config: Build config based on Linux 3.6-rc2
Aug 17, 2012
3e485be
ODROID-X: config: Remove Tickless System option
Aug 18, 2012
6dcac11
ODROID-X: config: Change DWMMC driver to be loadable
Aug 18, 2012
0a74022
Merge branch 'master' into github_odroidx-next
Aug 24, 2012
9f3eb6a
ODROIDX: config: Build config based on Linux 3.6-rc3
Aug 24, 2012
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media: s5p-tv: Add audio support 
This patch adds audio support in HDMI driver. This work is heavily based
on commit 3e148ba ("drm/exynos: enable hdmi audio feature").

Signed-off-by: Tushar Behera <[email protected]>
  • Loading branch information
@trbehera
trbehera authored and Dongjin Kim committed Aug 6, 2012
commit 55533d61b2328460cf0305d73308d1d5897c8858
163 changes: 163 additions & 0 deletions drivers/media/video/s5p-tv/hdmi_drv.c
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -174,6 +174,167 @@ static irqreturn_t hdmi_irq_handler(int irq, void *dev_data)
return IRQ_HANDLED;
}

/* Audio related changes */
static void hdmi_set_acr(u32 freq, u8 *acr)
{
u32 n, cts;

switch (freq) {
case 32000:
n = 4096;
cts = 27000;
break;
case 44100:
n = 6272;
cts = 30000;
break;
case 88200:
n = 12544;
cts = 30000;
break;
case 176400:
n = 25088;
cts = 30000;
break;
case 48000:
n = 6144;
cts = 27000;
break;
case 96000:
n = 12288;
cts = 27000;
break;
case 192000:
n = 24576;
cts = 27000;
break;
default:
n = 0;
cts = 0;
break;
}

acr[1] = cts >> 16;
acr[2] = cts >> 8 & 0xff;
acr[3] = cts & 0xff;

acr[4] = n >> 16;
acr[5] = n >> 8 & 0xff;
acr[6] = n & 0xff;
}

static void hdmi_reg_acr(struct hdmi_device *hdev, u8 *acr)
{
hdmi_writeb(hdev, HDMI_ACR_N0, acr[6]);
hdmi_writeb(hdev, HDMI_ACR_N1, acr[5]);
hdmi_writeb(hdev, HDMI_ACR_N2, acr[4]);
hdmi_writeb(hdev, HDMI_ACR_MCTS0, acr[3]);
hdmi_writeb(hdev, HDMI_ACR_MCTS1, acr[2]);
hdmi_writeb(hdev, HDMI_ACR_MCTS2, acr[1]);
hdmi_writeb(hdev, HDMI_ACR_CTS0, acr[3]);
hdmi_writeb(hdev, HDMI_ACR_CTS1, acr[2]);
hdmi_writeb(hdev, HDMI_ACR_CTS2, acr[1]);

hdmi_writeb(hdev, HDMI_ACR_CON, 4);
}

static void hdmi_audio_init(struct hdmi_device *hdev)
{
u32 sample_rate, bits_per_sample, frame_size_code;
u32 data_num, bit_ch, sample_frq;
u32 val;
u8 acr[7];

sample_rate = 44100;
bits_per_sample = 16;
frame_size_code = 0;

switch (bits_per_sample) {
case 20:
data_num = 2;
bit_ch = 1;
break;
case 24:
data_num = 3;
bit_ch = 1;
break;
default:
data_num = 1;
bit_ch = 0;
break;
}

hdmi_set_acr(sample_rate, acr);
hdmi_reg_acr(hdev, acr);

hdmi_writeb(hdev, HDMI_I2S_MUX_CON, HDMI_I2S_IN_DISABLE
| HDMI_I2S_AUD_I2S | HDMI_I2S_CUV_I2S_ENABLE
| HDMI_I2S_MUX_ENABLE);

hdmi_writeb(hdev, HDMI_I2S_MUX_CH, HDMI_I2S_CH0_EN
| HDMI_I2S_CH1_EN | HDMI_I2S_CH2_EN);

hdmi_writeb(hdev, HDMI_I2S_MUX_CUV, HDMI_I2S_CUV_RL_EN);

sample_frq = (sample_rate == 44100) ? 0 :
(sample_rate == 48000) ? 2 :
(sample_rate == 32000) ? 3 :
(sample_rate == 96000) ? 0xa : 0x0;

hdmi_writeb(hdev, HDMI_I2S_CLK_CON, HDMI_I2S_CLK_DIS);
hdmi_writeb(hdev, HDMI_I2S_CLK_CON, HDMI_I2S_CLK_EN);

val = hdmi_read(hdev, HDMI_I2S_DSD_CON) | 0x01;
hdmi_writeb(hdev, HDMI_I2S_DSD_CON, val);

/* Configuration I2S input ports. Configure I2S_PIN_SEL_0~4 */
hdmi_writeb(hdev, HDMI_I2S_PIN_SEL_0, HDMI_I2S_SEL_SCLK(5)
| HDMI_I2S_SEL_LRCK(6));
hdmi_writeb(hdev, HDMI_I2S_PIN_SEL_1, HDMI_I2S_SEL_SDATA1(3)
| HDMI_I2S_SEL_SDATA2(4));
hdmi_writeb(hdev, HDMI_I2S_PIN_SEL_2, HDMI_I2S_SEL_SDATA3(1)
| HDMI_I2S_SEL_SDATA2(2));
hdmi_writeb(hdev, HDMI_I2S_PIN_SEL_3, HDMI_I2S_SEL_DSD(0));

/* I2S_CON_1 & 2 */
hdmi_writeb(hdev, HDMI_I2S_CON_1, HDMI_I2S_SCLK_FALLING_EDGE
| HDMI_I2S_L_CH_LOW_POL);
hdmi_writeb(hdev, HDMI_I2S_CON_2, HDMI_I2S_MSB_FIRST_MODE
| HDMI_I2S_SET_BIT_CH(bit_ch)
| HDMI_I2S_SET_SDATA_BIT(data_num)
| HDMI_I2S_BASIC_FORMAT);

/* Configure register related to CUV information */
hdmi_writeb(hdev, HDMI_I2S_CH_ST_0, HDMI_I2S_CH_STATUS_MODE_0
| HDMI_I2S_2AUD_CH_WITHOUT_PREEMPH
| HDMI_I2S_COPYRIGHT
| HDMI_I2S_LINEAR_PCM
| HDMI_I2S_CONSUMER_FORMAT);
hdmi_writeb(hdev, HDMI_I2S_CH_ST_1, HDMI_I2S_CD_PLAYER);
hdmi_writeb(hdev, HDMI_I2S_CH_ST_2, HDMI_I2S_SET_SOURCE_NUM(0));
hdmi_writeb(hdev, HDMI_I2S_CH_ST_3, HDMI_I2S_CLK_ACCUR_LEVEL_2
| HDMI_I2S_SET_SMP_FREQ(sample_frq));
hdmi_writeb(hdev, HDMI_I2S_CH_ST_4,
HDMI_I2S_ORG_SMP_FREQ_44_1
| HDMI_I2S_WORD_LEN_MAX24_24BITS
| HDMI_I2S_WORD_LEN_MAX_24BITS);

hdmi_writeb(hdev, HDMI_I2S_CH_ST_CON, HDMI_I2S_CH_STATUS_RELOAD);
}

static void hdmi_audio_control(struct hdmi_device *hdev, bool onoff)
{
u32 mod;

mod = hdmi_read(hdev, HDMI_MODE_SEL);
if (mod & HDMI_MODE_DVI_EN)
return;

hdmi_writeb(hdev, HDMI_AUI_CON, onoff ? 2 : 0);
hdmi_write_mask(hdev, HDMI_CON_0, onoff ?
HDMI_ASP_EN : HDMI_ASP_DIS, HDMI_ASP_MASK);
}

static void hdmi_reg_init(struct hdmi_device *hdev)
{
/* enable HPD interrupts */
Expand Down Expand Up @@ -280,9 +441,11 @@ static int hdmi_conf_apply(struct hdmi_device *hdmi_dev)
mdelay(10);

hdmi_reg_init(hdmi_dev);
hdmi_audio_init(hdmi_dev);

/* setting core registers */
hdmi_timing_apply(hdmi_dev, conf);
hdmi_audio_control(hdmi_dev, true);

hdmi_dev->cur_conf_dirty = 0;

Expand Down
107 changes: 107 additions & 0 deletions drivers/media/video/s5p-tv/regs-hdmi.h
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -19,6 +19,7 @@

#define HDMI_CTRL_BASE(x) ((x) + 0x00000000)
#define HDMI_CORE_BASE(x) ((x) + 0x00010000)
#define HDMI_I2S_BASE(x) ((x) + 0x00040000)
#define HDMI_TG_BASE(x) ((x) + 0x00050000)

/* Control registers */
Expand Down Expand Up @@ -73,6 +74,20 @@
#define HDMI_VIDEO_PATTERN_GEN HDMI_CORE_BASE(0x05C4)
#define HDMI_HPD_GEN HDMI_CORE_BASE(0x05C8)

/* Audio related registers */
#define HDMI_ACR_CON HDMI_CORE_BASE(0x0180)
#define HDMI_ACR_MCTS0 HDMI_CORE_BASE(0x0184)
#define HDMI_ACR_MCTS1 HDMI_CORE_BASE(0x0188)
#define HDMI_ACR_MCTS2 HDMI_CORE_BASE(0x018C)
#define HDMI_ACR_CTS0 HDMI_CORE_BASE(0x0190)
#define HDMI_ACR_CTS1 HDMI_CORE_BASE(0x0194)
#define HDMI_ACR_CTS2 HDMI_CORE_BASE(0x0198)
#define HDMI_ACR_N0 HDMI_CORE_BASE(0x01A0)
#define HDMI_ACR_N1 HDMI_CORE_BASE(0x01A4)
#define HDMI_ACR_N2 HDMI_CORE_BASE(0x01A8)

#define HDMI_AUI_CON HDMI_CORE_BASE(0x0360)

/* Timing generator registers */
#define HDMI_TG_CMD HDMI_TG_BASE(0x0000)
#define HDMI_TG_H_FSZ_L HDMI_TG_BASE(0x0018)
Expand Down Expand Up @@ -125,6 +140,9 @@

/* HDMI_CON_0 */
#define HDMI_BLUE_SCR_EN (1 << 5)
#define HDMI_ASP_EN (1 << 2)
#define HDMI_ASP_DIS (0 << 2)
#define HDMI_ASP_MASK (1 << 2)
#define HDMI_EN (1 << 0)

/* HDMI_CON_2 */
Expand All @@ -139,6 +157,95 @@
#define HDMI_MODE_DVI_EN (1 << 0)
#define HDMI_MODE_MASK (3 << 0)

/* HDMI I2S register */
#define HDMI_I2S_CLK_CON HDMI_I2S_BASE(0x000)
#define HDMI_I2S_CON_1 HDMI_I2S_BASE(0x004)
#define HDMI_I2S_CON_2 HDMI_I2S_BASE(0x008)
#define HDMI_I2S_PIN_SEL_0 HDMI_I2S_BASE(0x00c)
#define HDMI_I2S_PIN_SEL_1 HDMI_I2S_BASE(0x010)
#define HDMI_I2S_PIN_SEL_2 HDMI_I2S_BASE(0x014)
#define HDMI_I2S_PIN_SEL_3 HDMI_I2S_BASE(0x018)
#define HDMI_I2S_DSD_CON HDMI_I2S_BASE(0x01c)
#define HDMI_I2S_MUX_CON HDMI_I2S_BASE(0x020)
#define HDMI_I2S_CH_ST_CON HDMI_I2S_BASE(0x024)
#define HDMI_I2S_CH_ST_0 HDMI_I2S_BASE(0x028)
#define HDMI_I2S_CH_ST_1 HDMI_I2S_BASE(0x02c)
#define HDMI_I2S_CH_ST_2 HDMI_I2S_BASE(0x030)
#define HDMI_I2S_CH_ST_3 HDMI_I2S_BASE(0x034)
#define HDMI_I2S_CH_ST_4 HDMI_I2S_BASE(0x038)
#define HDMI_I2S_MUX_CH HDMI_I2S_BASE(0x054)
#define HDMI_I2S_MUX_CUV HDMI_I2S_BASE(0x058)

/* I2S bit definition */

/* I2S_CLK_CON */
#define HDMI_I2S_CLK_DIS (0)
#define HDMI_I2S_CLK_EN (1)

/* I2S_CON_1 */
#define HDMI_I2S_SCLK_FALLING_EDGE (0 << 1)
#define HDMI_I2S_L_CH_LOW_POL (0)

/* I2S_CON_2 */
#define HDMI_I2S_MSB_FIRST_MODE (0 << 6)
#define HDMI_I2S_BASIC_FORMAT (0)
#define HDMI_I2S_SET_BIT_CH(x) (((x) & 0x7) << 4)
#define HDMI_I2S_SET_SDATA_BIT(x) (((x) & 0x7) << 2)

/* I2S_PIN_SEL_0 */
#define HDMI_I2S_SEL_SCLK(x) (((x) & 0x7) << 4)
#define HDMI_I2S_SEL_LRCK(x) ((x) & 0x7)

/* I2S_PIN_SEL_1 */
#define HDMI_I2S_SEL_SDATA1(x) (((x) & 0x7) << 4)
#define HDMI_I2S_SEL_SDATA2(x) ((x) & 0x7)

/* I2S_PIN_SEL_2 */
#define HDMI_I2S_SEL_SDATA3(x) (((x) & 0x7) << 4)
#define HDMI_I2S_SEL_SDATA4(x) ((x) & 0x7)

/* I2S_PIN_SEL_3 */
#define HDMI_I2S_SEL_DSD(x) ((x) & 0x7)

/* I2S_MUX_CON */
#define HDMI_I2S_IN_DISABLE (1 << 4)
#define HDMI_I2S_AUD_I2S (1 << 2)
#define HDMI_I2S_CUV_I2S_ENABLE (1 << 1)
#define HDMI_I2S_MUX_ENABLE (1)

/* I2S_CH_ST_CON */
#define HDMI_I2S_CH_STATUS_RELOAD (1)

/* I2S_CH_ST_0 / I2S_CH_ST_SH_0 */
#define HDMI_I2S_CH_STATUS_MODE_0 (0 << 6)
#define HDMI_I2S_2AUD_CH_WITHOUT_PREEMPH (0 << 3)
#define HDMI_I2S_COPYRIGHT (0 << 2)
#define HDMI_I2S_LINEAR_PCM (0 << 1)
#define HDMI_I2S_CONSUMER_FORMAT (0)

/* I2S_CH_ST_1 / I2S_CH_ST_SH_1 */
#define HDMI_I2S_CD_PLAYER (0x00)

/* I2S_CH_ST_2 / I2S_CH_ST_SH_2 */
#define HDMI_I2S_SET_SOURCE_NUM(x) ((x) & (0xF))

/* I2S_CH_ST_3 / I2S_CH_ST_SH_3 */
#define HDMI_I2S_CLK_ACCUR_LEVEL_2 (0 << 4)
#define HDMI_I2S_SET_SMP_FREQ(x) ((x) & (0xF))

/* I2S_CH_ST_4 / I2S_CH_ST_SH_4 */
#define HDMI_I2S_ORG_SMP_FREQ_44_1 (0xF << 4)
#define HDMI_I2S_WORD_LEN_MAX24_24BITS (0x5 << 1)
#define HDMI_I2S_WORD_LEN_MAX_24BITS (1)

/* I2S_MUX_CH */
#define HDMI_I2S_CH2_EN (3 << 4)
#define HDMI_I2S_CH1_EN (3 << 2)
#define HDMI_I2S_CH0_EN (3)

/* I2S_MUX_CUV */
#define HDMI_I2S_CUV_RL_EN (0x03)

/* HDMI_TG_CMD */
#define HDMI_TG_FIELD_EN (1 << 1)
#define HDMI_TG_EN (1 << 0)
Expand Down