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[MIPS]Remove unnecessary SLL instructions on MIPS64el #109386
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✅ With the latest revision this PR passed the C/C++ code formatter. |
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EVT VT = N->getValueType(0); | ||
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// Pattern match XOR. | ||
// $dst = sign_extend (xor (trunc $src), imm) |
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trunc
needs an argument. I guess the argument will have some effects on the result.
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For example, if $src=0x12345678
; imm=0xffff
.
lets truncate it to i8
, then it will be 0x78
, the result will be ~0x78.
lets truncate it to i16
, then it will be 0x5678
, the result will be ~0x5678.
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Maybe it is not correct.
Thanks for your review, I would find another solution. |
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@wzssyqa Could you help review again, thanks! |
Please read: https://llvm.org/docs/LangRef.html#id2158 |
SDValue Xor = DAG.getNode(ISD::XOR, SDLoc(N), VT, TruncateOperand, | ||
DAG.getTargetConstant(Mask, SDLoc(N), VT)); | ||
SDValue Truncate = | ||
DAG.getNode(ISD::TRUNCATE, SDLoc(N), N0->getValueType(0), Xor); |
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@wzssyqa The third parameter N0->getValueType(0)
is the truncate's destination type, that you mentioned the code lacked. Through this Node we can truncate the fourth parameter Xor
to type N0->getValueType(0)
.
So I think this did not lack a imm. May I understand right?
Ping. |
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I don't think this transform is correct: https://alive2.llvm.org/ce/z/-kNt7y
SDValue TruncateOperand = N0.getOperand(0).getOperand(0); | ||
if (VT == MVT::i64 && VT == TruncateOperand->getValueType(0)) { | ||
APInt MinusOne(32, -1, true); | ||
if (N0.getConstantOperandAPInt(1) == MinusOne) { |
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N0.getOperandAPInt(1).isAllOnes()?
APInt MinusOne(32, -1, true); | ||
if (N0.getConstantOperandAPInt(1) == MinusOne) { | ||
return DAG.getNode(ISD::XOR, SDLoc(N0), VT, TruncateOperand, | ||
DAG.getTargetConstant(-1, SDLoc(N0), VT)); |
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This should not be a target constant. TargetConstant should only nodes that always take an immediate for that operand.
SDValue N0 = N->getOperand(0); | ||
EVT VT = N->getValueType(0); | ||
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if (N0->getNumOperands() != 2) { |
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This check is unnecessary. The N0.getOpcode() == ISD::XOR
check below covers it.
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Yes, I will remove it.
N0.getOperand(0).getOpcode() == ISD::TRUNCATE && | ||
N0.getOperand(1).getOpcode() == ISD::Constant) { | ||
SDValue TruncateOperand = N0.getOperand(0).getOperand(0); | ||
if (VT == MVT::i64 && VT == TruncateOperand->getValueType(0)) { |
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This should be TruncateOperand.getValueType()
. You don't that result 0 of the TruncateOperand
node is being used. The result number is stored in the SDValue so you should use it.
I agree. You either need to call ComputeNumSignBits on the truncate input or do this transform instead: ((signext (xor (trunc X), imm)) to (xor (signext_inreg X, i32), imm). |
Thanks for your review. I will modify it to " (xor (signext_inreg X, i32), imm)" based on your comments. |
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Ping. |
cc @nikic |
; RUN: -check-prefixes=ALL,MM,MM32 | ||
; RUN: llc < %s -mtriple=mips -mcpu=mips32r6 -mattr=+micromips | FileCheck %s \ | ||
; RUN: -check-prefixes=ALL,MM,MM32 | ||
; RUN: llc < %s -march=mips -mcpu=mips2 | FileCheck %s -check-prefixes=GP32 |
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Why change -mtriple to -march?
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It was my oversight, I will restore it to -mtriple.
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Sorry, I checked the code again and changing -mtriple to -march is the result after running test_checks.py.Because the original code only specifies the CPU architecture .
This new patch LGTM. |
…inreg X, i32), imm) The constant operand of the XOR is an i32, which makes the two operands being truncated to i32, and sign extended to i64 afterwards. Since both of the i32 operands are sign extended to i64 before performing the TRUNCATE operation, we just remove the unnecessary TRUNCATE and SIGN_EXTEND. Fix llvm#99783
LGTM. |
LLVM Buildbot has detected a new failure on builder Full details are available at: https://lab.llvm.org/buildbot/#/builders/162/builds/21788 Here is the relevant piece of the build log for the reference
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Optimize ((signext (xor (trunc X), imm)) to (xor (X, imm)). Fix llvm#99783
Optimize ((signext (xor (trunc X), imm)) to (xor (X, imm)).
Fix #99783