[SPIRV] Add explicit layout #135789
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[SPIRV] Add explicit layout #135789
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Adds code add offset decorations when needed. This could cause a type mismatch for memory instructions. We add code to fix up OpLoad instructions, so that we could get some tests. Other memory operations will be handled in another PR. Part of llvm#134119.
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@llvm/pr-subscribers-backend-spir-v Author: Steven Perron (s-perron) ChangesAdds code add offset decorations when needed. This could cause a Part of #134119. Patch is 45.83 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/135789.diff 7 Files Affected:
diff --git a/llvm/lib/Target/SPIRV/SPIRVGlobalRegistry.cpp b/llvm/lib/Target/SPIRV/SPIRVGlobalRegistry.cpp
index 4ce316ea32e1c..2655167abe6af 100644
--- a/llvm/lib/Target/SPIRV/SPIRVGlobalRegistry.cpp
+++ b/llvm/lib/Target/SPIRV/SPIRVGlobalRegistry.cpp
@@ -835,13 +835,31 @@ static std::string buildSpirvTypeName(const SPIRVType *Type,
}
case SPIRV::OpTypeStruct: {
std::string TypeName = "{";
- for (uint32_t I = 2; I < Type->getNumOperands(); ++I) {
+ for (uint32_t I = 1; I < Type->getNumOperands(); ++I) {
SPIRVType *MemberType =
GR.getSPIRVTypeForVReg(Type->getOperand(I).getReg());
- TypeName = '_' + buildSpirvTypeName(MemberType, MIRBuilder, GR);
+ TypeName += '_' + buildSpirvTypeName(MemberType, MIRBuilder, GR);
}
return TypeName + "}";
}
+ case SPIRV::OpTypeVector: {
+ MachineRegisterInfo *MRI = MIRBuilder.getMRI();
+ Register ElementTypeReg = Type->getOperand(1).getReg();
+ auto *ElementType = MRI->getUniqueVRegDef(ElementTypeReg);
+ uint32_t VectorSize = GR.getScalarOrVectorComponentCount(Type);
+ return (buildSpirvTypeName(ElementType, MIRBuilder, GR) + Twine("[") +
+ Twine(VectorSize) + Twine("]"))
+ .str();
+ }
+ case SPIRV::OpTypeRuntimeArray: {
+ MachineRegisterInfo *MRI = MIRBuilder.getMRI();
+ Register ElementTypeReg = Type->getOperand(1).getReg();
+ auto *ElementType = MRI->getUniqueVRegDef(ElementTypeReg);
+ uint32_t ArraySize = 0;
+ return (buildSpirvTypeName(ElementType, MIRBuilder, GR) + Twine("[") +
+ Twine(ArraySize) + Twine("]"))
+ .str();
+ }
default:
llvm_unreachable("Trying to the the name of an unknown type.");
}
@@ -883,30 +901,41 @@ Register SPIRVGlobalRegistry::getOrCreateGlobalVariableWithBinding(
return VarReg;
}
+// TODO: Double check the calls to getOpTypeArray to make sure that `ElemType`
+// is explicitly laid out when required.
SPIRVType *SPIRVGlobalRegistry::getOpTypeArray(uint32_t NumElems,
SPIRVType *ElemType,
MachineIRBuilder &MIRBuilder,
+ bool ExplicitLayoutRequired,
bool EmitIR) {
assert((ElemType->getOpcode() != SPIRV::OpTypeVoid) &&
"Invalid array element type");
SPIRVType *SpvTypeInt32 = getOrCreateSPIRVIntegerType(32, MIRBuilder);
-
+ SPIRVType *ArrayType = nullptr;
if (NumElems != 0) {
Register NumElementsVReg =
buildConstantInt(NumElems, MIRBuilder, SpvTypeInt32, EmitIR);
- return createOpType(MIRBuilder, [&](MachineIRBuilder &MIRBuilder) {
+ ArrayType = createOpType(MIRBuilder, [&](MachineIRBuilder &MIRBuilder) {
return MIRBuilder.buildInstr(SPIRV::OpTypeArray)
.addDef(createTypeVReg(MIRBuilder))
.addUse(getSPIRVTypeID(ElemType))
.addUse(NumElementsVReg);
});
+ } else {
+ ArrayType = createOpType(MIRBuilder, [&](MachineIRBuilder &MIRBuilder) {
+ return MIRBuilder.buildInstr(SPIRV::OpTypeRuntimeArray)
+ .addDef(createTypeVReg(MIRBuilder))
+ .addUse(getSPIRVTypeID(ElemType));
+ });
}
- return createOpType(MIRBuilder, [&](MachineIRBuilder &MIRBuilder) {
- return MIRBuilder.buildInstr(SPIRV::OpTypeRuntimeArray)
- .addDef(createTypeVReg(MIRBuilder))
- .addUse(getSPIRVTypeID(ElemType));
- });
+ if (ExplicitLayoutRequired) {
+ Type *ET = const_cast<Type *>(getTypeForSPIRVType(ElemType));
+ addArrayStrideDecorations(ArrayType->defs().begin()->getReg(), ET,
+ MIRBuilder);
+ }
+
+ return ArrayType;
}
SPIRVType *SPIRVGlobalRegistry::getOpTypeOpaque(const StructType *Ty,
@@ -924,7 +953,8 @@ SPIRVType *SPIRVGlobalRegistry::getOpTypeOpaque(const StructType *Ty,
SPIRVType *SPIRVGlobalRegistry::getOpTypeStruct(
const StructType *Ty, MachineIRBuilder &MIRBuilder,
- SPIRV::AccessQualifier::AccessQualifier AccQual, bool EmitIR) {
+ SPIRV::AccessQualifier::AccessQualifier AccQual,
+ bool ExplicitLayoutRequired, bool EmitIR) {
SmallVector<Register, 4> FieldTypes;
constexpr unsigned MaxWordCount = UINT16_MAX;
const size_t NumElements = Ty->getNumElements();
@@ -938,8 +968,8 @@ SPIRVType *SPIRVGlobalRegistry::getOpTypeStruct(
}
for (const auto &Elem : Ty->elements()) {
- SPIRVType *ElemTy =
- findSPIRVType(toTypedPointer(Elem), MIRBuilder, AccQual, EmitIR);
+ SPIRVType *ElemTy = findSPIRVType(toTypedPointer(Elem), MIRBuilder, AccQual,
+ ExplicitLayoutRequired, EmitIR);
assert(ElemTy && ElemTy->getOpcode() != SPIRV::OpTypeVoid &&
"Invalid struct element type");
FieldTypes.push_back(getSPIRVTypeID(ElemTy));
@@ -950,18 +980,27 @@ SPIRVType *SPIRVGlobalRegistry::getOpTypeStruct(
if (Ty->isPacked())
buildOpDecorate(ResVReg, MIRBuilder, SPIRV::Decoration::CPacked, {});
- return createOpType(MIRBuilder, [&](MachineIRBuilder &MIRBuilder) {
- auto MIBStruct = MIRBuilder.buildInstr(SPIRV::OpTypeStruct).addDef(ResVReg);
- for (size_t I = 0; I < SPIRVStructNumElements; ++I)
- MIBStruct.addUse(FieldTypes[I]);
- for (size_t I = SPIRVStructNumElements; I < NumElements;
- I += MaxNumElements) {
- auto MIBCont = MIRBuilder.buildInstr(SPIRV::OpTypeStructContinuedINTEL);
- for (size_t J = I; J < std::min(I + MaxNumElements, NumElements); ++J)
- MIBCont.addUse(FieldTypes[I]);
- }
- return MIBStruct;
- });
+ SPIRVType *SPVType =
+ createOpType(MIRBuilder, [&](MachineIRBuilder &MIRBuilder) {
+ auto MIBStruct =
+ MIRBuilder.buildInstr(SPIRV::OpTypeStruct).addDef(ResVReg);
+ for (size_t I = 0; I < SPIRVStructNumElements; ++I)
+ MIBStruct.addUse(FieldTypes[I]);
+ for (size_t I = SPIRVStructNumElements; I < NumElements;
+ I += MaxNumElements) {
+ auto MIBCont =
+ MIRBuilder.buildInstr(SPIRV::OpTypeStructContinuedINTEL);
+ for (size_t J = I; J < std::min(I + MaxNumElements, NumElements); ++J)
+ MIBCont.addUse(FieldTypes[I]);
+ }
+ return MIBStruct;
+ });
+
+ if (ExplicitLayoutRequired)
+ addStructOffsetDecorations(SPVType->defs().begin()->getReg(),
+ const_cast<StructType *>(Ty), MIRBuilder);
+
+ return SPVType;
}
SPIRVType *SPIRVGlobalRegistry::getOrCreateSpecialType(
@@ -1011,22 +1050,26 @@ SPIRVType *SPIRVGlobalRegistry::getOrCreateOpTypeFunctionWithArgs(
const Type *Ty, SPIRVType *RetType,
const SmallVectorImpl<SPIRVType *> &ArgTypes,
MachineIRBuilder &MIRBuilder) {
- if (const MachineInstr *MI = findMI(Ty, &MIRBuilder.getMF()))
+ if (const MachineInstr *MI = findMI(Ty, false, &MIRBuilder.getMF()))
return MI;
const MachineInstr *NewMI = getOpTypeFunction(RetType, ArgTypes, MIRBuilder);
- add(Ty, NewMI);
+ add(Ty, false, NewMI);
return finishCreatingSPIRVType(Ty, NewMI);
}
SPIRVType *SPIRVGlobalRegistry::findSPIRVType(
const Type *Ty, MachineIRBuilder &MIRBuilder,
- SPIRV::AccessQualifier::AccessQualifier AccQual, bool EmitIR) {
+ SPIRV::AccessQualifier::AccessQualifier AccQual,
+ bool ExplicitLayoutRequired, bool EmitIR) {
Ty = adjustIntTypeByWidth(Ty);
- if (const MachineInstr *MI = findMI(Ty, &MIRBuilder.getMF()))
+ // TODO: findMI needs to know if a layout is required.
+ if (const MachineInstr *MI =
+ findMI(Ty, ExplicitLayoutRequired, &MIRBuilder.getMF()))
return MI;
if (auto It = ForwardPointerTypes.find(Ty); It != ForwardPointerTypes.end())
return It->second;
- return restOfCreateSPIRVType(Ty, MIRBuilder, AccQual, EmitIR);
+ return restOfCreateSPIRVType(Ty, MIRBuilder, AccQual, ExplicitLayoutRequired,
+ EmitIR);
}
Register SPIRVGlobalRegistry::getSPIRVTypeID(const SPIRVType *SpirvType) const {
@@ -1060,11 +1103,13 @@ const Type *SPIRVGlobalRegistry::adjustIntTypeByWidth(const Type *Ty) const {
SPIRVType *SPIRVGlobalRegistry::createSPIRVType(
const Type *Ty, MachineIRBuilder &MIRBuilder,
- SPIRV::AccessQualifier::AccessQualifier AccQual, bool EmitIR) {
+ SPIRV::AccessQualifier::AccessQualifier AccQual,
+ bool ExplicitLayoutRequired, bool EmitIR) {
if (isSpecialOpaqueType(Ty))
return getOrCreateSpecialType(Ty, MIRBuilder, AccQual);
- if (const MachineInstr *MI = findMI(Ty, &MIRBuilder.getMF()))
+ if (const MachineInstr *MI =
+ findMI(Ty, ExplicitLayoutRequired, &MIRBuilder.getMF()))
return MI;
if (auto IType = dyn_cast<IntegerType>(Ty)) {
@@ -1077,27 +1122,31 @@ SPIRVType *SPIRVGlobalRegistry::createSPIRVType(
if (Ty->isVoidTy())
return getOpTypeVoid(MIRBuilder);
if (Ty->isVectorTy()) {
- SPIRVType *El = findSPIRVType(cast<FixedVectorType>(Ty)->getElementType(),
- MIRBuilder, AccQual, EmitIR);
+ SPIRVType *El =
+ findSPIRVType(cast<FixedVectorType>(Ty)->getElementType(), MIRBuilder,
+ AccQual, ExplicitLayoutRequired, EmitIR);
return getOpTypeVector(cast<FixedVectorType>(Ty)->getNumElements(), El,
MIRBuilder);
}
if (Ty->isArrayTy()) {
- SPIRVType *El =
- findSPIRVType(Ty->getArrayElementType(), MIRBuilder, AccQual, EmitIR);
- return getOpTypeArray(Ty->getArrayNumElements(), El, MIRBuilder, EmitIR);
+ SPIRVType *El = findSPIRVType(Ty->getArrayElementType(), MIRBuilder,
+ AccQual, ExplicitLayoutRequired, EmitIR);
+ return getOpTypeArray(Ty->getArrayNumElements(), El, MIRBuilder,
+ ExplicitLayoutRequired, EmitIR);
}
if (auto SType = dyn_cast<StructType>(Ty)) {
if (SType->isOpaque())
return getOpTypeOpaque(SType, MIRBuilder);
- return getOpTypeStruct(SType, MIRBuilder, AccQual, EmitIR);
+ return getOpTypeStruct(SType, MIRBuilder, AccQual, ExplicitLayoutRequired,
+ EmitIR);
}
if (auto FType = dyn_cast<FunctionType>(Ty)) {
- SPIRVType *RetTy =
- findSPIRVType(FType->getReturnType(), MIRBuilder, AccQual, EmitIR);
+ SPIRVType *RetTy = findSPIRVType(FType->getReturnType(), MIRBuilder,
+ AccQual, ExplicitLayoutRequired, EmitIR);
SmallVector<SPIRVType *, 4> ParamTypes;
for (const auto &ParamTy : FType->params())
- ParamTypes.push_back(findSPIRVType(ParamTy, MIRBuilder, AccQual, EmitIR));
+ ParamTypes.push_back(findSPIRVType(ParamTy, MIRBuilder, AccQual,
+ ExplicitLayoutRequired, EmitIR));
return getOpTypeFunction(RetTy, ParamTypes, MIRBuilder);
}
@@ -1112,44 +1161,50 @@ SPIRVType *SPIRVGlobalRegistry::createSPIRVType(
const SPIRVSubtarget *ST =
static_cast<const SPIRVSubtarget *>(&MIRBuilder.getMF().getSubtarget());
auto SC = addressSpaceToStorageClass(AddrSpace, *ST);
- // Null pointer means we have a loop in type definitions, make and
- // return corresponding OpTypeForwardPointer.
- if (SpvElementType == nullptr) {
- auto [It, Inserted] = ForwardPointerTypes.try_emplace(Ty);
- if (Inserted)
- It->second = getOpTypeForwardPointer(SC, MIRBuilder);
- return It->second;
+
+ Type *ElemTy = ::getPointeeType(Ty);
+ if (!ElemTy) {
+ ElemTy = Type::getInt8Ty(MIRBuilder.getContext());
}
+
// If we have forward pointer associated with this type, use its register
// operand to create OpTypePointer.
if (auto It = ForwardPointerTypes.find(Ty); It != ForwardPointerTypes.end()) {
Register Reg = getSPIRVTypeID(It->second);
+ // TODO: what does getOpTypePointer do?
return getOpTypePointer(SC, SpvElementType, MIRBuilder, Reg);
}
- return getOrCreateSPIRVPointerType(SpvElementType, MIRBuilder, SC);
+ return getOrCreateSPIRVPointerType(ElemTy, MIRBuilder, SC);
}
SPIRVType *SPIRVGlobalRegistry::restOfCreateSPIRVType(
const Type *Ty, MachineIRBuilder &MIRBuilder,
- SPIRV::AccessQualifier::AccessQualifier AccessQual, bool EmitIR) {
+ SPIRV::AccessQualifier::AccessQualifier AccessQual,
+ bool ExplicitLayoutRequired, bool EmitIR) {
+ // TODO: Could this create a problem if one requires an explicit layout, and
+ // the next time it does not?
if (TypesInProcessing.count(Ty) && !isPointerTyOrWrapper(Ty))
return nullptr;
TypesInProcessing.insert(Ty);
- SPIRVType *SpirvType = createSPIRVType(Ty, MIRBuilder, AccessQual, EmitIR);
+ SPIRVType *SpirvType = createSPIRVType(Ty, MIRBuilder, AccessQual,
+ ExplicitLayoutRequired, EmitIR);
TypesInProcessing.erase(Ty);
VRegToTypeMap[&MIRBuilder.getMF()][getSPIRVTypeID(SpirvType)] = SpirvType;
+
+ // TODO: We could end up with two SPIR-V types pointing to the same llvm type.
+ // Is that a problem?
SPIRVToLLVMType[SpirvType] = unifyPtrType(Ty);
if (SpirvType->getOpcode() == SPIRV::OpTypeForwardPointer ||
- findMI(Ty, &MIRBuilder.getMF()) || isSpecialOpaqueType(Ty))
+ findMI(Ty, false, &MIRBuilder.getMF()) || isSpecialOpaqueType(Ty))
return SpirvType;
if (auto *ExtTy = dyn_cast<TargetExtType>(Ty);
ExtTy && isTypedPointerWrapper(ExtTy))
add(ExtTy->getTypeParameter(0), ExtTy->getIntParameter(0), SpirvType);
else if (!isPointerTy(Ty))
- add(Ty, SpirvType);
+ add(Ty, ExplicitLayoutRequired, SpirvType);
else if (isTypedPointerTy(Ty))
add(cast<TypedPointerType>(Ty)->getElementType(),
getPointerAddressSpace(Ty), SpirvType);
@@ -1181,14 +1236,15 @@ SPIRVType *SPIRVGlobalRegistry::getResultType(Register VReg,
SPIRVType *SPIRVGlobalRegistry::getOrCreateSPIRVType(
const Type *Ty, MachineIRBuilder &MIRBuilder,
- SPIRV::AccessQualifier::AccessQualifier AccessQual, bool EmitIR) {
+ SPIRV::AccessQualifier::AccessQualifier AccessQual,
+ bool ExplicitLayoutRequired, bool EmitIR) {
const MachineFunction *MF = &MIRBuilder.getMF();
Register Reg;
if (auto *ExtTy = dyn_cast<TargetExtType>(Ty);
ExtTy && isTypedPointerWrapper(ExtTy))
Reg = find(ExtTy->getTypeParameter(0), ExtTy->getIntParameter(0), MF);
else if (!isPointerTy(Ty))
- Reg = find(Ty = adjustIntTypeByWidth(Ty), MF);
+ Reg = find(Ty = adjustIntTypeByWidth(Ty), ExplicitLayoutRequired, MF);
else if (isTypedPointerTy(Ty))
Reg = find(cast<TypedPointerType>(Ty)->getElementType(),
getPointerAddressSpace(Ty), MF);
@@ -1199,15 +1255,20 @@ SPIRVType *SPIRVGlobalRegistry::getOrCreateSPIRVType(
return getSPIRVTypeForVReg(Reg);
TypesInProcessing.clear();
- SPIRVType *STy = restOfCreateSPIRVType(Ty, MIRBuilder, AccessQual, EmitIR);
+ SPIRVType *STy = restOfCreateSPIRVType(Ty, MIRBuilder, AccessQual,
+ ExplicitLayoutRequired, EmitIR);
// Create normal pointer types for the corresponding OpTypeForwardPointers.
for (auto &CU : ForwardPointerTypes) {
+ // Pointer type themselves do not require an explicit layout. The types
+ // they pointer to might, but that is taken care of when creating the type.
+ bool PtrNeedsLayout = false;
const Type *Ty2 = CU.first;
SPIRVType *STy2 = CU.second;
- if ((Reg = find(Ty2, MF)).isValid())
+ if ((Reg = find(Ty2, PtrNeedsLayout, MF)).isValid())
STy2 = getSPIRVTypeForVReg(Reg);
else
- STy2 = restOfCreateSPIRVType(Ty2, MIRBuilder, AccessQual, EmitIR);
+ STy2 = restOfCreateSPIRVType(Ty2, MIRBuilder, AccessQual, PtrNeedsLayout,
+ EmitIR);
if (Ty == Ty2)
STy = STy2;
}
@@ -1360,16 +1421,16 @@ SPIRVType *SPIRVGlobalRegistry::getOrCreateVulkanBufferType(
if (const MachineInstr *MI = findMI(Key, &MIRBuilder.getMF()))
return MI;
- // TODO(134119): The SPIRVType for `ElemType` will not have an explicit
- // layout. This generates invalid SPIR-V.
+ bool ExplicitLayoutRequired = storageClassRequiresExplictLayout(SC);
+ // We need to get the SPIR-V type for the element here, so we can add the
+ // decoration to it.
auto *T = StructType::create(ElemType);
auto *BlockType =
- getOrCreateSPIRVType(T, MIRBuilder, SPIRV::AccessQualifier::None, EmitIr);
+ getOrCreateSPIRVType(T, MIRBuilder, SPIRV::AccessQualifier::None,
+ ExplicitLayoutRequired, EmitIr);
buildOpDecorate(BlockType->defs().begin()->getReg(), MIRBuilder,
SPIRV::Decoration::Block, {});
- buildOpMemberDecorate(BlockType->defs().begin()->getReg(), MIRBuilder,
- SPIRV::Decoration::Offset, 0, {0});
if (!IsWritable) {
buildOpMemberDecorate(BlockType->defs().begin()->getReg(), MIRBuilder,
@@ -1478,7 +1539,8 @@ SPIRVType *SPIRVGlobalRegistry::getOrCreateOpTypeCoopMatr(
MachineIRBuilder &MIRBuilder, const TargetExtType *ExtensionType,
const SPIRVType *ElemType, uint32_t Scope, uint32_t Rows, uint32_t Columns,
uint32_t Use, bool EmitIR) {
- if (const MachineInstr *MI = findMI(ExtensionType, &MIRBuilder.getMF()))
+ if (const MachineInstr *MI =
+ findMI(ExtensionType, false, &MIRBuilder.getMF()))
return MI;
const MachineInstr *NewMI =
createOpType(MIRBuilder, [&](MachineIRBuilder &MIRBuilder) {
@@ -1491,26 +1553,26 @@ SPIRVType *SPIRVGlobalRegistry::getOrCreateOpTypeCoopMatr(
.addUse(buildConstantInt(Columns, MIRBuilder, SpvTypeInt32, EmitIR))
.addUse(buildConstantInt(Use, MIRBuilder, SpvTypeInt32, EmitIR));
});
- add(ExtensionType, NewMI);
+ add(ExtensionType, false, NewMI);
return NewMI;
}
SPIRVType *SPIRVGlobalRegistry::getOrCreateOpTypeByOpcode(
const Type *Ty, MachineIRBuilder &MIRBuilder, unsigned Opcode) {
- if (const MachineInstr *MI = findMI(Ty, &MIRBuilder.getMF()))
+ if (const MachineInstr *MI = findMI(Ty, false, &MIRBuilder.getMF()))
return MI;
const MachineInstr *NewMI =
createOpType(MIRBuilder, [&](MachineIRBuilder &MIRBuilder) {
return MIRBuilder.buildInstr(Opcode).addDef(createTypeVReg(MIRBuilder));
});
- add(Ty, NewMI);
+ add(Ty, false, NewMI);
return NewMI;
}
SPIRVType *SPIRVGlobalRegistry::getOrCreateUnknownType(
const Type *Ty, MachineIRBuilder &MIRBuilder, unsigned Opcode,
const ArrayRef<MCOperand> Operands) {
- if (const MachineInstr *MI = findMI(Ty, &MIRBuilder.getMF()))
+ if (const MachineInstr *MI = findMI(Ty, false, &MIRBuilder.getMF()))
return MI;
Register ResVReg = createTypeVReg(MIRBuilder);
const MachineInstr *NewMI =
@@ -1527,7 +1589,7 @@ SPIRVType *SPIRVGlobalRegistry::getOrCreateUnknownType(
}
return MIB;
});
- add(Ty, NewMI);
+ add(Ty, false, NewMI);
return NewMI;
}
@@ -1543,7 +1605,7 @@ SPIRVType *SPIRVGlobalRegistry::getOrCreateSPIRVTypeByName(
if (hasBuiltinTypePrefix(TypeStr))
return getOrCreateSPIRVType(SPIRV::parseBuiltinTypeNameToTargetExtType(
TypeStr.str(), MIRBuilder.getContext()),
- MIRBuilder, AQ, true);
+ MIRBuilder, AQ, false, true);
// Parse type name in either "typeN" or "type vector[N]" format, where
// N is the number of elements of the vector.
@@ -1554,7 +1616,7 @@ SPIRVType *SPIRVGlobalRegistry::getOrCreateSPIRVTypeByName(
// Unable to recognize SPIRV type name
return nullptr;
- auto SpirvTy = getOrCreateSPIRVType(Ty, MIRBuilder, AQ, true);
+ auto SpirvTy = getOrCreateSPIRVType(Ty, MIRBuilder, AQ, false, true);
// Handle "type*" or "type* vector[N]".
if (TypeStr.starts_with("*")) {
@@ -1583,7 +1645,7 @@ SPIRVGlobalRegistry::getOrCreateSPIRVIntegerType(unsigned BitWidth,
MachineIRBuilder &MIRBuilder) {
return getOrCreateSPIRVType(
IntegerType::get(MIRBuilder.getMF().getFunction().getContext(), BitWidth),
- MIRBuilder, SPIRV::AccessQualifier::ReadWrite, true);
+ MIRBuilder, SPIRV::AccessQualifier::ReadWrite, false, true);
}
SPIRVType *SPIRVGlobalRegistry::finishCreatingSPIRVType(const Type *LLVMTy,
@@ -1599,7 +1661,7 @@ SPIRVType *SPIRVGlobalRegistry::getOrCreateSPIRVType(unsigned BitWidth,
const SPIRVInstrInfo &TII,
unsigned SPIRVOPcode,
...
[truncated]
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Keenuts
reviewed
Apr 16, 2025
|
@VyacheslavLevytskyy I am interested in your thought on the changes to SPIRVIRMapping.Thanks. |
Sure, I'm reviewing right now, by a coincidence :) |
There was a problem hiding this comment.
I think this should work for the compute part without problems, but I'd like to notify about the change @michalpaszkowski and @MrSidims, so that they are able to check this PR in advance with OpenCL CTS and SYCL CTS in case if they decide that it's worth double checking with extended test suites. The point is that compute environments are quite sensitive to correct types and we used to check big changes in types with CTS to be sure that all works.
|
aside of the idea to check with one or two compute CTS test suites in advance, this looks good to me |
VyacheslavLevytskyy
approved these changes
Apr 28, 2025
Currently running OpenCL CTS, this takes a while (around 30 hours) -- I should have the results by the end of the day on Wednesday. Will add a review once I get the results. @VyacheslavLevytskyy / @MrSidims: I don't have the infrastructure setup to run SYCL CTS / DPC++ testing, please check on your end. |
|
@michalpaszkowski @MrSidims Any results from the CTS tests? |
@s-perron Sorry, this took a bit longer than I anticipated, I found no regressions with OpenCL CTS. The change LGTM from my side. @asudarsa Would you be able to double-check with DPC++ CI? |
michalpaszkowski
approved these changes
May 5, 2025
Keenuts
approved these changes
May 5, 2025
MrSidims
approved these changes
May 5, 2025
|
LLVM Buildbot has detected a new failure on builder Full details are available at: https://lab.llvm.org/buildbot/#/builders/55/builds/10878 Here is the relevant piece of the build log for the reference |
|
LLVM Buildbot has detected a new failure on builder Full details are available at: https://lab.llvm.org/buildbot/#/builders/24/builds/8092 Here is the relevant piece of the build log for the reference |
|
LLVM Buildbot has detected a new failure on builder Full details are available at: https://lab.llvm.org/buildbot/#/builders/94/builds/6850 Here is the relevant piece of the build log for the reference |
s-perron
added a commit
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that referenced
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May 6, 2025
When the DataLayout is destroyed, the memory backing `Offsets` is released. This causes a use after free. To fix it, I added a DataLayout varible that will not be destroyed until after Offsets is used. Fixes asan failure caused by llvm#135789
|
I opened #138695 to fix the asan failures. |
s-perron
added a commit
that referenced
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May 6, 2025
When the DataLayout is destroyed, the memory backing `Offsets` is released. This causes a use after free. To fix it, I added a DataLayout varible that will not be destroyed until after Offsets is used. Fixes asan failure caused by #135789
kstoimenov
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May 6, 2025
Breaks bot: https://lab.llvm.org/buildbot/#/builders/24/builds/8092 This reverts commit 492ad84.
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When the DataLayout is destroyed, the memory backing `Offsets` is released. This causes a use after free. To fix it, I added a DataLayout varible that will not be destroyed until after Offsets is used. Fixes asan failure caused by llvm/llvm-project#135789
s-perron
added a commit
to s-perron/llvm-project
that referenced
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May 7, 2025
The asan failure was fixed by llvm#138695, but another failure was introduced in the meantime. The cause for the other failure has been fixed. I will reapply the two PRs. Reapply "[SPIRV] Add explicit layout (llvm#135789)" This reverts commit 0fb5720. Reapply "[SPIRV] Fix asan failure (llvm#138695)" This reverts commit df90ab9.
GeorgeARM
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Adds code to add offset decorations when needed. This could cause a type mismatch for memory instructions. We add code to fix up OpLoad instructions, so that we could get some tests. Other memory operations will be handled in another PR. Part of llvm#134119.
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When the DataLayout is destroyed, the memory backing `Offsets` is released. This causes a use after free. To fix it, I added a DataLayout varible that will not be destroyed until after Offsets is used. Fixes asan failure caused by llvm#135789
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Breaks bot: https://lab.llvm.org/buildbot/#/builders/24/builds/8092 This reverts commit 492ad84.
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The asan failure was fixed by #138695, but another failure was introduced in the meantime. The cause for the other failure has been fixed. I will reapply the two PRs. Reapply "[SPIRV] Add explicit layout (#135789)" This reverts commit 0fb5720. Reapply "[SPIRV] Fix asan failure (#138695)" This reverts commit df90ab9.
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Adds code to add offset decorations when needed. This could cause a
type mismatch for memory instructions. We add code to fix up OpLoad
instructions, so that we could get some tests. Other memory operations
will be handled in another PR.
Part of #134119.