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[mlir][vector] Linearization: push 'bit width' logic out of patterns #136581

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Merged
merged 5 commits into from
Apr 30, 2025
Merged

[mlir][vector] Linearization: push 'bit width' logic out of patterns #136581

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b523a5a
factorize out the logic about bounded bitwidth
newling Apr 21, 2025
86ceb57
clang-format
newling Apr 21, 2025
be48849
push further with the separation of concerns
newling Apr 22, 2025
5d21371
clang-format
newling Apr 22, 2025
cbd1069
fix typo
newling Apr 22, 2025
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clang-format
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@newling
newling committed Apr 21, 2025
commit 86ceb57b31dffd6a433ac11cf748dc4d5b1ea2e7
2 changes: 1 addition & 1 deletion mlir/lib/Dialect/Vector/Transforms/VectorLinearize.cpp
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Expand Up @@ -450,7 +450,7 @@ struct LinearizeVectorBitCast final
} // namespace

/// If `type` is VectorType with trailing dimension of (bit) size greater than
/// or equal to `targetBitWidth`, its defining op is considered legal.
/// or equal to `targetBitWidth`, its defining op is considered legal.
static bool legalBecauseOfBitwidth(Type type, unsigned targetBitWidth) {

VectorType vecType = dyn_cast<VectorType>(type);
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