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[VectorUtils][VPlan] Consolidate VPWidenIntrinsicRecipe::onlyFirstLaneUsed and isVectorIntrinsicWithScalarOpAtArg #137497

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Merged
merged 5 commits into from
Apr 30, 2025
Merged

[VectorUtils][VPlan] Consolidate VPWidenIntrinsicRecipe::onlyFirstLaneUsed and isVectorIntrinsicWithScalarOpAtArg #137497

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ecc63e7
Precommit test
lukel97 Apr 29, 2025
2cfab8b
[VectorUtils][VPlan] Consolidate VPWidenIntrinsicRecipe::onlyFirstLan…
lukel97 Apr 27, 2025
353adf0
Check all operands
lukel97 Apr 29, 2025
e525298
Use all_of
lukel97 Apr 30, 2025
162896e
Use const, update EVL comment, remove noalias, rename test
lukel97 Apr 30, 2025
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6 changes: 5 additions & 1 deletion llvm/lib/Analysis/VectorUtils.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -149,6 +149,10 @@ bool llvm::isVectorIntrinsicWithScalarOpAtArg(Intrinsic::ID ID,
if (TTI && Intrinsic::isTargetIntrinsic(ID))
return TTI->isTargetIntrinsicWithScalarOpAtArg(ID, ScalarOpdIdx);

// Vector predication intrinsics have the EVL as the last operand.
if (VPIntrinsic::getVectorLengthParamPos(ID) == ScalarOpdIdx)
return true;

switch (ID) {
case Intrinsic::abs:
case Intrinsic::vp_abs:
Expand All @@ -166,7 +170,7 @@ bool llvm::isVectorIntrinsicWithScalarOpAtArg(Intrinsic::ID ID,
case Intrinsic::umul_fix_sat:
return (ScalarOpdIdx == 2);
case Intrinsic::experimental_vp_splice:
return ScalarOpdIdx == 2 || ScalarOpdIdx == 4 || ScalarOpdIdx == 5;
return ScalarOpdIdx == 2 || ScalarOpdIdx == 4;
default:
return false;
}
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9 changes: 5 additions & 4 deletions llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
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Expand Up @@ -1364,10 +1364,11 @@ StringRef VPWidenIntrinsicRecipe::getIntrinsicName() const {

bool VPWidenIntrinsicRecipe::onlyFirstLaneUsed(const VPValue *Op) const {
assert(is_contained(operands(), Op) && "Op must be an operand of the recipe");
// Vector predication intrinsics only demand the the first lane the last
// operand (the EVL operand).
return VPIntrinsic::isVPIntrinsic(VectorIntrinsicID) &&
Op == getOperand(getNumOperands() - 1);
return all_of(enumerate(operands()), [this, &Op](const auto &X) {
auto [Idx, V] = X;
return V != Op || isVectorIntrinsicWithScalarOpAtArg(getVectorIntrinsicID(),
Idx, nullptr);
});
}

#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
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54 changes: 54 additions & 0 deletions llvm/test/Transforms/LoopVectorize/widen-intrinsic.ll
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@@ -0,0 +1,54 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --check-globals none --version 5
; RUN: opt < %s -passes=loop-vectorize -force-vector-width=4 -S | FileCheck %s

; Check that we don't unnecessarily broadcast %pow
define void @powi_only_first_lane_used_of_second_arg(ptr %p, i32 %pow) {
; CHECK-LABEL: define void @powi_only_first_lane_used_of_second_arg(
; CHECK-SAME: ptr [[P:%.*]], i32 [[POW:%.*]]) {
; CHECK-NEXT: [[ENTRY:.*]]:
; CHECK-NEXT: br i1 false, label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]
; CHECK: [[VECTOR_PH]]:
; CHECK-NEXT: br label %[[VECTOR_BODY:.*]]
; CHECK: [[VECTOR_BODY]]:
; CHECK-NEXT: [[INDEX:%.*]] = phi i32 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
; CHECK-NEXT: [[TMP0:%.*]] = getelementptr float, ptr [[P]], i32 [[INDEX]]
; CHECK-NEXT: [[TMP1:%.*]] = getelementptr float, ptr [[TMP0]], i32 0
; CHECK-NEXT: [[WIDE_LOAD:%.*]] = load <4 x float>, ptr [[TMP1]], align 4
; CHECK-NEXT: [[TMP2:%.*]] = call <4 x float> @llvm.powi.v4f32.i32(<4 x float> [[WIDE_LOAD]], i32 [[POW]])
; CHECK-NEXT: store <4 x float> [[TMP2]], ptr [[TMP1]], align 4
; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i32 [[INDEX]], 4
; CHECK-NEXT: [[TMP3:%.*]] = icmp eq i32 [[INDEX_NEXT]], 1024
; CHECK-NEXT: br i1 [[TMP3]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]
; CHECK: [[MIDDLE_BLOCK]]:
; CHECK-NEXT: br i1 true, label %[[EXIT:.*]], label %[[SCALAR_PH]]
; CHECK: [[SCALAR_PH]]:
; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i32 [ 1024, %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ]
; CHECK-NEXT: br label %[[LOOP:.*]]
; CHECK: [[LOOP]]:
; CHECK-NEXT: [[IV:%.*]] = phi i32 [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], %[[LOOP]] ]
; CHECK-NEXT: [[P_GEP:%.*]] = getelementptr float, ptr [[P]], i32 [[IV]]
; CHECK-NEXT: [[X:%.*]] = load float, ptr [[P_GEP]], align 4
; CHECK-NEXT: [[Y:%.*]] = call float @llvm.powi.f32.i32(float [[X]], i32 [[POW]])
; CHECK-NEXT: store float [[Y]], ptr [[P_GEP]], align 4
; CHECK-NEXT: [[IV_NEXT]] = add i32 [[IV]], 1
; CHECK-NEXT: [[DONE:%.*]] = icmp eq i32 [[IV_NEXT]], 1024
; CHECK-NEXT: br i1 [[DONE]], label %[[EXIT]], label %[[LOOP]], !llvm.loop [[LOOP3:![0-9]+]]
; CHECK: [[EXIT]]:
; CHECK-NEXT: ret void
;
entry:
br label %loop

loop:
%iv = phi i32 [0, %entry], [%iv.next, %loop]
%p.gep = getelementptr float, ptr %p, i32 %iv
%x = load float, ptr %p.gep
%y = call float @llvm.powi(float %x, i32 %pow)
store float %y, ptr %p.gep
%iv.next = add i32 %iv, 1
%done = icmp eq i32 %iv.next, 1024
br i1 %done, label %exit, label %loop

exit:
ret void
}