[RISCV][MC] Support Base P non-GPR pair instructions #137927
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This patch adds support for non-GPR pair instructions in purposed Base P extension for RISC-V. Documentation: jhauser.us/RISCV/ext-P/RVP-baseInstrs-014.pdf jhauser.us/RISCV/ext-P/RVP-instrEncodings-014b.pdf
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@llvm/pr-subscribers-backend-risc-v @llvm/pr-subscribers-mc Author: None (realqhc) ChangesThis patch adds support for non-GPR pair instructions in purposed Base P extension for RISC-V. Documentation: Full diff: https://github.com/llvm/llvm-project/pull/137927.diff 10 Files Affected:
diff --git a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
index 9bc4734815364..fc20a7b1af4cc 100644
--- a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
+++ b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
@@ -803,6 +803,7 @@ struct RISCVOperand final : public MCParsedAsmOperand {
bool isSImm5() const { return isSImm<5>(); }
bool isSImm6() const { return isSImm<6>(); }
+ bool isSImm10() const { return isSImm<10>(); }
bool isSImm11() const { return isSImm<11>(); }
bool isSImm16() const { return isSImm<16>(); }
bool isSImm26() const { return isSImm<26>(); }
@@ -1524,6 +1525,9 @@ bool RISCVAsmParser::matchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
return generateImmOutOfRangeError(
Operands, ErrorInfo, 0, (1 << 9) - 8,
"immediate must be a multiple of 8 bytes in the range");
+ case Match_InvalidSImm10:
+ return generateImmOutOfRangeError(Operands, ErrorInfo, -(1 << 9),
+ (1 << 9) - 1);
case Match_InvalidUImm10Lsb00NonZero:
return generateImmOutOfRangeError(
Operands, ErrorInfo, 4, (1 << 10) - 4,
diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
index 6ef94fb5e93da..1612941be6631 100644
--- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
+++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
@@ -336,6 +336,7 @@ enum OperandType : unsigned {
OPERAND_SIMM5_PLUS1,
OPERAND_SIMM6,
OPERAND_SIMM6_NONZERO,
+ OPERAND_SIMM10,
OPERAND_SIMM10_LSB0000_NONZERO,
OPERAND_SIMM11,
OPERAND_SIMM12,
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.td b/llvm/lib/Target/RISCV/RISCVInstrInfo.td
index 7cd36aa46efbe..b4e650f87eda2 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.td
@@ -2160,6 +2160,9 @@ include "RISCVInstrInfoV.td"
include "RISCVInstrInfoZvk.td"
include "RISCVInstrInfoZvqdotq.td"
+// Packed SIMD
+include "RISCVInstrInfoP.td"
+
// Integer
include "RISCVInstrInfoZimop.td"
include "RISCVInstrInfoZicbo.td"
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoP.td b/llvm/lib/Target/RISCV/RISCVInstrInfoP.td
new file mode 100644
index 0000000000000..a398721ab3fb2
--- /dev/null
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoP.td
@@ -0,0 +1,165 @@
+//===-- RISCVInstrInfoP.td - RISC-V 'P' instructions -------*- tablegen -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// This file describes the RISC-V instructions from the standard 'Base P'
+// Packed SIMD instruction set extension.
+//
+// This version is still experimental as the 'P' extension hasn't been
+// ratified yet.
+//
+//===----------------------------------------------------------------------===//
+
+//===----------------------------------------------------------------------===//
+// Operand and SDNode transformation definitions.
+//===----------------------------------------------------------------------===//
+
+def RVPGPRPairRV32 : RegisterOperand<GPRPair> {
+ let ParserMatchClass = GPRPairRV32Operand;
+ let EncoderMethod = "getRVPGPRPair";
+ let DecoderMethod = "decodeRVPGPRPair";
+}
+
+def simm10 : RISCVSImmLeafOp<10>;
+
+//===----------------------------------------------------------------------===//
+// Instruction class templates
+//===----------------------------------------------------------------------===//
+
+let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
+class RVPUnaryImm9<bits<7> funct7, string opcodestr>
+ : RVInstIBase<0b010, OPC_OP_IMM_32, (outs GPR:$rd), (ins simm10:$simm10),
+ opcodestr, "$rd, $simm10"> {
+ bits<10> simm10;
+
+ let Inst{31-25} = funct7;
+ let Inst{24-15} = simm10;
+}
+
+let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
+class RVPUnaryImm9Rdp<bits<7> funct7, string opcodestr>
+ : RVInstIBase<0b010, OPC_OP_IMM_32, (outs RVPGPRPairRV32:$rdp),
+ (ins simm10:$simm10),
+ opcodestr, "$rdp, $simm10"> {
+ bits<10> simm10;
+ bits<4> rdp;
+
+ let Inst{31-25} = funct7;
+ let Inst{24-15} = simm10;
+ let Inst{11-8} = rdp;
+ let Inst{7} = 0b0;
+}
+
+let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
+class RVPUnaryImm8<bits<8> funct8, string opcodestr>
+ : RVInstIBase<0b010, OPC_OP_IMM_32, (outs GPR:$rd), (ins uimm8:$uimm8),
+ opcodestr, "$rd, $uimm8"> {
+ bits<8> uimm8;
+
+ let Inst{31-24} = funct8;
+ let Inst{23-16} = uimm8;
+ let Inst{15} = 0b0;
+}
+
+let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
+class RVPUnaryImm5<bits<3> f, string opcodestr>
+ : RVInstIBase<0b010, OPC_OP_IMM_32, (outs GPR:$rd),
+ (ins GPR:$rs1, uimm5:$uimm5), opcodestr, "$rd, $rs1, $uimm5"> {
+ bits<5> uimm5;
+ let Inst{31} = 0b1;
+ let Inst{30-28} = f;
+ let Inst{27} = 0b0;
+ let Inst{26-25} = 0b01;
+ let Inst{24-20} = uimm5;
+}
+
+let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
+class RVPUnaryImm4<bits<3> f, string opcodestr>
+ : RVInstIBase<0b010, OPC_OP_IMM_32, (outs GPR:$rd),
+ (ins GPR:$rs1, uimm4:$uimm4), opcodestr, "$rd, $rs1, $uimm4"> {
+ bits<4> uimm4;
+ let Inst{31} = 0b1;
+ let Inst{30-28} = f;
+ let Inst{27} = 0b0;
+ let Inst{26-24} = 0b001;
+ let Inst{23-20} = uimm4;
+}
+
+let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
+class RVPUnaryImm3<bits<3> f, string opcodestr>
+ : RVInstIBase<0b010, OPC_OP_IMM_32, (outs GPR:$rd),
+ (ins GPR:$rs1, uimm3:$uimm3), opcodestr, "$rd, $rs1, $uimm3"> {
+ bits<3> uimm3;
+ let Inst{31} = 0b1;
+ let Inst{30-28} = f;
+ let Inst{27} = 0b0;
+ let Inst{26-23} = 0b0001;
+ let Inst{22-20} = uimm3;
+}
+
+let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
+class RVPUnaryWUF<bits<2> w, bits<5> uf, string opcodestr>
+ : RVInstIBase<0b010, OPC_OP_IMM_32, (outs GPR:$rd), (ins GPR:$rs1),
+ opcodestr, "$rd, $rs1"> {
+ let Inst{31-27} = 0b11100;
+ let Inst{26-25} = w;
+ let Inst{24-20} = uf;
+}
+
+//===----------------------------------------------------------------------===//
+// Instructions
+//===----------------------------------------------------------------------===//
+
+let Predicates = [HasStdExtP] in {
+def CLS : Unary_r<0b011000000011, 0b001, "cls">;
+def ABS : Unary_r<0b011000000111, 0b001, "abs">;
+} // Predicates = [HasStdExtP]
+let Predicates = [HasStdExtP, IsRV32] in
+def REV_RV32 : Unary_r<0b011010011111, 0b101, "rev">;
+
+let Predicates = [HasStdExtP, IsRV64] in {
+def REV16 : Unary_r<0b011010110000, 0b101, "rev16">;
+def REV_RV64 : Unary_r<0b011110111111, 0b101, "rev">;
+
+def CLSW : UnaryW_r<0b011000000011, 0b001, "clsw">;
+def ABSW : UnaryW_r<0b011000000111, 0b001, "absw">;
+} // Predicates = [HasStdExtP, IsRV64]
+
+let Predicates = [HasStdExtP] in {
+def PSLLI_B : RVPUnaryImm3<0b000, "pslli.b">;
+def PSLLI_H : RVPUnaryImm4<0b000, "pslli.h">;
+def PSSLAI_H : RVPUnaryImm4<0b101, "psslai.h">;
+} // Predicates = [HasStdExtP]
+let DecoderNamespace = "RV32Only",
+ Predicates = [HasStdExtP, IsRV32] in
+def SSLAI : RVPUnaryImm5<0b101, "sslai">;
+let Predicates = [HasStdExtP, IsRV64] in {
+def PSLLI_W : RVPUnaryImm5<0b000, "pslli.w">;
+def PSSLAI_W : RVPUnaryImm5<0b101, "psslai.w">;
+} // Predicates = [HasStdExtP, IsRV64]
+
+let Predicates = [HasStdExtP] in
+def PLI_H : RVPUnaryImm9<0b1011000, "pli.h">;
+let Predicates = [HasStdExtP, IsRV64] in
+def PLI_W : RVPUnaryImm9<0b1011001, "pli.w">;
+let Predicates = [HasStdExtP] in
+def PLI_B : RVPUnaryImm8<0b10110100, "pli.b">;
+
+let Predicates = [HasStdExtP] in {
+def PSEXT_H_B : RVPUnaryWUF<0b00, 0b00100, "psext.h.b">;
+def PSABS_H : RVPUnaryWUF<0b00, 0b00111, "psabs.h">;
+def PSABS_B : RVPUnaryWUF<0b10, 0b00111, "psabs.b">;
+} // Predicates = [HasStdExtP]
+let Predicates = [HasStdExtP, IsRV64] in {
+def PSEXT_W_B : RVPUnaryWUF<0b01, 0b00100, "psext.w.b">;
+def PSEXT_W_H : RVPUnaryWUF<0b01, 0b00101, "psext.w.h">;
+} // Predicates = [HasStdExtP, IsRV64]
+
+let Predicates = [HasStdExtP] in
+def PLUI_H : RVPUnaryImm9<0b1111000, "plui.h">;
+let Predicates = [HasStdExtP, IsRV64] in
+def PLUI_W : RVPUnaryImm9<0b1111001, "plui.w">;
diff --git a/llvm/test/CodeGen/RISCV/attributes.ll b/llvm/test/CodeGen/RISCV/attributes.ll
index 49e05f9acb4b2..10a15ff9de506 100644
--- a/llvm/test/CodeGen/RISCV/attributes.ll
+++ b/llvm/test/CodeGen/RISCV/attributes.ll
@@ -327,6 +327,7 @@
; RUN: llc -mtriple=riscv64 -mattr=+sdext %s -o - | FileCheck --check-prefix=RV64SDEXT %s
; RUN: llc -mtriple=riscv64 -mattr=+sdtrig %s -o - | FileCheck --check-prefix=RV64SDTRIG %s
; RUN: llc -mtriple=riscv64 -mattr=+experimental-xqccmp %s -o - | FileCheck --check-prefix=RV64XQCCMP %s
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-p %s -o - | FileCheck --check-prefix=RV64P %s
; Tests for profile features.
@@ -511,6 +512,7 @@
; RV32SUPM: .attribute 5, "rv32i2p1_supm1p0"
; RV32SMCTR: .attribute 5, "rv32i2p1_smctr1p0_sscsrind1p0"
; RV32SSCTR: .attribute 5, "rv32i2p1_sscsrind1p0_ssctr1p0"
+; RV32P: .attribute 5, "rv32i2p1_p0p14"
; RV64M: .attribute 5, "rv64i2p1_m2p0_zmmul1p0"
; RV64ZMMUL: .attribute 5, "rv64i2p1_zmmul1p0"
@@ -668,6 +670,7 @@
; RV64SDEXT: .attribute 5, "rv64i2p1_sdext1p0"
; RV64SDTRIG: .attribute 5, "rv64i2p1_sdtrig1p0"
; RV64XQCCMP: .attribute 5, "rv64i2p1_zca1p0_xqccmp0p1"
+; RV64P: .attribute 5, "rv64i2p1_p0p14"
; RVI20U32: .attribute 5, "rv32i2p1"
; RVI20U64: .attribute 5, "rv64i2p1"
diff --git a/llvm/test/MC/RISCV/invalid-instruction-spellcheck.s b/llvm/test/MC/RISCV/invalid-instruction-spellcheck.s
index c5c0d2f3a0b12..8e8c42e033b8a 100644
--- a/llvm/test/MC/RISCV/invalid-instruction-spellcheck.s
+++ b/llvm/test/MC/RISCV/invalid-instruction-spellcheck.s
@@ -22,10 +22,10 @@ fl ft0, 0(sp)
# CHECK-RV64IF: did you mean: flw, la, lb, ld, lh, li, lw
# CHECK-NEXT: fl ft0, 0(sp)
-addd x1, x1, x1
+addc x1, x1, x1
# CHECK-RV32: did you mean: add, addi
# CHECK-RV64: did you mean: add, addi, addw
-# CHECK-NEXT: addd x1, x1, x1
+# CHECK-NEXT: addc x1, x1, x1
vm x0, x0
# CHECK: did you mean: mv
diff --git a/llvm/test/MC/RISCV/rv32p-invalid.s b/llvm/test/MC/RISCV/rv32p-invalid.s
new file mode 100644
index 0000000000000..f6410eb68ea33
--- /dev/null
+++ b/llvm/test/MC/RISCV/rv32p-invalid.s
@@ -0,0 +1,17 @@
+# RUN: not llvm-mc -triple=riscv32 --mattr=+experimental-p %s 2>&1 \
+# RUN: | FileCheck %s --check-prefixes=CHECK-ERROR
+
+# Imm overflow
+pli.h a0, 0x400
+# CHECK-ERROR: immediate must be an integer in the range [-512, 511]
+pli.b a0, 0x200
+# CHECK-ERROR: immediate must be an integer in the range [0, 255]
+
+pslli.b a6, a7, 100
+# CHECK-ERROR: immediate must be an integer in the range [0, 7]
+pslli.h ra, sp, 100
+# CHECK-ERROR: immediate must be an integer in the range [0, 15]
+psslai.h t0, t1, 100
+# CHECK-ERROR: immediate must be an integer in the range [0, 15]
+sslai a4, a5, -1
+# CHECK-ERROR: immediate must be an integer in the range [0, 31]
diff --git a/llvm/test/MC/RISCV/rv32p-valid.s b/llvm/test/MC/RISCV/rv32p-valid.s
index e2e366593f9b9..46800c429b37b 100644
--- a/llvm/test/MC/RISCV/rv32p-valid.s
+++ b/llvm/test/MC/RISCV/rv32p-valid.s
@@ -1,36 +1,75 @@
# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-p -M no-aliases -show-encoding \
# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+experimental-p < %s \
-# RUN: | llvm-objdump --mattr=+experimental-p -M no-aliases -d -r - \
+# RUN: | llvm-objdump --mattr=+experimental-p -M no-aliases -d -r --no-print-imm-hex - \
# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
-# CHECK-ASM-AND-OBJ: sh1add a0, a1, a2
-# CHECK-ASM: encoding: [0x33,0xa5,0xc5,0x20]
-sh1add a0, a1, a2
# CHECK-ASM-AND-OBJ: clz a0, a1
# CHECK-ASM: encoding: [0x13,0x95,0x05,0x60]
clz a0, a1
+# CHECK-ASM-AND-OBJ: cls a1, a2
+# CHECK-ASM: encoding: [0x93,0x15,0x36,0x60]
+cls a1, a2
# CHECK-ASM-AND-OBJ: sext.b a2, a3
# CHECK-ASM: encoding: [0x13,0x96,0x46,0x60]
sext.b a2, a3
# CHECK-ASM-AND-OBJ: sext.h t0, t1
# CHECK-ASM: encoding: [0x93,0x12,0x53,0x60]
sext.h t0, t1
+# CHECK-ASM-AND-OBJ: abs a4, a5
+# CHECK-ASM: encoding: [0x13,0x97,0x77,0x60]
+abs a4, a5
+# CHECK-ASM-AND-OBJ: rev8 s0, s1
+# CHECK-ASM: encoding: [0x13,0xd4,0x84,0x69]
+rev8 s0, s1
+# CHECK-ASM-AND-OBJ: rev s2, s3
+# CHECK-ASM: encoding: [0x13,0xd9,0xf9,0x69]
+rev s2, s3
+# CHECK-ASM-AND-OBJ: sh1add a0, a1, a2
+# CHECK-ASM: encoding: [0x33,0xa5,0xc5,0x20]
+sh1add a0, a1, a2
+# CHECK-ASM-AND-OBJ: pack s0, s1, s2
+# CHECK-ASM: encoding: [0x33,0xc4,0x24,0x09]
+pack s0, s1, s2
# CHECK-ASM-AND-OBJ: min t0, t1, t2
# CHECK-ASM: encoding: [0xb3,0x42,0x73,0x0a]
min t0, t1, t2
-# CHECK-ASM-AND-OBJ: minu t0, t1, t2
-# CHECK-ASM: encoding: [0xb3,0x52,0x73,0x0a]
-minu t0, t1, t2
+# CHECK-ASM-AND-OBJ: minu ra, sp, gp
+# CHECK-ASM: encoding: [0xb3,0x50,0x31,0x0a]
+minu ra, sp, gp
# CHECK-ASM-AND-OBJ: max t3, t4, t5
# CHECK-ASM: encoding: [0x33,0xee,0xee,0x0b]
max t3, t4, t5
# CHECK-ASM-AND-OBJ: maxu a4, a5, a6
# CHECK-ASM: encoding: [0x33,0xf7,0x07,0x0b]
maxu a4, a5, a6
-# CHECK-ASM-AND-OBJ: pack s0, s1, s2
-# CHECK-ASM: encoding: [0x33,0xc4,0x24,0x09]
-pack s0, s1, s2
-# CHECK-ASM-AND-OBJ: rev8 s0, s1
-# CHECK-ASM: encoding: [0x13,0xd4,0x84,0x69]
-rev8 s0, s1
+# CHECK-ASM-AND-OBJ: pslli.b a6, a7, 0
+# CHECK-ASM: encoding: [0x1b,0xa8,0x88,0x80]
+pslli.b a6, a7, 0
+# CHECK-ASM-AND-OBJ: pslli.h ra, sp, 1
+# CHECK-ASM: encoding: [0x9b,0x20,0x11,0x81]
+pslli.h ra, sp, 1
+# CHECK-ASM-AND-OBJ: psslai.h t0, t1, 2
+# CHECK-ASM: encoding: [0x9b,0x22,0x23,0xd1]
+psslai.h t0, t1, 2
+# CHECK-ASM-AND-OBJ: sslai a4, a5, 3
+# CHECK-ASM: encoding: [0x1b,0xa7,0x37,0xd2]
+sslai a4, a5, 3
+# CHECK-ASM-AND-OBJ: pli.h a5, 16
+# CHECK-ASM: encoding: [0x9b,0x27,0x08,0xb0]
+pli.h a5, 16
+# CHECK-ASM-AND-OBJ: pli.b a6, 16
+# CHECK-ASM: encoding: [0x1b,0x28,0x10,0xb4]
+pli.b a6, 16
+# CHECK-ASM-AND-OBJ: psext.h.b a7, a0
+# CHECK-ASM: encoding: [0x9b,0x28,0x45,0xe0]
+psext.h.b a7, a0
+# CHECK-ASM-AND-OBJ: psabs.h a1, a2
+# CHECK-ASM: encoding: [0x9b,0x25,0x76,0xe0]
+psabs.h a1, a2
+# CHECK-ASM-AND-OBJ: psabs.b t0, t1
+# CHECK-ASM: encoding: [0x9b,0x22,0x73,0xe4]
+psabs.b t0, t1
+# CHECK-ASM-AND-OBJ: plui.h gp, 32
+# CHECK-ASM: encoding: [0x9b,0x21,0x10,0xf0]
+plui.h gp, 32
diff --git a/llvm/test/MC/RISCV/rv64p-invalid.s b/llvm/test/MC/RISCV/rv64p-invalid.s
new file mode 100644
index 0000000000000..2132aecdcbc9b
--- /dev/null
+++ b/llvm/test/MC/RISCV/rv64p-invalid.s
@@ -0,0 +1,19 @@
+# RUN: not llvm-mc -triple=riscv64 --mattr=+experimental-p %s 2>&1 \
+# RUN: | FileCheck %s --check-prefixes=CHECK-ERROR
+
+# Imm overflow
+pli.h a0, 0x400
+# CHECK-ERROR: immediate must be an integer in the range [-512, 511]
+pli.w a1, -0x201
+# CHECK-ERROR: immediate must be an integer in the range [-512, 511]
+
+pslli.b a6, a7, 100
+# CHECK-ERROR: immediate must be an integer in the range [0, 7]
+pslli.h ra, sp, 100
+# CHECK-ERROR: immediate must be an integer in the range [0, 15]
+pslli.w ra, sp, 100
+# CHECK-ERROR: immediate must be an integer in the range [0, 31]
+psslai.h t0, t1, 100
+# CHECK-ERROR: immediate must be an integer in the range [0, 15]
+psslai.w a4, a5, -1
+# CHECK-ERROR: error: immediate must be an integer in the range [0, 31]
diff --git a/llvm/test/MC/RISCV/rv64p-valid.s b/llvm/test/MC/RISCV/rv64p-valid.s
index 1ec5ee312e100..f6be735fbeac0 100644
--- a/llvm/test/MC/RISCV/rv64p-valid.s
+++ b/llvm/test/MC/RISCV/rv64p-valid.s
@@ -1,39 +1,102 @@
-# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-p -M no-aliases -show-encoding \
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-p -riscv-no-aliases -show-encoding \
# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
-# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+experimental-p < %s \
-# RUN: | llvm-objdump --mattr=+experimental-p -M no-aliases -d -r - \
+# RUN: llvm-mc -filetype=obj --triple=riscv64 -mattr=+experimental-p < %s \
+# RUN: | llvm-objdump --triple=riscv64 --mattr=+experimental-p -M no-aliases --no-print-imm-hex -d -r - \
# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
-# CHECK-ASM-AND-OBJ: sh1add a0, a1, a2
-# CHECK-ASM: encoding: [0x33,0xa5,0xc5,0x20]
-sh1add a0, a1, a2
# CHECK-ASM-AND-OBJ: clz a0, a1
# CHECK-ASM: encoding: [0x13,0x95,0x05,0x60]
clz a0, a1
-# CHECK-ASM-AND-OBJ: clzw s0, s1
-# CHECK-ASM: encoding: [0x1b,0x94,0x04,0x60]
-clzw s0, s1
+# CHECK-ASM-AND-OBJ: cls a1, a2
+# CHECK-ASM: encoding: [0x93,0x15,0x36,0x60]
+cls a1, a2
# CHECK-ASM-AND-OBJ: sext.b a2, a3
# CHECK-ASM: encoding: [0x13,0x96,0x46,0x60]
sext.b a2, a3
# CHECK-ASM-AND-OBJ: sext.h t0, t1
# CHECK-ASM: encoding: [0x93,0x12,0x53,0x60]
sext.h t0, t1
+# CHECK-ASM-AND-OBJ: abs a4, a5
+# CHECK-ASM: encoding: [0x13,0x97,0x77,0x60]
+abs a4, a5
+# CHECK-ASM-AND-OBJ: rev16 s0, s1
+# CHECK-ASM: encoding: [0x13,0xd4,0x04,0x6b]
+rev16 s0, s1
+# CHECK-ASM-AND-OBJ: rev8 s0, s1
+# CHECK-ASM: encoding: [0x13,0xd4,0x84,0x6b]
+rev8 s0, s1
+# CHECK-ASM-AND-OBJ: rev s2, s3
+# CHECK-ASM: encoding: [0x13,0xd9,0xf9,0x7b]
+rev s2, s3
+# CHECK-ASM-AND-OBJ: clzw s0, s1
+# CHECK-ASM: encoding: [0x1b,0x94,0x04,0x60]
+clzw s0, s1
+# CHECK-ASM-AND-OBJ: clsw s2, s3
+# CHECK-ASM: encoding: [0x1b,0x99,0x39,0x60]
+clsw s2, s3
+# CHECK-ASM-AND-OBJ: absw s2, s3
+# CHECK-ASM: encoding: [0x1b,0x99,0x79,0x60]
+absw s2, s3
+# CHECK-ASM-AND-OBJ: sh1add a0, a1, a2
+# CHECK-ASM: encoding: [0x33,0xa5,0xc5,0x20]
+sh1add a0, a1, a2
+# CHECK-ASM-AND-OBJ: pack s0, s1, s2
+# CHECK-ASM: encoding: [0x33,0xc4,0x24,0x09]
+pack s0, s1, s2
# CHECK-ASM-AND-OBJ: min t0, t1, t2
# CHECK-ASM: encoding: [0xb3,0x42,0x73,0x0a]
min t0, t1, t2
-# CHECK-ASM-AND-OBJ: minu t0, t1, t2
-# CHECK-ASM: encoding: [0xb3,0x52,0x73,0x0a]
-minu t0, t1, t2
+# CHECK-ASM-AND-OBJ: minu ra, sp, gp
+# CHECK-ASM: encoding: [0xb3,0x50,0x31,0x0a]
+minu ra, sp, gp
# CHECK-ASM-AND-OBJ: max t3, t4, t5
# CHECK-ASM: encoding: [0x33,0xee,0xee,0x0b]
max t3, t4, t5
# CHECK-ASM-AND-OBJ: maxu a4, a5, a6
# CHECK-ASM: encoding: [0x33,0xf7,0x07,0x0b]
maxu a4, a5, a6
-# CHECK-ASM-AND-OBJ: pack s0, s1, s2
-# CHECK-ASM: encoding: [0x33,0xc4,0x24,0x09]
-pack s0, s1, s2
-# CHECK-ASM-AND-OBJ: rev8 s0, s1
-# CHECK-ASM: encoding: [0x13,0xd4,0x84,0x6b]
-rev8 s0, s1
+# CHECK-ASM-AND-OBJ: pslli.b a6, a7
+# CHECK-ASM: encoding: [0x1b,0xa8,0x88,0x80]
+pslli.b a6, a7, 0
+# CHECK-ASM-AND-OBJ: pslli.h ra, sp, 1
+# CHECK-ASM: encoding: [0x9b,0x20,0x11,0x81]
+pslli.h ra, sp, 1
+# CHECK-ASM-AND-OBJ: pslli.w ra, sp, 2
+# CHECK-ASM: encoding: [0x9b,0x20,0x21,0x82]
+pslli.w ra, sp, 2
+# CHECK-ASM-AND-OBJ: psslai.h t0, t1, 3
+# CHECK-ASM: encoding: [0x9b,0x22,0x33,0xd1]
+psslai.h t0, t1, 3
+# CHECK-ASM-AND-OBJ: psslai.w a4, a5, 4
+# CHECK-ASM: encoding: [0x1b,0xa7,0x47,0xd2]
+psslai.w a4, a5, 4
+# CHECK-ASM-AND-OBJ: pli.h a5, 5
+# CHECK-ASM: encoding: [0x9b,0xa7,0x02,0xb0]
+pli.h a5, 5
+# CHECK-ASM-AND-OBJ: pli.w a5, 5
+# CHECK-ASM: encoding: [0x9b,0xa7,0x02,0xb2]
+pli.w a5, 5
+# CHECK-ASM-AND-OBJ: pli.b a6, 6
+# CHECK-ASM: encoding: [0x1b,0x28,0x06,0xb4]
+pli.b a6, 6
+# CHECK-ASM-AND-OBJ: psext.h.b t3, a2
+# CHECK-ASM: encoding: [0x1b,0x2e,0x46,0xe0]
+psext.h.b t3, a2
+# CHECK-ASM-AND-OBJ: psext.w.b a2, s0
+# CHECK-ASM: encoding: [0x1b,0x26,0x44,0xe2]
+psext.w.b a2, s0
+# CHECK-ASM-AND-OBJ: psext.w.h t1, t3
+# CHECK-ASM: encoding: [0x1b,0x23,0x5e,0xe2]
+psext.w.h t1, t3
+# CHECK-ASM-AND-OBJ: psabs.h t1, t5
+# CHECK-ASM: encoding: [0x1b,0x23,0x7f,0xe0]
+psabs.h t1, t5
+# CHECK-ASM-AND-OBJ: psabs.b a0, s2
+# CHECK-ASM: encoding: [0x1b,0x25,0x79,0xe4]
+psabs.b a0, s2
+# CHECK-ASM-AND-OBJ: plui.h s2, 4
+# CHECK-ASM: encoding: [0x1b,0x29,0x02,0xf0]
+plui.h s2, 4
+# CHECK-ASM-AND-OBJ: plui.w a2, 1
+# CHECK-ASM: encoding: [0x1b,0xa6,0x00,0xf2]
+plui.w a2, 1
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kito-cheng
reviewed
Apr 30, 2025
topperc
reviewed
Apr 30, 2025
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||
| let Predicates = [HasStdExtP, IsRV64] in { | ||
| def REV16 : Unary_r<0b011010110000, 0b101, "rev16">; | ||
| def REV_RV64 : Unary_r<0b011110111111, 0b101, "rev">; |
There was a problem hiding this comment.
This encoding is incorrect as I already said here https://github.com/llvm/llvm-project/pull/123271/files#r2011058609
topperc
reviewed
Apr 30, 2025
| //===----------------------------------------------------------------------===// | ||
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||
| let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in | ||
| class RVPUnaryImm9<bits<7> funct7, string opcodestr> |
There was a problem hiding this comment.
Should this be Imm10 instead of Imm9 to match the simm10 field name?
| } // Predicates = [HasStdExtP, IsRV64] | ||
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| let Predicates = [HasStdExtP] in | ||
| def PLUI_H : RVPUnaryImm9<0b1111000, "plui.h">; |
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The immediate for plui.h is supposed to be encoded as imm[6|15:7]. That means the bits need to be rotated. I don't see this happening in the tablegen code.
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Is the assembly programmer supposed to write the immediate in as a 16-bit value that is divisible by 64 or are they supposed to just write the 10 upper bits similar to lui from the base ISA?
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| let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in | ||
| class RVPUnaryImm9<bits<7> funct7, string opcodestr> | ||
| : RVInstIBase<0b010, OPC_OP_IMM_32, (outs GPR:$rd), (ins simm10:$simm10), |
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For plui.w plui.h should this be an unsigned immediate?
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I sent a message to the mailing list https://lists.riscv.org/g/tech-p-ext/message/568. It's not clear to me if plui.w/h should diverge from base ISA lui which uses unsigned immediate.
| @@ -22,10 +22,10 @@ fl ft0, 0(sp) | |||
| # CHECK-RV64IF: did you mean: flw, la, lb, ld, lh, li, lw | |||
| # CHECK-NEXT: fl ft0, 0(sp) | |||
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| addd x1, x1, x1 | |||
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Why does this need to change in this patch? You didn't include addd in this patch.
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This patch adds support for non-GPR pair instructions in purposed Base P extension for RISC-V.
Documentation:
https://jhauser.us/RISCV/ext-P/RVP-baseInstrs-014.pdf
https://jhauser.us/RISCV/ext-P/RVP-instrEncodings-014b.pdf