[RISCV] TableGen-erate RISC-V SDNodes #138381
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This commit moves RISC-V to auto-generate its target-specific SDNode types. The biggest change is that SDNodes can now be validated against their expected type profiles, and that we don't need to edit several different files when declaring a new one. This takes Sergei's work in llvm#119709 and "finishes" it - by moving the final five RISCVISD opcodes into tablegen (including defining their types), and by ensuring the tablegen has expected closing scope comments. Only one opcode is not currently verifying on the in-tree tests: PROBED_ALLOCA, which I cannot make head or tail of what it should be doing, so I have just ensured it skips verification for the moment (as in Sergei's patch). Co-authored-by: Sergei Barannikov <[email protected]>
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@llvm/pr-subscribers-backend-risc-v Author: Sam Elliott (lenary) ChangesThis commit moves RISC-V to auto-generate its target-specific SDNode types. The biggest change is that SDNodes can now be validated against their expected type profiles, and that we don't need to edit several different files when declaring a new one. This takes Sergei's work in #119709 and "finishes" it - by moving the final five RISCVISD opcodes into tablegen (including defining their types), and by ensuring the tablegen has expected closing scope comments. Only one opcode is not currently verifying on the in-tree tests: Patch is 109.70 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/138381.diff 23 Files Affected:
diff --git a/llvm/lib/Target/RISCV/CMakeLists.txt b/llvm/lib/Target/RISCV/CMakeLists.txt
index b0456aa25f09e..e32d6eab3b977 100644
--- a/llvm/lib/Target/RISCV/CMakeLists.txt
+++ b/llvm/lib/Target/RISCV/CMakeLists.txt
@@ -16,6 +16,7 @@ tablegen(LLVM RISCVGenRegisterInfo.inc -gen-register-info)
tablegen(LLVM RISCVGenSearchableTables.inc -gen-searchable-tables)
tablegen(LLVM RISCVGenSubtargetInfo.inc -gen-subtarget)
tablegen(LLVM RISCVGenExegesis.inc -gen-exegesis)
+tablegen(LLVM RISCVGenSDNodeInfo.inc -gen-sd-node-info)
set(LLVM_TARGET_DEFINITIONS RISCVGISel.td)
tablegen(LLVM RISCVGenGlobalISel.inc -gen-global-isel)
diff --git a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
index 86bdb4c7fd24c..fa7dac0624adc 100644
--- a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
@@ -11,6 +11,7 @@
//===----------------------------------------------------------------------===//
#include "RISCVISelDAGToDAG.h"
+#include "RISCVSelectionDAGInfo.h"
#include "MCTargetDesc/RISCVBaseInfo.h"
#include "MCTargetDesc/RISCVMCTargetDesc.h"
#include "MCTargetDesc/RISCVMatInt.h"
@@ -34,6 +35,9 @@ static cl::opt<bool> UsePseudoMovImm(
"constant materialization"),
cl::init(false));
+#define GET_DAGISEL_BODY RISCVDAGToDAGISel
+#include "RISCVGenDAGISel.inc"
+
void RISCVDAGToDAGISel::PreprocessISelDAG() {
SelectionDAG::allnodes_iterator Position = CurDAG->allnodes_end();
diff --git a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.h b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.h
index 0672b6ad8829e..af8d235c54012 100644
--- a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.h
+++ b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.h
@@ -191,6 +191,7 @@ class RISCVDAGToDAGISel : public SelectionDAGISel {
}
// Include the pieces autogenerated from the target description.
+#define GET_DAGISEL_DECL
#include "RISCVGenDAGISel.inc"
private:
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index 0d3003b59eeba..2637446646f38 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -6965,49 +6965,7 @@ static unsigned getRISCVVLOp(SDValue Op) {
#undef VP_CASE
}
-/// Return true if a RISC-V target specified op has a passthru operand.
-static bool hasPassthruOp(unsigned Opcode) {
- assert(Opcode > RISCVISD::FIRST_NUMBER &&
- Opcode <= RISCVISD::LAST_STRICTFP_OPCODE &&
- "not a RISC-V target specific op");
- static_assert(
- RISCVISD::LAST_VL_VECTOR_OP - RISCVISD::FIRST_VL_VECTOR_OP == 134 &&
- RISCVISD::LAST_STRICTFP_OPCODE - RISCVISD::FIRST_STRICTFP_OPCODE == 21 &&
- "adding target specific op should update this function");
- if (Opcode >= RISCVISD::ADD_VL && Opcode <= RISCVISD::VFMAX_VL)
- return true;
- if (Opcode == RISCVISD::FCOPYSIGN_VL)
- return true;
- if (Opcode >= RISCVISD::VWMUL_VL && Opcode <= RISCVISD::VFWSUB_W_VL)
- return true;
- if (Opcode == RISCVISD::SETCC_VL)
- return true;
- if (Opcode >= RISCVISD::STRICT_FADD_VL && Opcode <= RISCVISD::STRICT_FDIV_VL)
- return true;
- if (Opcode == RISCVISD::VMERGE_VL)
- return true;
- return false;
-}
-/// Return true if a RISC-V target specified op has a mask operand.
-static bool hasMaskOp(unsigned Opcode) {
- assert(Opcode > RISCVISD::FIRST_NUMBER &&
- Opcode <= RISCVISD::LAST_STRICTFP_OPCODE &&
- "not a RISC-V target specific op");
- static_assert(
- RISCVISD::LAST_VL_VECTOR_OP - RISCVISD::FIRST_VL_VECTOR_OP == 134 &&
- RISCVISD::LAST_STRICTFP_OPCODE - RISCVISD::FIRST_STRICTFP_OPCODE == 21 &&
- "adding target specific op should update this function");
- if (Opcode >= RISCVISD::TRUNCATE_VECTOR_VL && Opcode <= RISCVISD::SETCC_VL)
- return true;
- if (Opcode >= RISCVISD::VRGATHER_VX_VL &&
- Opcode <= RISCVISD::LAST_VL_VECTOR_OP)
- return true;
- if (Opcode >= RISCVISD::STRICT_FADD_VL &&
- Opcode <= RISCVISD::STRICT_VFROUND_NOEXCEPT_VL)
- return true;
- return false;
-}
static bool isPromotedOpNeedingSplit(SDValue Op,
const RISCVSubtarget &Subtarget) {
@@ -12606,9 +12564,12 @@ SDValue RISCVTargetLowering::lowerFixedLengthVectorSelectToRVV(
SDValue RISCVTargetLowering::lowerToScalableOp(SDValue Op,
SelectionDAG &DAG) const {
+ const auto &TSInfo =
+ static_cast<const RISCVSelectionDAGInfo &>(DAG.getSelectionDAGInfo());
+
unsigned NewOpc = getRISCVVLOp(Op);
- bool HasPassthruOp = hasPassthruOp(NewOpc);
- bool HasMask = hasMaskOp(NewOpc);
+ bool HasPassthruOp = TSInfo.hasPassthruOp(NewOpc);
+ bool HasMask = TSInfo.hasMaskOp(NewOpc);
MVT VT = Op.getSimpleValueType();
MVT ContainerVT = getContainerForFixedLengthVector(VT);
@@ -12659,8 +12620,11 @@ SDValue RISCVTargetLowering::lowerToScalableOp(SDValue Op,
// * Fixed-length vectors are converted to their scalable-vector container
// types.
SDValue RISCVTargetLowering::lowerVPOp(SDValue Op, SelectionDAG &DAG) const {
+ const auto &TSInfo =
+ static_cast<const RISCVSelectionDAGInfo &>(DAG.getSelectionDAGInfo());
+
unsigned RISCVISDOpc = getRISCVVLOp(Op);
- bool HasPassthruOp = hasPassthruOp(RISCVISDOpc);
+ bool HasPassthruOp = TSInfo.hasPassthruOp(RISCVISDOpc);
SDLoc DL(Op);
MVT VT = Op.getSimpleValueType();
@@ -13635,7 +13599,7 @@ SDValue RISCVTargetLowering::lowerEH_DWARF_CFA(SDValue Op,
// Returns the opcode of the target-specific SDNode that implements the 32-bit
// form of the given Opcode.
-static RISCVISD::NodeType getRISCVWOpcode(unsigned Opcode) {
+static unsigned getRISCVWOpcode(unsigned Opcode) {
switch (Opcode) {
default:
llvm_unreachable("Unexpected opcode");
@@ -13666,7 +13630,7 @@ static RISCVISD::NodeType getRISCVWOpcode(unsigned Opcode) {
static SDValue customLegalizeToWOp(SDNode *N, SelectionDAG &DAG,
unsigned ExtOpc = ISD::ANY_EXTEND) {
SDLoc DL(N);
- RISCVISD::NodeType WOpcode = getRISCVWOpcode(N->getOpcode());
+ unsigned WOpcode = getRISCVWOpcode(N->getOpcode());
SDValue NewOp0 = DAG.getNode(ExtOpc, DL, MVT::i64, N->getOperand(0));
SDValue NewOp1 = DAG.getNode(ExtOpc, DL, MVT::i64, N->getOperand(1));
SDValue NewRes = DAG.getNode(WOpcode, DL, MVT::i64, NewOp0, NewOp1);
@@ -18411,15 +18375,9 @@ static SDValue combineToVWMACC(SDNode *N, SelectionDAG &DAG,
if (AddMask != MulMask || AddVL != MulVL)
return SDValue();
- unsigned Opc = RISCVISD::VWMACC_VL + MulOp.getOpcode() - RISCVISD::VWMUL_VL;
- static_assert(RISCVISD::VWMACC_VL + 1 == RISCVISD::VWMACCU_VL,
- "Unexpected opcode after VWMACC_VL");
- static_assert(RISCVISD::VWMACC_VL + 2 == RISCVISD::VWMACCSU_VL,
- "Unexpected opcode after VWMACC_VL!");
- static_assert(RISCVISD::VWMUL_VL + 1 == RISCVISD::VWMULU_VL,
- "Unexpected opcode after VWMUL_VL!");
- static_assert(RISCVISD::VWMUL_VL + 2 == RISCVISD::VWMULSU_VL,
- "Unexpected opcode after VWMUL_VL!");
+ const auto &TSInfo =
+ static_cast<const RISCVSelectionDAGInfo &>(DAG.getSelectionDAGInfo());
+ unsigned Opc = TSInfo.getMAccOpcode(MulOp.getOpcode());
SDLoc DL(N);
EVT VT = N->getValueType(0);
@@ -22169,283 +22127,6 @@ bool RISCVTargetLowering::mayBeEmittedAsTailCall(const CallInst *CI) const {
return CI->isTailCall();
}
-const char *RISCVTargetLowering::getTargetNodeName(unsigned Opcode) const {
-#define NODE_NAME_CASE(NODE) \
- case RISCVISD::NODE: \
- return "RISCVISD::" #NODE;
- // clang-format off
- switch ((RISCVISD::NodeType)Opcode) {
- case RISCVISD::FIRST_NUMBER:
- break;
- NODE_NAME_CASE(RET_GLUE)
- NODE_NAME_CASE(SRET_GLUE)
- NODE_NAME_CASE(MRET_GLUE)
- NODE_NAME_CASE(QC_C_MILEAVERET_GLUE)
- NODE_NAME_CASE(CALL)
- NODE_NAME_CASE(TAIL)
- NODE_NAME_CASE(SELECT_CC)
- NODE_NAME_CASE(BR_CC)
- NODE_NAME_CASE(BuildGPRPair)
- NODE_NAME_CASE(SplitGPRPair)
- NODE_NAME_CASE(BuildPairF64)
- NODE_NAME_CASE(SplitF64)
- NODE_NAME_CASE(ADD_LO)
- NODE_NAME_CASE(HI)
- NODE_NAME_CASE(LLA)
- NODE_NAME_CASE(ADD_TPREL)
- NODE_NAME_CASE(MULHSU)
- NODE_NAME_CASE(SHL_ADD)
- NODE_NAME_CASE(SLLW)
- NODE_NAME_CASE(SRAW)
- NODE_NAME_CASE(SRLW)
- NODE_NAME_CASE(DIVW)
- NODE_NAME_CASE(DIVUW)
- NODE_NAME_CASE(REMUW)
- NODE_NAME_CASE(ROLW)
- NODE_NAME_CASE(RORW)
- NODE_NAME_CASE(CLZW)
- NODE_NAME_CASE(CTZW)
- NODE_NAME_CASE(ABSW)
- NODE_NAME_CASE(FMV_H_X)
- NODE_NAME_CASE(FMV_X_ANYEXTH)
- NODE_NAME_CASE(FMV_X_SIGNEXTH)
- NODE_NAME_CASE(FMV_W_X_RV64)
- NODE_NAME_CASE(FMV_X_ANYEXTW_RV64)
- NODE_NAME_CASE(FCVT_X)
- NODE_NAME_CASE(FCVT_XU)
- NODE_NAME_CASE(FCVT_W_RV64)
- NODE_NAME_CASE(FCVT_WU_RV64)
- NODE_NAME_CASE(STRICT_FCVT_W_RV64)
- NODE_NAME_CASE(STRICT_FCVT_WU_RV64)
- NODE_NAME_CASE(FROUND)
- NODE_NAME_CASE(FCLASS)
- NODE_NAME_CASE(FSGNJX)
- NODE_NAME_CASE(FMAX)
- NODE_NAME_CASE(FMIN)
- NODE_NAME_CASE(FLI)
- NODE_NAME_CASE(READ_COUNTER_WIDE)
- NODE_NAME_CASE(BREV8)
- NODE_NAME_CASE(ORC_B)
- NODE_NAME_CASE(ZIP)
- NODE_NAME_CASE(UNZIP)
- NODE_NAME_CASE(CLMUL)
- NODE_NAME_CASE(CLMULH)
- NODE_NAME_CASE(CLMULR)
- NODE_NAME_CASE(MOPR)
- NODE_NAME_CASE(MOPRR)
- NODE_NAME_CASE(SHA256SIG0)
- NODE_NAME_CASE(SHA256SIG1)
- NODE_NAME_CASE(SHA256SUM0)
- NODE_NAME_CASE(SHA256SUM1)
- NODE_NAME_CASE(SM4KS)
- NODE_NAME_CASE(SM4ED)
- NODE_NAME_CASE(SM3P0)
- NODE_NAME_CASE(SM3P1)
- NODE_NAME_CASE(TH_LWD)
- NODE_NAME_CASE(TH_LWUD)
- NODE_NAME_CASE(TH_LDD)
- NODE_NAME_CASE(TH_SWD)
- NODE_NAME_CASE(TH_SDD)
- NODE_NAME_CASE(VMV_V_V_VL)
- NODE_NAME_CASE(VMV_V_X_VL)
- NODE_NAME_CASE(VFMV_V_F_VL)
- NODE_NAME_CASE(VMV_X_S)
- NODE_NAME_CASE(VMV_S_X_VL)
- NODE_NAME_CASE(VFMV_S_F_VL)
- NODE_NAME_CASE(SPLAT_VECTOR_SPLIT_I64_VL)
- NODE_NAME_CASE(READ_VLENB)
- NODE_NAME_CASE(TRUNCATE_VECTOR_VL)
- NODE_NAME_CASE(TRUNCATE_VECTOR_VL_SSAT)
- NODE_NAME_CASE(TRUNCATE_VECTOR_VL_USAT)
- NODE_NAME_CASE(VSLIDEUP_VL)
- NODE_NAME_CASE(VSLIDE1UP_VL)
- NODE_NAME_CASE(VSLIDEDOWN_VL)
- NODE_NAME_CASE(VSLIDE1DOWN_VL)
- NODE_NAME_CASE(VFSLIDE1UP_VL)
- NODE_NAME_CASE(VFSLIDE1DOWN_VL)
- NODE_NAME_CASE(VID_VL)
- NODE_NAME_CASE(VFNCVT_ROD_VL)
- NODE_NAME_CASE(VECREDUCE_ADD_VL)
- NODE_NAME_CASE(VECREDUCE_UMAX_VL)
- NODE_NAME_CASE(VECREDUCE_SMAX_VL)
- NODE_NAME_CASE(VECREDUCE_UMIN_VL)
- NODE_NAME_CASE(VECREDUCE_SMIN_VL)
- NODE_NAME_CASE(VECREDUCE_AND_VL)
- NODE_NAME_CASE(VECREDUCE_OR_VL)
- NODE_NAME_CASE(VECREDUCE_XOR_VL)
- NODE_NAME_CASE(VECREDUCE_FADD_VL)
- NODE_NAME_CASE(VECREDUCE_SEQ_FADD_VL)
- NODE_NAME_CASE(VECREDUCE_FMIN_VL)
- NODE_NAME_CASE(VECREDUCE_FMAX_VL)
- NODE_NAME_CASE(ADD_VL)
- NODE_NAME_CASE(AND_VL)
- NODE_NAME_CASE(MUL_VL)
- NODE_NAME_CASE(OR_VL)
- NODE_NAME_CASE(SDIV_VL)
- NODE_NAME_CASE(SHL_VL)
- NODE_NAME_CASE(SREM_VL)
- NODE_NAME_CASE(SRA_VL)
- NODE_NAME_CASE(SRL_VL)
- NODE_NAME_CASE(ROTL_VL)
- NODE_NAME_CASE(ROTR_VL)
- NODE_NAME_CASE(SUB_VL)
- NODE_NAME_CASE(UDIV_VL)
- NODE_NAME_CASE(UREM_VL)
- NODE_NAME_CASE(XOR_VL)
- NODE_NAME_CASE(AVGFLOORS_VL)
- NODE_NAME_CASE(AVGFLOORU_VL)
- NODE_NAME_CASE(AVGCEILS_VL)
- NODE_NAME_CASE(AVGCEILU_VL)
- NODE_NAME_CASE(SADDSAT_VL)
- NODE_NAME_CASE(UADDSAT_VL)
- NODE_NAME_CASE(SSUBSAT_VL)
- NODE_NAME_CASE(USUBSAT_VL)
- NODE_NAME_CASE(FADD_VL)
- NODE_NAME_CASE(FSUB_VL)
- NODE_NAME_CASE(FMUL_VL)
- NODE_NAME_CASE(FDIV_VL)
- NODE_NAME_CASE(FNEG_VL)
- NODE_NAME_CASE(FABS_VL)
- NODE_NAME_CASE(FSQRT_VL)
- NODE_NAME_CASE(FCLASS_VL)
- NODE_NAME_CASE(VFMADD_VL)
- NODE_NAME_CASE(VFNMADD_VL)
- NODE_NAME_CASE(VFMSUB_VL)
- NODE_NAME_CASE(VFNMSUB_VL)
- NODE_NAME_CASE(VFWMADD_VL)
- NODE_NAME_CASE(VFWNMADD_VL)
- NODE_NAME_CASE(VFWMSUB_VL)
- NODE_NAME_CASE(VFWNMSUB_VL)
- NODE_NAME_CASE(FCOPYSIGN_VL)
- NODE_NAME_CASE(SMIN_VL)
- NODE_NAME_CASE(SMAX_VL)
- NODE_NAME_CASE(UMIN_VL)
- NODE_NAME_CASE(UMAX_VL)
- NODE_NAME_CASE(BITREVERSE_VL)
- NODE_NAME_CASE(BSWAP_VL)
- NODE_NAME_CASE(CTLZ_VL)
- NODE_NAME_CASE(CTTZ_VL)
- NODE_NAME_CASE(CTPOP_VL)
- NODE_NAME_CASE(VFMIN_VL)
- NODE_NAME_CASE(VFMAX_VL)
- NODE_NAME_CASE(MULHS_VL)
- NODE_NAME_CASE(MULHU_VL)
- NODE_NAME_CASE(VFCVT_RTZ_X_F_VL)
- NODE_NAME_CASE(VFCVT_RTZ_XU_F_VL)
- NODE_NAME_CASE(VFCVT_RM_X_F_VL)
- NODE_NAME_CASE(VFCVT_RM_XU_F_VL)
- NODE_NAME_CASE(VFROUND_NOEXCEPT_VL)
- NODE_NAME_CASE(SINT_TO_FP_VL)
- NODE_NAME_CASE(UINT_TO_FP_VL)
- NODE_NAME_CASE(VFCVT_RM_F_XU_VL)
- NODE_NAME_CASE(VFCVT_RM_F_X_VL)
- NODE_NAME_CASE(FP_EXTEND_VL)
- NODE_NAME_CASE(FP_ROUND_VL)
- NODE_NAME_CASE(STRICT_FADD_VL)
- NODE_NAME_CASE(STRICT_FSUB_VL)
- NODE_NAME_CASE(STRICT_FMUL_VL)
- NODE_NAME_CASE(STRICT_FDIV_VL)
- NODE_NAME_CASE(STRICT_FSQRT_VL)
- NODE_NAME_CASE(STRICT_VFMADD_VL)
- NODE_NAME_CASE(STRICT_VFNMADD_VL)
- NODE_NAME_CASE(STRICT_VFMSUB_VL)
- NODE_NAME_CASE(STRICT_VFNMSUB_VL)
- NODE_NAME_CASE(STRICT_FP_ROUND_VL)
- NODE_NAME_CASE(STRICT_FP_EXTEND_VL)
- NODE_NAME_CASE(STRICT_VFNCVT_ROD_VL)
- NODE_NAME_CASE(STRICT_SINT_TO_FP_VL)
- NODE_NAME_CASE(STRICT_UINT_TO_FP_VL)
- NODE_NAME_CASE(STRICT_VFCVT_RM_X_F_VL)
- NODE_NAME_CASE(STRICT_VFCVT_RTZ_X_F_VL)
- NODE_NAME_CASE(STRICT_VFCVT_RTZ_XU_F_VL)
- NODE_NAME_CASE(STRICT_FSETCC_VL)
- NODE_NAME_CASE(STRICT_FSETCCS_VL)
- NODE_NAME_CASE(STRICT_VFROUND_NOEXCEPT_VL)
- NODE_NAME_CASE(VWMUL_VL)
- NODE_NAME_CASE(VWMULU_VL)
- NODE_NAME_CASE(VWMULSU_VL)
- NODE_NAME_CASE(VWADD_VL)
- NODE_NAME_CASE(VWADDU_VL)
- NODE_NAME_CASE(VWSUB_VL)
- NODE_NAME_CASE(VWSUBU_VL)
- NODE_NAME_CASE(VWADD_W_VL)
- NODE_NAME_CASE(VWADDU_W_VL)
- NODE_NAME_CASE(VWSUB_W_VL)
- NODE_NAME_CASE(VWSUBU_W_VL)
- NODE_NAME_CASE(VWSLL_VL)
- NODE_NAME_CASE(VFWMUL_VL)
- NODE_NAME_CASE(VFWADD_VL)
- NODE_NAME_CASE(VFWSUB_VL)
- NODE_NAME_CASE(VFWADD_W_VL)
- NODE_NAME_CASE(VFWSUB_W_VL)
- NODE_NAME_CASE(VWMACC_VL)
- NODE_NAME_CASE(VWMACCU_VL)
- NODE_NAME_CASE(VWMACCSU_VL)
- NODE_NAME_CASE(SETCC_VL)
- NODE_NAME_CASE(VMERGE_VL)
- NODE_NAME_CASE(VMAND_VL)
- NODE_NAME_CASE(VMOR_VL)
- NODE_NAME_CASE(VMXOR_VL)
- NODE_NAME_CASE(VMCLR_VL)
- NODE_NAME_CASE(VMSET_VL)
- NODE_NAME_CASE(VRGATHER_VX_VL)
- NODE_NAME_CASE(VRGATHER_VV_VL)
- NODE_NAME_CASE(VRGATHEREI16_VV_VL)
- NODE_NAME_CASE(VSEXT_VL)
- NODE_NAME_CASE(VZEXT_VL)
- NODE_NAME_CASE(VCPOP_VL)
- NODE_NAME_CASE(VFIRST_VL)
- NODE_NAME_CASE(RI_VINSERT_VL)
- NODE_NAME_CASE(RI_VZIPEVEN_VL)
- NODE_NAME_CASE(RI_VZIPODD_VL)
- NODE_NAME_CASE(RI_VZIP2A_VL)
- NODE_NAME_CASE(RI_VZIP2B_VL)
- NODE_NAME_CASE(RI_VUNZIP2A_VL)
- NODE_NAME_CASE(RI_VUNZIP2B_VL)
- NODE_NAME_CASE(RI_VEXTRACT)
- NODE_NAME_CASE(READ_CSR)
- NODE_NAME_CASE(WRITE_CSR)
- NODE_NAME_CASE(SWAP_CSR)
- NODE_NAME_CASE(CZERO_EQZ)
- NODE_NAME_CASE(CZERO_NEZ)
- NODE_NAME_CASE(SW_GUARDED_BRIND)
- NODE_NAME_CASE(SW_GUARDED_CALL)
- NODE_NAME_CASE(SW_GUARDED_TAIL)
- NODE_NAME_CASE(TUPLE_INSERT)
- NODE_NAME_CASE(TUPLE_EXTRACT)
- NODE_NAME_CASE(SF_VC_XV_SE)
- NODE_NAME_CASE(SF_VC_IV_SE)
- NODE_NAME_CASE(SF_VC_VV_SE)
- NODE_NAME_CASE(SF_VC_FV_SE)
- NODE_NAME_CASE(SF_VC_XVV_SE)
- NODE_NAME_CASE(SF_VC_IVV_SE)
- NODE_NAME_CASE(SF_VC_VVV_SE)
- NODE_NAME_CASE(SF_VC_FVV_SE)
- NODE_NAME_CASE(SF_VC_XVW_SE)
- NODE_NAME_CASE(SF_VC_IVW_SE)
- NODE_NAME_CASE(SF_VC_VVW_SE)
- NODE_NAME_CASE(SF_VC_FVW_SE)
- NODE_NAME_CASE(SF_VC_V_X_SE)
- NODE_NAME_CASE(SF_VC_V_I_SE)
- NODE_NAME_CASE(SF_VC_V_XV_SE)
- NODE_NAME_CASE(SF_VC_V_IV_SE)
- NODE_NAME_CASE(SF_VC_V_VV_SE)
- NODE_NAME_CASE(SF_VC_V_FV_SE)
- NODE_NAME_CASE(SF_VC_V_XVV_SE)
- NODE_NAME_CASE(SF_VC_V_IVV_SE)
- NODE_NAME_CASE(SF_VC_V_VVV_SE)
- NODE_NAME_CASE(SF_VC_V_FVV_SE)
- NODE_NAME_CASE(SF_VC_V_XVW_SE)
- NODE_NAME_CASE(SF_VC_V_IVW_SE)
- NODE_NAME_CASE(SF_VC_V_VVW_SE)
- NODE_NAME_CASE(SF_VC_V_FVW_SE)
- NODE_NAME_CASE(PROBED_ALLOCA)
- }
- // clang-format on
- return nullptr;
-#undef NODE_NAME_CASE
-}
-
/// getConstraintType - Given a constraint letter, return the type of
/// constraint it is for this target.
RISCVTargetLowering::ConstraintType
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.h b/llvm/lib/Target/RISCV/RISCVISelLowering.h
index ba24a0c324f51..d58225e79d09a 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.h
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.h
@@ -26,507 +26,6 @@ class InstructionCost;
class RISCVSubtarget;
struct RISCVRegisterInfo;
-namespace RISCVISD {
-// clang-format off
-enum NodeType : unsigned {
- FIRST_NUMBER = ISD::BUILTIN_OP_END,
- RET_GLUE,
- SRET_GLUE,
- MRET_GLUE,
- QC_C_MILEAVERET_GLUE,
- CALL,
- TAIL,
- /// Select with condition operator - This selects between a true value and
- /// a false value (ops #3 and #4) based on the boolean result of comparing
- /// the lhs and rhs (ops #0 and #1) of a conditional expression with the
- /// condition code in op #2, a XLenVT constant from the ISD::CondCode enum.
- /// The lhs and rhs are XLenVT integers. The true and false values can be
- /// integer or floating point.
- SELECT_CC,
- BR_CC,
-
- /// Turn a pair of `i<xlen>`s into an even-odd register pair (`untyped`).
- /// - Output: `untyped` even-odd register pair
- /// - Input 0: `i<xlen>` low-order bits, for even register.
- /// - Input 1: `i<xlen>` high-order bits, for odd register.
- BuildGPRPair,
-
- /// Turn an even-odd register pair (`untyped`) into a pair of `i<xlen>`s.
- /// - Output 0: `i<xlen>` low-order bits, from even register.
- /// - Output 1: `i<xlen>` high-order bits, from odd register.
- /// - Input: `untyped` even-odd register pair
- SplitGPRPair,
-
- /// Turns a pair of `i32`s into an `f64`. Needed for rv32d/ilp32.
- /// - Output: `f64`.
- /// - Input 0: low-order bits (31-0) (as `i32`), for even register.
- /// - Input 1: high-order bits (63-32) (as `i32`), for odd register.
- BuildPairF64,
-
- /// Turns a `f64` into a pair of `i32`s. Needed for rv32d/ilp32.
- /// - Output 0: low-order bits (31-0) (as `i32`), from even register.
- /// - Output 1: high-order bits (63-32) (as `i32`), from odd register.
- /// - Input 0: `f64`.
- SplitF64,
-
- // Add the Lo 12 bits from an address. Selected to ADDI.
- ADD_LO,
- // Get the Hi 20 bits from an address. Selected to LUI.
- HI,
-
- // Represents an AUIPC+ADDI pair. Selected to PseudoLLA.
- LLA,
-
- // Selected as PseudoAddTPRel. Used to emit a TP-relative relocation.
- ADD_TPREL,
-
- // Multiply high for signedxunsigned.
- MULHSU,
-
- // Represents (ADD (SHL a, b), c) with the arguments appearing in the order
- // a, b, c. 'b' must be a constant. Maps to sh1add/sh2add/sh3add with zba
- // or addsl with XTheadBa.
- SHL_ADD,
-
- // RV64I shifts, directly matching the semantics of the named RISC-V
- // instructions.
- SLLW,
- SRAW,
- SRLW,
- // 32-bit operations from RV64M that can't be simply matched with a pattern
- // at instruction selection time. These have undefined behavior for division
- // by 0 or overflow (divw) like their target independent counterparts.
- DIVW,
- DIVUW,
- REMUW,
- // RV64IB rotates, directly matching the semantics of the named RISC-V
- // instructions.
- ROLW,
- RORW,
- // RV64IZbb bit counting instructions directly matching the semantics of the
- // named RISC-V instructions.
- CLZW,
- CTZW,
-
- // RV64IZbb absolute value for i32. Expanded to (max (negw X), X) during isel.
- ABSW,
-
- // FPR<->GPR transfer operations when the FPR is smaller than XLEN, needed as
- // XLEN is the only legal integer width.
- //
- // FMV_H_X matches the semantics of the FMV.H.X.
- // FMV_X_ANYEXTH is similar to FMV.X.H but has an any-extended result.
- // FMV_X_SIGNEXTH is similar to FMV.X.H and has a sign-extended result.
- // FMV_W_X_RV64 matches the semantics of the FMV.W.X.
- // FMV_X_ANYEXTW_RV64 is similar to FMV.X.W but has an any-extended result.
- //
- // This is a more convenient semantic for producing dagcombines that remove
- // unnecessary GPR->FPR->GPR moves.
- FMV_H_X,
- FMV_X_ANYEXTH,
- FMV_X_SIGNEXTH,
- FMV_W_X_RV64,
- FMV_X_ANYEXTW_RV64,
- // FP to XLen int conversions. Corresponds to fcvt.l(u).s/d/h on RV64 and
- // fcvt.w(u).s/d/h on RV32. Unlike FP_TO_S/UINT these saturate out of
- // range inputs. These are used for FP_TO_S/UINT_SAT lowering. Rounding mode
- // is passed as a TargetConstant operand using the RISCVFPRndMode enum.
- FCVT_X,
- FCVT_XU,
- // FP to 32 bit int conversions fo...
[truncated]
|
s-barannikov
reviewed
May 3, 2025
topperc
reviewed
May 8, 2025
s-barannikov
reviewed
May 8, 2025
| @@ -14,6 +14,15 @@ | |||
| // RISC-V specific DAG Nodes. | |||
| //===----------------------------------------------------------------------===// | |||
|
|
|||
| class RVSDNode<string opcode, SDTypeProfile type_profile, | |||
| list<SDNodeProperty> properties = []> | |||
There was a problem hiding this comment.
Suggested change
| list<SDNodeProperty> properties = []> | |
| list<SDNodeProperty> properties = []> |
* main: (420 commits) [AArch64] Merge scaled and unscaled narrow zero stores (llvm#136705) [RISCV] One last migration to getInsertSubvector [nfc] [flang][OpenMP] Update `do concurrent` mapping pass to use `fir.do_concurrent` op (llvm#138489) [MLIR][LLVM] Fix llvm.mlir.global mismatching print and parser order (llvm#138986) [lld][NFC] Fix minor typo in docs (llvm#138898) [RISCV] Migrate getConstant indexed insert/extract subvector to new API (llvm#139111) GlobalISel: Translate minimumnum and maximumnum (llvm#139106) [MemProf] Simplify unittest save and restore of options (llvm#139117) [BOLT][AArch64] Patch functions targeted by optional relocs (llvm#138750) [Coverage] Support -fprofile-list for cold function coverage (llvm#136333) Remove unused forward decl (llvm#139108) [AMDGPU][NFC] Get rid of OPW constants. (llvm#139074) [CIR] Upstream extract op for VectorType (llvm#138413) [mlir][xegpu] Handle scalar uniform ops in SIMT distribution. (llvm#138593) [GlobalISel][AMDGPU] Fix handling of v2i128 type for AND, OR, XOR (llvm#138574) AMDGPU][True16][CodeGen] FP_Round f64 to f16 in true16 (llvm#128911) Reland [Clang] Deprecate `__is_trivially_relocatable` (llvm#139061) [HLSL][NFC] Stricter Overload Tests (clamp,max,min,pow) (llvm#138993) [MLIR] Fixing the memref linearization size computation for non-packed memref (llvm#138922) [TableGen][NFC] Use early exit to simplify large block in emitAction. (llvm#138220) ...
topperc
approved these changes
May 8, 2025
| def riscv_vmv_x_s : SDNode<"RISCVISD::VMV_X_S", | ||
| // VMV_X_S matches the semantics of vmv.x.s. The result is always XLenVT sign | ||
| // extended from the vector element size. | ||
| def riscv_vmv_x_s : RVSDNode<"VMV_X_S", | ||
| SDTypeProfile<1, 1, [SDTCisInt<0>, SDTCisVec<1>, |
| def riscv_read_vlenb : SDNode<"RISCVISD::READ_VLENB", | ||
|
|
||
| // Read VLENB CSR | ||
| def riscv_read_vlenb : RVSDNode<"READ_VLENB", | ||
| SDTypeProfile<1, 0, [SDTCisVT<0, XLenVT>]>>; |
| @@ -32,10 +32,11 @@ class RVInstRMoprr<bits<4> imm4, bits<3> imm3, bits<3> funct3, RISCVOpcode opcod | |||
| let Inst{25} = imm4{0}; | |||
| } | |||
|
|
|||
| def riscv_mopr : SDNode<"RISCVISD::MOPR", | |||
| // May-Be-Operations | |||
| def riscv_mopr : RVSDNode<"MOPR", | |||
| SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisSameAs<0, 1>, | |||
| SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisSameAs<0, 1>, | ||
| SDTCisSameAs<0, 2>]>>; | ||
| def riscv_moprr : SDNode<"RISCVISD::MOPRR", | ||
| def riscv_moprr : RVSDNode<"MOPRR", | ||
| SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<0, 1>, |
|
LLVM Buildbot has detected a new failure on builder Full details are available at: https://lab.llvm.org/buildbot/#/builders/23/builds/10143 Here is the relevant piece of the build log for the reference |
|
LLVM Buildbot has detected a new failure on builder Full details are available at: https://lab.llvm.org/buildbot/#/builders/64/builds/3486 Here is the relevant piece of the build log for the reference |
|
LLVM Buildbot has detected a new failure on builder Full details are available at: https://lab.llvm.org/buildbot/#/builders/146/builds/2886 Here is the relevant piece of the build log for the reference |
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This commit moves RISC-V to auto-generate its target-specific SDNode types. The biggest change is that SDNodes can now be validated against their expected type profiles, and that we don't need to edit several different files when declaring a new one.
This takes Sergei's work in #119709 and "finishes" it - by moving the final five RISCVISD opcodes into tablegen (including defining their types), and by ensuring the tablegen has expected closing scope comments.
Only one opcode is not currently verifying on the in-tree tests:
PROBED_ALLOCAso I have just ensured it skips verification for the moment (as in Sergei's patch).