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[AMDGPU][True16][CodeGen] clean up a few codegen test for true16 mode #138542

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Merged
merged 1 commit into from
May 5, 2025
Merged

[AMDGPU][True16][CodeGen] clean up a few codegen test for true16 mode #138542

merged 1 commit into from
May 5, 2025

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broxigarchen
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@broxigarchen broxigarchen commented May 5, 2025 •
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This is a NFC patch.

Clean up three test for true16 mode:

  1. remove strayed test line
  2. remove t16 test line from fake16 mir test
  3. update check-label to shrink test size

@broxigarchen broxigarchen marked this pull request as ready for review May 5, 2025 15:35
@broxigarchen broxigarchen requested review from Sisyph and kosarev May 5, 2025 15:35
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llvmbot commented May 5, 2025

@llvm/pr-subscribers-backend-amdgpu

Author: Brox Chen (broxigarchen)

Changes

This is a NFC patch.

Clean up three test for true16 mode:

  1. remove strayed test line
  2. remove t16 instructions from fake16 test file
  3. update check-label to shrink test size

Patch is 72.77 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/138542.diff

3 Files Affected:

  • (modified) llvm/test/CodeGen/AMDGPU/combine_andor_with_cmps.ll (+333-706)
  • (modified) llvm/test/CodeGen/AMDGPU/omod.ll (-38)
  • (modified) llvm/test/CodeGen/AMDGPU/vopc_dpp.mir (+22-47)
diff --git a/llvm/test/CodeGen/AMDGPU/combine_andor_with_cmps.ll b/llvm/test/CodeGen/AMDGPU/combine_andor_with_cmps.ll
index 9d679779fed0e..1d20218440f6a 100644
--- a/llvm/test/CodeGen/AMDGPU/combine_andor_with_cmps.ll
+++ b/llvm/test/CodeGen/AMDGPU/combine_andor_with_cmps.ll
@@ -1,8 +1,8 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
 ; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 -verify-machineinstrs -amdgpu-enable-delay-alu=0 < %s | FileCheck %s -check-prefixes=GCN,GFX11,GFX11-TRUE16
 ; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 -verify-machineinstrs -amdgpu-enable-delay-alu=0 < %s | FileCheck %s -check-prefixes=GCN,GFX11,GFX11-FAKE16
-; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 -verify-machineinstrs -amdgpu-enable-delay-alu=0 -enable-no-nans-fp-math < %s | FileCheck %s -check-prefixes=GCN,GCN-TRUE16,GFX11NONANS,GFX11NONANS-TRUE16
-; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 -verify-machineinstrs -amdgpu-enable-delay-alu=0 -enable-no-nans-fp-math < %s | FileCheck %s -check-prefixes=GCN,GCN-FAKE16,GFX11NONANS,GFX11NONANS-FAKE16
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 -verify-machineinstrs -amdgpu-enable-delay-alu=0 -enable-no-nans-fp-math < %s | FileCheck %s -check-prefixes=GCN,GFX11NONANS,GCN-TRUE16,GFX11NONANS-TRUE16
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 -verify-machineinstrs -amdgpu-enable-delay-alu=0 -enable-no-nans-fp-math < %s | FileCheck %s -check-prefixes=GCN,GFX11NONANS,GCN-FAKE16,GFX11NONANS-FAKE16
 
 ; The tests check the following optimization of DAGCombiner:
 ; CMP(A,C)||CMP(B,C) => CMP(MIN/MAX(A,B), C)
@@ -863,21 +863,13 @@ define i1 @test58(double %arg1, double %arg2, double %arg3) #0 {
 ; GFX11-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
 ; GFX11-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GCN-TRUE16-LABEL: test58:
-; GCN-TRUE16:       ; %bb.0:
-; GCN-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-TRUE16-NEXT:    v_min_f64 v[0:1], v[0:1], v[2:3]
-; GCN-TRUE16-NEXT:    v_cmp_gt_f64_e32 vcc_lo, v[0:1], v[4:5]
-; GCN-TRUE16-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; GCN-TRUE16-NEXT:    s_setpc_b64 s[30:31]
-;
-; GCN-FAKE16-LABEL: test58:
-; GCN-FAKE16:       ; %bb.0:
-; GCN-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-FAKE16-NEXT:    v_min_f64 v[0:1], v[0:1], v[2:3]
-; GCN-FAKE16-NEXT:    v_cmp_gt_f64_e32 vcc_lo, v[0:1], v[4:5]
-; GCN-FAKE16-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; GCN-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+; GFX11NONANS-LABEL: test58:
+; GFX11NONANS:       ; %bb.0:
+; GFX11NONANS-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11NONANS-NEXT:    v_min_f64 v[0:1], v[0:1], v[2:3]
+; GFX11NONANS-NEXT:    v_cmp_gt_f64_e32 vcc_lo, v[0:1], v[4:5]
+; GFX11NONANS-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GFX11NONANS-NEXT:    s_setpc_b64 s[30:31]
   %cmp1 = fcmp ugt double %arg1, %arg3
   %cmp2 = fcmp ugt double %arg2, %arg3
   %and1  = and i1 %cmp1, %cmp2
@@ -893,21 +885,13 @@ define i1 @test59(float %arg1, float %arg2, float %arg3) #0 {
 ; GFX11-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
 ; GFX11-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GCN-TRUE16-LABEL: test59:
-; GCN-TRUE16:       ; %bb.0:
-; GCN-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-TRUE16-NEXT:    v_min_f32_e32 v0, v0, v1
-; GCN-TRUE16-NEXT:    v_cmp_ge_f32_e32 vcc_lo, v0, v2
-; GCN-TRUE16-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; GCN-TRUE16-NEXT:    s_setpc_b64 s[30:31]
-;
-; GCN-FAKE16-LABEL: test59:
-; GCN-FAKE16:       ; %bb.0:
-; GCN-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-FAKE16-NEXT:    v_min_f32_e32 v0, v0, v1
-; GCN-FAKE16-NEXT:    v_cmp_ge_f32_e32 vcc_lo, v0, v2
-; GCN-FAKE16-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; GCN-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+; GFX11NONANS-LABEL: test59:
+; GFX11NONANS:       ; %bb.0:
+; GFX11NONANS-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11NONANS-NEXT:    v_min_f32_e32 v0, v0, v1
+; GFX11NONANS-NEXT:    v_cmp_ge_f32_e32 vcc_lo, v0, v2
+; GFX11NONANS-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GFX11NONANS-NEXT:    s_setpc_b64 s[30:31]
   %cmp1 = fcmp uge float %arg1, %arg3
   %cmp2 = fcmp uge float %arg2, %arg3
   %and1  = and i1 %cmp1, %cmp2
@@ -923,21 +907,13 @@ define i1 @test60(float %arg1, float %arg2, float %arg3) #0 {
 ; GFX11-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
 ; GFX11-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GCN-TRUE16-LABEL: test60:
-; GCN-TRUE16:       ; %bb.0:
-; GCN-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-TRUE16-NEXT:    v_max_f32_e32 v0, v0, v1
-; GCN-TRUE16-NEXT:    v_cmp_le_f32_e32 vcc_lo, v0, v2
-; GCN-TRUE16-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; GCN-TRUE16-NEXT:    s_setpc_b64 s[30:31]
-;
-; GCN-FAKE16-LABEL: test60:
-; GCN-FAKE16:       ; %bb.0:
-; GCN-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-FAKE16-NEXT:    v_max_f32_e32 v0, v0, v1
-; GCN-FAKE16-NEXT:    v_cmp_le_f32_e32 vcc_lo, v0, v2
-; GCN-FAKE16-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; GCN-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+; GFX11NONANS-LABEL: test60:
+; GFX11NONANS:       ; %bb.0:
+; GFX11NONANS-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11NONANS-NEXT:    v_max_f32_e32 v0, v0, v1
+; GFX11NONANS-NEXT:    v_cmp_le_f32_e32 vcc_lo, v0, v2
+; GFX11NONANS-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GFX11NONANS-NEXT:    s_setpc_b64 s[30:31]
   %cmp1 = fcmp ule float %arg1, %arg3
   %cmp2 = fcmp ule float %arg2, %arg3
   %and1  = and i1 %cmp1, %cmp2
@@ -953,21 +929,13 @@ define i1 @test61(double %arg1, double %arg2, double %arg3) #0 {
 ; GFX11-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
 ; GFX11-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GCN-TRUE16-LABEL: test61:
-; GCN-TRUE16:       ; %bb.0:
-; GCN-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-TRUE16-NEXT:    v_max_f64 v[0:1], v[0:1], v[2:3]
-; GCN-TRUE16-NEXT:    v_cmp_lt_f64_e32 vcc_lo, v[0:1], v[4:5]
-; GCN-TRUE16-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; GCN-TRUE16-NEXT:    s_setpc_b64 s[30:31]
-;
-; GCN-FAKE16-LABEL: test61:
-; GCN-FAKE16:       ; %bb.0:
-; GCN-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-FAKE16-NEXT:    v_max_f64 v[0:1], v[0:1], v[2:3]
-; GCN-FAKE16-NEXT:    v_cmp_lt_f64_e32 vcc_lo, v[0:1], v[4:5]
-; GCN-FAKE16-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; GCN-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+; GFX11NONANS-LABEL: test61:
+; GFX11NONANS:       ; %bb.0:
+; GFX11NONANS-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11NONANS-NEXT:    v_max_f64 v[0:1], v[0:1], v[2:3]
+; GFX11NONANS-NEXT:    v_cmp_lt_f64_e32 vcc_lo, v[0:1], v[4:5]
+; GFX11NONANS-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GFX11NONANS-NEXT:    s_setpc_b64 s[30:31]
   %cmp1 = fcmp ult double %arg1, %arg3
   %cmp2 = fcmp ult double %arg2, %arg3
   %and1 = and i1 %cmp1, %cmp2
@@ -1124,21 +1092,13 @@ define i1 @test70(float %arg1, float %arg2, float %arg3) {
 ; GFX11-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
 ; GFX11-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GCN-TRUE16-LABEL: test70:
-; GCN-TRUE16:       ; %bb.0:
-; GCN-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-TRUE16-NEXT:    v_min_f32_e32 v0, v0, v1
-; GCN-TRUE16-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v0, v2
-; GCN-TRUE16-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; GCN-TRUE16-NEXT:    s_setpc_b64 s[30:31]
-;
-; GCN-FAKE16-LABEL: test70:
-; GCN-FAKE16:       ; %bb.0:
-; GCN-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-FAKE16-NEXT:    v_min_f32_e32 v0, v0, v1
-; GCN-FAKE16-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v0, v2
-; GCN-FAKE16-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; GCN-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+; GFX11NONANS-LABEL: test70:
+; GFX11NONANS:       ; %bb.0:
+; GFX11NONANS-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11NONANS-NEXT:    v_min_f32_e32 v0, v0, v1
+; GFX11NONANS-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v0, v2
+; GFX11NONANS-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GFX11NONANS-NEXT:    s_setpc_b64 s[30:31]
   %var1 = call float @llvm.canonicalize.f32(float %arg1)
   %var2 = call float @llvm.canonicalize.f32(float %arg2)
   %cmp1 = fcmp olt float %var1, %arg3
@@ -1193,21 +1153,13 @@ define i1 @test73(float %arg1, float %arg2, float %arg3) {
 ; GFX11-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
 ; GFX11-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GCN-TRUE16-LABEL: test73:
-; GCN-TRUE16:       ; %bb.0:
-; GCN-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-TRUE16-NEXT:    v_max_f32_e32 v0, v0, v1
-; GCN-TRUE16-NEXT:    v_cmp_ge_f32_e32 vcc_lo, v0, v2
-; GCN-TRUE16-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; GCN-TRUE16-NEXT:    s_setpc_b64 s[30:31]
-;
-; GCN-FAKE16-LABEL: test73:
-; GCN-FAKE16:       ; %bb.0:
-; GCN-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-FAKE16-NEXT:    v_max_f32_e32 v0, v0, v1
-; GCN-FAKE16-NEXT:    v_cmp_ge_f32_e32 vcc_lo, v0, v2
-; GCN-FAKE16-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; GCN-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+; GFX11NONANS-LABEL: test73:
+; GFX11NONANS:       ; %bb.0:
+; GFX11NONANS-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11NONANS-NEXT:    v_max_f32_e32 v0, v0, v1
+; GFX11NONANS-NEXT:    v_cmp_ge_f32_e32 vcc_lo, v0, v2
+; GFX11NONANS-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GFX11NONANS-NEXT:    s_setpc_b64 s[30:31]
   %var1 = call float @llvm.canonicalize.f32(float %arg1)
   %var2 = call float @llvm.canonicalize.f32(float %arg2)
   %cmp1 = fcmp oge float %var1, %arg3
@@ -1227,25 +1179,15 @@ define i1 @test74(double %arg1, double %arg2, double %arg3) {
 ; GFX11-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
 ; GFX11-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GCN-TRUE16-LABEL: test74:
-; GCN-TRUE16:       ; %bb.0:
-; GCN-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-TRUE16-NEXT:    v_max_f64 v[0:1], v[0:1], v[0:1]
-; GCN-TRUE16-NEXT:    v_max_f64 v[2:3], v[2:3], v[2:3]
-; GCN-TRUE16-NEXT:    v_min_f64 v[0:1], v[0:1], v[2:3]
-; GCN-TRUE16-NEXT:    v_cmp_gt_f64_e32 vcc_lo, v[0:1], v[4:5]
-; GCN-TRUE16-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; GCN-TRUE16-NEXT:    s_setpc_b64 s[30:31]
-;
-; GCN-FAKE16-LABEL: test74:
-; GCN-FAKE16:       ; %bb.0:
-; GCN-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-FAKE16-NEXT:    v_max_f64 v[0:1], v[0:1], v[0:1]
-; GCN-FAKE16-NEXT:    v_max_f64 v[2:3], v[2:3], v[2:3]
-; GCN-FAKE16-NEXT:    v_min_f64 v[0:1], v[0:1], v[2:3]
-; GCN-FAKE16-NEXT:    v_cmp_gt_f64_e32 vcc_lo, v[0:1], v[4:5]
-; GCN-FAKE16-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; GCN-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+; GFX11NONANS-LABEL: test74:
+; GFX11NONANS:       ; %bb.0:
+; GFX11NONANS-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11NONANS-NEXT:    v_max_f64 v[0:1], v[0:1], v[0:1]
+; GFX11NONANS-NEXT:    v_max_f64 v[2:3], v[2:3], v[2:3]
+; GFX11NONANS-NEXT:    v_min_f64 v[0:1], v[0:1], v[2:3]
+; GFX11NONANS-NEXT:    v_cmp_gt_f64_e32 vcc_lo, v[0:1], v[4:5]
+; GFX11NONANS-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GFX11NONANS-NEXT:    s_setpc_b64 s[30:31]
   %var1 = call double @llvm.canonicalize.f64(double %arg1)
   %var2 = call double @llvm.canonicalize.f64(double %arg2)
   %cmp1 = fcmp ugt double %var1, %arg3
@@ -1264,21 +1206,13 @@ define i1 @test75(float %arg1, float %arg2, float %arg3) {
 ; GFX11-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
 ; GFX11-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GCN-TRUE16-LABEL: test75:
-; GCN-TRUE16:       ; %bb.0:
-; GCN-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-TRUE16-NEXT:    v_min_f32_e32 v0, v0, v1
-; GCN-TRUE16-NEXT:    v_cmp_ge_f32_e32 vcc_lo, v0, v2
-; GCN-TRUE16-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; GCN-TRUE16-NEXT:    s_setpc_b64 s[30:31]
-;
-; GCN-FAKE16-LABEL: test75:
-; GCN-FAKE16:       ; %bb.0:
-; GCN-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-FAKE16-NEXT:    v_min_f32_e32 v0, v0, v1
-; GCN-FAKE16-NEXT:    v_cmp_ge_f32_e32 vcc_lo, v0, v2
-; GCN-FAKE16-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; GCN-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+; GFX11NONANS-LABEL: test75:
+; GFX11NONANS:       ; %bb.0:
+; GFX11NONANS-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11NONANS-NEXT:    v_min_f32_e32 v0, v0, v1
+; GFX11NONANS-NEXT:    v_cmp_ge_f32_e32 vcc_lo, v0, v2
+; GFX11NONANS-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GFX11NONANS-NEXT:    s_setpc_b64 s[30:31]
   %var1 = call float @llvm.canonicalize.f32(float %arg1)
   %var2 = call float @llvm.canonicalize.f32(float %arg2)
   %cmp1 = fcmp uge float %var1, %arg3
@@ -1297,21 +1231,13 @@ define i1 @test76(float %arg1, float %arg2, float %arg3) {
 ; GFX11-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
 ; GFX11-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GCN-TRUE16-LABEL: test76:
-; GCN-TRUE16:       ; %bb.0:
-; GCN-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-TRUE16-NEXT:    v_max_f32_e32 v0, v0, v1
-; GCN-TRUE16-NEXT:    v_cmp_le_f32_e32 vcc_lo, v0, v2
-; GCN-TRUE16-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; GCN-TRUE16-NEXT:    s_setpc_b64 s[30:31]
-;
-; GCN-FAKE16-LABEL: test76:
-; GCN-FAKE16:       ; %bb.0:
-; GCN-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-FAKE16-NEXT:    v_max_f32_e32 v0, v0, v1
-; GCN-FAKE16-NEXT:    v_cmp_le_f32_e32 vcc_lo, v0, v2
-; GCN-FAKE16-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; GCN-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+; GFX11NONANS-LABEL: test76:
+; GFX11NONANS:       ; %bb.0:
+; GFX11NONANS-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11NONANS-NEXT:    v_max_f32_e32 v0, v0, v1
+; GFX11NONANS-NEXT:    v_cmp_le_f32_e32 vcc_lo, v0, v2
+; GFX11NONANS-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GFX11NONANS-NEXT:    s_setpc_b64 s[30:31]
   %var1 = call float @llvm.canonicalize.f32(float %arg1)
   %var2 = call float @llvm.canonicalize.f32(float %arg2)
   %cmp1 = fcmp ule float %var1, %arg3
@@ -1331,25 +1257,15 @@ define i1 @test77(double %arg1, double %arg2, double %arg3) {
 ; GFX11-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
 ; GFX11-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GCN-TRUE16-LABEL: test77:
-; GCN-TRUE16:       ; %bb.0:
-; GCN-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-TRUE16-NEXT:    v_max_f64 v[0:1], v[0:1], v[0:1]
-; GCN-TRUE16-NEXT:    v_max_f64 v[2:3], v[2:3], v[2:3]
-; GCN-TRUE16-NEXT:    v_max_f64 v[0:1], v[0:1], v[2:3]
-; GCN-TRUE16-NEXT:    v_cmp_lt_f64_e32 vcc_lo, v[0:1], v[4:5]
-; GCN-TRUE16-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; GCN-TRUE16-NEXT:    s_setpc_b64 s[30:31]
-;
-; GCN-FAKE16-LABEL: test77:
-; GCN-FAKE16:       ; %bb.0:
-; GCN-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-FAKE16-NEXT:    v_max_f64 v[0:1], v[0:1], v[0:1]
-; GCN-FAKE16-NEXT:    v_max_f64 v[2:3], v[2:3], v[2:3]
-; GCN-FAKE16-NEXT:    v_max_f64 v[0:1], v[0:1], v[2:3]
-; GCN-FAKE16-NEXT:    v_cmp_lt_f64_e32 vcc_lo, v[0:1], v[4:5]
-; GCN-FAKE16-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; GCN-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+; GFX11NONANS-LABEL: test77:
+; GFX11NONANS:       ; %bb.0:
+; GFX11NONANS-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11NONANS-NEXT:    v_max_f64 v[0:1], v[0:1], v[0:1]
+; GFX11NONANS-NEXT:    v_max_f64 v[2:3], v[2:3], v[2:3]
+; GFX11NONANS-NEXT:    v_max_f64 v[0:1], v[0:1], v[2:3]
+; GFX11NONANS-NEXT:    v_cmp_lt_f64_e32 vcc_lo, v[0:1], v[4:5]
+; GFX11NONANS-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GFX11NONANS-NEXT:    s_setpc_b64 s[30:31]
   %var1 = call double @llvm.canonicalize.f64(double %arg1)
   %var2 = call double @llvm.canonicalize.f64(double %arg2)
   %cmp1 = fcmp ult double %var1, %arg3
@@ -1381,21 +1297,13 @@ define i1 @test79(float %arg1, float %arg2, float %arg3) #0 {
 ; GFX11-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
 ; GFX11-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GCN-TRUE16-LABEL: test79:
-; GCN-TRUE16:       ; %bb.0:
-; GCN-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-TRUE16-NEXT:    v_max_f32_e32 v0, v0, v1
-; GCN-TRUE16-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v0, v2
-; GCN-TRUE16-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; GCN-TRUE16-NEXT:    s_setpc_b64 s[30:31]
-;
-; GCN-FAKE16-LABEL: test79:
-; GCN-FAKE16:       ; %bb.0:
-; GCN-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-FAKE16-NEXT:    v_max_f32_e32 v0, v0, v1
-; GCN-FAKE16-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v0, v2
-; GCN-FAKE16-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; GCN-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+; GFX11NONANS-LABEL: test79:
+; GFX11NONANS:       ; %bb.0:
+; GFX11NONANS-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11NONANS-NEXT:    v_max_f32_e32 v0, v0, v1
+; GFX11NONANS-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v0, v2
+; GFX11NONANS-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GFX11NONANS-NEXT:    s_setpc_b64 s[30:31]
   %cmp1 = fcmp ult float %arg1, %arg3
   %cmp2 = fcmp ugt float %arg3, %arg2
   %and1  = and i1 %cmp1, %cmp2
@@ -1465,21 +1373,13 @@ define i1 @test83(float %arg1, float %arg2, float %arg3) {
 ; GFX11-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
 ; GFX11-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GCN-TRUE16-LABEL: test83:
-; GCN-TRUE16:       ; %bb.0:
-; GCN-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-TRUE16-NEXT:    v_max_f32_e32 v0, v0, v1
-; GCN-TRUE16-NEXT:    v_cmp_le_f32_e32 vcc_lo, v0, v2
-; GCN-TRUE16-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; GCN-TRUE16-NEXT:    s_setpc_b64 s[30:31]
-;
-; GCN-FAKE16-LABEL: test83:
-; GCN-FAKE16:       ; %bb.0:
-; GCN-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-FAKE16-NEXT:    v_max_f32_e32 v0, v0, v1
-; GCN-FAKE16-NEXT:    v_cmp_le_f32_e32 vcc_lo, v0, v2
-; GCN-FAKE16-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; GCN-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+; GFX11NONANS-LABEL: test83:
+; GFX11NONANS:       ; %bb.0:
+; GFX11NONANS-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11NONANS-NEXT:    v_max_f32_e32 v0, v0, v1
+; GFX11NONANS-NEXT:    v_cmp_le_f32_e32 vcc_lo, v0, v2
+; GFX11NONANS-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GFX11NONANS-NEXT:    s_setpc_b64 s[30:31]
   %var1 = call float @llvm.canonicalize.f32(float %arg1)
   %var2 = call float @llvm.canonicalize.f32(float %arg2)
   %cmp1 = fcmp ule float %var1, %arg3
@@ -2283,21 +2183,13 @@ define i1 @test108(float %arg1, float %arg2, float %arg3, float %C) {
 ; GFX11-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
 ; GFX11-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GCN-TRUE16-LABEL: test108:
-; GCN-TRUE16:       ; %bb.0:
-; GCN-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-TRUE16-NEXT:    v_max3_f32 v0, v0, v1, v2
-; GCN-TRUE16-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v0, v3
-; GCN-TRUE16-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; GCN-TRUE16-NEXT:    s_setpc_b64 s[30:31]
-;
-; GCN-FAKE16-LABEL: test108:
-; GCN-FAKE16:       ; %bb.0:
-; GCN-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-FAKE16-NEXT:    v_max3_f32 v0, v0, v1, v2
-; GCN-FAKE16-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v0, v3
-; GCN-FAKE16-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; GCN-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+; GFX11NONANS-LABEL: test108:
+; GFX11NONANS:       ; %bb.0:
+; GFX11NONANS-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11NONANS-NEXT:    v_max3_f32 v0, v0, v1, v2
+; GFX11NONANS-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v0, v3
+; GFX11NONANS-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GFX11NONANS-NEXT:    s_setpc_b64 s[30:31]
   %cmp1 = fcmp ult float %arg1, %C
   %cmp2 = fcmp ult float %arg2, %C
   %cmp3 = fcmp ult float %arg3, %C
@@ -2319,25 +2211,15 @@ define i1 @test109(float %arg1, float %arg2, float %arg3, float %arg4, float %C)
 ; GFX11-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s0
 ; GFX11-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GCN-TRUE16-LABEL: test109:
-; GCN-TRUE16:       ; %bb.0:
-; GCN-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-TRUE16-NEXT:    v_dual_min_f32 v0, v0, v1 :: v_dual_max_f32 v1, v2, v3
-; GCN-TRUE16-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v0, v4
-; GCN-TRUE16-NEXT:    v_cmp_gt_f32_e64 s0, v1, v4
-; GCN-TRUE16-NEXT:    s_or_b32 s0, vcc_lo, s0
-; GCN-TRUE16-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s0
-; GCN-TRUE16-NEXT:    s_setpc_b64 s[30:31]
-;
-; GCN-FAKE16-LABEL: test109:
-; GCN-FAKE16:       ; %bb.0:
-; GCN-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-FAKE16-NEXT:    v_dual_min_f32 v0, v0, v1 :: v_dual_max_f32 v1, v2, v3
-; GCN-FAKE16-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v0, v4
-; G...
[truncated]

Sisyph
Sisyph approved these changes May 5, 2025
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LGTM

@broxigarchen broxigarchen merged commit 71ee336 into llvm:main May 5, 2025
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GeorgeARM pushed a commit to GeorgeARM/llvm-project that referenced this pull request May 7, 2025
@broxigarchen @GeorgeARM
[AMDGPU][True16][CodeGen] clean up a few codegen test for true16 mode (…
e26bd1d 
…llvm#138542)

This is a NFC patch.

Clean up three test for true16 mode:
1. remove strayed test line
2. remove t16 test line from fake16 mir test
3. update check-label to shrink test size
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@Sisyph Sisyph Sisyph approved these changes

@kosarev kosarev Awaiting requested review from kosarev

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@broxigarchen @llvmbot @Sisyph