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[Hexagon] Add missing patterns to select PFALSE and PTRUE #138712

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Merged
merged 1 commit into from
May 6, 2025
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[Hexagon] Add missing patterns to select PFALSE and PTRUE #138712

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5 changes: 5 additions & 0 deletions llvm/lib/Target/Hexagon/HexagonPatterns.td
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Original file line number Diff line number Diff line change
Expand Up @@ -109,7 +109,12 @@ def pfalse: PatFrag<(ops), (HexagonPFALSE)>;
def pnot: PatFrag<(ops node:$Pu), (xor node:$Pu, ptrue)>;

def: Pat<(v8i1 (HexagonPFALSE)), (C2_tfrrp (A2_tfrsi (i32 0)))>;
def: Pat<(v4i1 (HexagonPFALSE)), (C2_tfrrp (A2_tfrsi (i32 0)))>;
def: Pat<(v2i1 (HexagonPFALSE)), (C2_tfrrp (A2_tfrsi (i32 0)))>;

def: Pat<(v8i1 (HexagonPTRUE)), (C2_tfrrp (A2_tfrsi (i32 -1)))>;
def: Pat<(v4i1 (HexagonPTRUE)), (C2_tfrrp (A2_tfrsi (i32 -1)))>;
def: Pat<(v2i1 (HexagonPTRUE)), (C2_tfrrp (A2_tfrsi (i32 -1)))>;

def valign: PatFrag<(ops node:$Vt, node:$Vs, node:$Ru),
(HexagonVALIGN node:$Vt, node:$Vs, node:$Ru)>;
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29 changes: 29 additions & 0 deletions llvm/test/CodeGen/Hexagon/isel/pfalse-v4i1.ll
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@@ -0,0 +1,29 @@
; RUN: llc -march=hexagon -debug-only=isel 2>&1 < %s - | FileCheck %s

; CHECK: [[R0:%[0-9]+]]:intregs = A2_tfrsi 0
; CHECK-NEXT: predregs = C2_tfrrp killed [[R0]]:intregs

define fastcc i16 @test(ptr %0, { <4 x i32>, <4 x i1> } %1, <4 x i1> %2) {
Entry:
%3 = alloca [16 x i8], i32 0, align 16
%4 = alloca [16 x i8], i32 0, align 16
store <4 x i32> <i32 1, i32 2, i32 3, i32 4>, ptr %4, align 16
store <4 x i32> <i32 5, i32 6, i32 7, i32 8>, ptr %3, align 16
%5 = load <4 x i32>, ptr %4, align 16
%6 = load <4 x i32>, ptr %3, align 16
%7 = call { <4 x i32>, <4 x i1> } @llvm.sadd.with.overflow.v4i32(<4 x i32> %5, <4 x i32> %6)
%8 = call i1 @llvm.vector.reduce.or.v4i1(<4 x i1> %2)
br i1 %8, label %OverflowFail, label %OverflowOk

OverflowFail: ; preds = %Entry
store volatile i32 0, ptr null, align 4
unreachable

OverflowOk: ; preds = %Entry
%9 = extractvalue { <4 x i32>, <4 x i1> } %7, 0
store <4 x i32> %9, ptr %0, align 16
ret i16 0
}

declare { <4 x i32>, <4 x i1> } @llvm.sadd.with.overflow.v4i32(<4 x i32>, <4 x i32>) #0
declare i1 @llvm.vector.reduce.or.v4i1(<4 x i1>) #0