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[RISC] Use hasBEXTILike in useInversedSetcc and shouldFoldSelectWithSingleBitTest. #158366

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Merged
merged 1 commit into from
Sep 12, 2025
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[RISC] Use hasBEXTILike in useInversedSetcc and shouldFoldSelectWithSingleBitTest. #158366

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6 changes: 3 additions & 3 deletions llvm/lib/Target/RISCV/RISCVISelLowering.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -18950,7 +18950,7 @@ static SDValue useInversedSetcc(SDNode *N, SelectionDAG &DAG,

// Replace (setcc eq (and x, C)) with (setcc ne (and x, C))) to generate
// BEXTI, where C is power of 2.
if (Subtarget.hasStdExtZbs() && VT.isScalarInteger() &&
if (Subtarget.hasBEXTILike() && VT.isScalarInteger() &&
(Subtarget.hasCZEROLike() || Subtarget.hasVendorXTHeadCondMov())) {
SDValue LHS = Cond.getOperand(0);
SDValue RHS = Cond.getOperand(1);
Expand Down Expand Up @@ -24939,8 +24939,8 @@ RISCVTargetLowering::BuildSDIVPow2(SDNode *N, const APInt &Divisor,

bool RISCVTargetLowering::shouldFoldSelectWithSingleBitTest(
EVT VT, const APInt &AndMask) const {
if (Subtarget.hasCZEROLike())
return !Subtarget.hasStdExtZbs() && AndMask.ugt(1024);
if (Subtarget.hasCZEROLike() || Subtarget.hasVendorXTHeadCondMov())
return !Subtarget.hasBEXTILike() && AndMask.ugt(1024);
return TargetLowering::shouldFoldSelectWithSingleBitTest(VT, AndMask);
}

Expand Down
19 changes: 8 additions & 11 deletions llvm/test/CodeGen/RISCV/condops.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -3,7 +3,7 @@
; RUN: llc -mtriple=riscv64 -target-abi=lp64f -mattr=+f,+zbs < %s | FileCheck %s -check-prefix=RV64I
; RUN: llc -mtriple=riscv32 -target-abi=ilp32f -mattr=+f,+zbs,+xventanacondops < %s | FileCheck %s -check-prefix=RV32XVENTANACONDOPS
; RUN: llc -mtriple=riscv64 -target-abi=lp64f -mattr=+f,+zbs,+xventanacondops < %s | FileCheck %s -check-prefix=RV64XVENTANACONDOPS
; RUN: llc -mtriple=riscv64 -target-abi=lp64f -mattr=+f,+zbs,+xtheadcondmov < %s | FileCheck %s -check-prefix=RV64XTHEADCONDMOV
; RUN: llc -mtriple=riscv64 -target-abi=lp64f -mattr=+f,+xtheadbs,+xtheadcondmov < %s | FileCheck %s -check-prefix=RV64XTHEADCONDMOV
; RUN: llc -mtriple=riscv32 -target-abi=ilp32f -mattr=+f,+zbs,+zicond < %s | FileCheck %s -check-prefix=RV32ZICOND
; RUN: llc -mtriple=riscv64 -target-abi=lp64f -mattr=+f,+zbs,+zicond < %s | FileCheck %s -check-prefix=RV64ZICOND

Expand Down Expand Up @@ -126,7 +126,7 @@ define i64 @zero_singlebit1(i64 %rs1, i64 %rs2) {
;
; RV64XTHEADCONDMOV-LABEL: zero_singlebit1:
; RV64XTHEADCONDMOV: # %bb.0:
; RV64XTHEADCONDMOV-NEXT: bexti a1, a1, 12
; RV64XTHEADCONDMOV-NEXT: th.tst a1, a1, 12
; RV64XTHEADCONDMOV-NEXT: th.mvnez a0, zero, a1
; RV64XTHEADCONDMOV-NEXT: ret
;
Expand Down Expand Up @@ -179,9 +179,8 @@ define i64 @zero_singlebit2(i64 %rs1, i64 %rs2) {
;
; RV64XTHEADCONDMOV-LABEL: zero_singlebit2:
; RV64XTHEADCONDMOV: # %bb.0:
; RV64XTHEADCONDMOV-NEXT: slli a1, a1, 51
; RV64XTHEADCONDMOV-NEXT: srai a1, a1, 63
; RV64XTHEADCONDMOV-NEXT: and a0, a1, a0
; RV64XTHEADCONDMOV-NEXT: th.tst a1, a1, 12
; RV64XTHEADCONDMOV-NEXT: th.mveqz a0, zero, a1
; RV64XTHEADCONDMOV-NEXT: ret
;
; RV32ZICOND-LABEL: zero_singlebit2:
Expand Down Expand Up @@ -4297,9 +4296,8 @@ define i64 @single_bit(i64 %x) {
;
; RV64XTHEADCONDMOV-LABEL: single_bit:
; RV64XTHEADCONDMOV: # %bb.0: # %entry
; RV64XTHEADCONDMOV-NEXT: slli a1, a0, 53
; RV64XTHEADCONDMOV-NEXT: srai a1, a1, 63
; RV64XTHEADCONDMOV-NEXT: and a0, a1, a0
; RV64XTHEADCONDMOV-NEXT: andi a1, a0, 1024
; RV64XTHEADCONDMOV-NEXT: th.mveqz a0, zero, a1
; RV64XTHEADCONDMOV-NEXT: ret
;
; RV32ZICOND-LABEL: single_bit:
Expand Down Expand Up @@ -4353,9 +4351,8 @@ define i64 @single_bit2(i64 %x) {
;
; RV64XTHEADCONDMOV-LABEL: single_bit2:
; RV64XTHEADCONDMOV: # %bb.0: # %entry
; RV64XTHEADCONDMOV-NEXT: slli a1, a0, 52
; RV64XTHEADCONDMOV-NEXT: srai a1, a1, 63
; RV64XTHEADCONDMOV-NEXT: and a0, a1, a0
; RV64XTHEADCONDMOV-NEXT: th.tst a1, a0, 11
; RV64XTHEADCONDMOV-NEXT: th.mveqz a0, zero, a1
; RV64XTHEADCONDMOV-NEXT: ret
;
; RV32ZICOND-LABEL: single_bit2:
Expand Down
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