[LegalizeTypes][X86] Use getShiftAmountConstant in ExpandIntRes_SIGN_EXTEND. #158388
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…EXTEND. This ensures we don't need to fixup the shift amount later. Unfortunately, this enabled the (SRA (SHL X, ShlConst), SraConst) -> (SRA (sext_in_reg X), SraConst - ShlConst) combine in combineShiftRightArithmetic for some cases in is_fpclass-fp80.ll. So we need to also update checkSignTestSetCCCombine to look through sign_extend_inreg to prevent a regression.
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@llvm/pr-subscribers-llvm-selectiondag @llvm/pr-subscribers-backend-x86 Author: Craig Topper (topperc) ChangesThis ensures we don't need to fixup the shift amount later. Unfortunately, this enabled the So we need to also update checkSignTestSetCCCombine to look through sign_extend_inreg to prevent a regression. Full diff: https://github.com/llvm/llvm-project/pull/158388.diff 2 Files Affected:
diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
index 87570e6f44a6f..4671124a37f5d 100644
--- a/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
@@ -5088,9 +5088,8 @@ void DAGTypeLegalizer::ExpandIntRes_SIGN_EXTEND(SDNode *N,
Lo = DAG.getNode(ISD::SIGN_EXTEND, dl, NVT, N->getOperand(0));
// The high part is obtained by SRA'ing all but one of the bits of low part.
unsigned LoSize = NVT.getSizeInBits();
- Hi = DAG.getNode(
- ISD::SRA, dl, NVT, Lo,
- DAG.getConstant(LoSize - 1, dl, TLI.getPointerTy(DAG.getDataLayout())));
+ Hi = DAG.getNode(ISD::SRA, dl, NVT, Lo,
+ DAG.getShiftAmountConstant(LoSize - 1, NVT, dl));
} else {
// For example, extension of an i48 to an i64. The operand type necessarily
// promotes to the result type, so will end up being expanded too.
@@ -5123,8 +5122,8 @@ ExpandIntRes_SIGN_EXTEND_INREG(SDNode *N, SDValue &Lo, SDValue &Hi) {
// The high part gets the sign extension from the lo-part. This handles
// things like sextinreg V:i64 from i8.
Hi = DAG.getNode(ISD::SRA, dl, Hi.getValueType(), Lo,
- DAG.getConstant(Hi.getValueSizeInBits() - 1, dl,
- TLI.getPointerTy(DAG.getDataLayout())));
+ DAG.getShiftAmountConstant(Hi.getValueSizeInBits() - 1,
+ Hi.getValueType(), dl));
} else {
// For example, extension of an i48 to an i64. Leave the low part alone,
// sext_inreg the high part.
@@ -5929,14 +5928,13 @@ SDValue DAGTypeLegalizer::ExpandIntOp_STORE(StoreSDNode *N, unsigned OpNo) {
if (ExcessBits < NVT.getSizeInBits()) {
// Transfer high bits from the top of Lo to the bottom of Hi.
- Hi = DAG.getNode(ISD::SHL, dl, NVT, Hi,
- DAG.getConstant(NVT.getSizeInBits() - ExcessBits, dl,
- TLI.getPointerTy(DAG.getDataLayout())));
+ Hi = DAG.getNode(
+ ISD::SHL, dl, NVT, Hi,
+ DAG.getShiftAmountConstant(NVT.getSizeInBits() - ExcessBits, NVT, dl));
Hi = DAG.getNode(
ISD::OR, dl, NVT, Hi,
DAG.getNode(ISD::SRL, dl, NVT, Lo,
- DAG.getConstant(ExcessBits, dl,
- TLI.getPointerTy(DAG.getDataLayout()))));
+ DAG.getShiftAmountConstant(ExcessBits, NVT, dl)));
}
// Store both the high bits and maybe some of the low bits.
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index 3631016b0f5c7..eeb5eb8a262de 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -48396,13 +48396,17 @@ static SDValue checkSignTestSetCCCombine(SDValue Cmp, X86::CondCode &CC,
MVT SrcVT = Src.getSimpleValueType();
APInt BitMask = APInt::getSignMask(SrcVT.getScalarSizeInBits());
- // If Src came from a SHL (probably from an expanded SIGN_EXTEND_INREG), then
- // peek through and adjust the TEST bit.
+ // If Src came from a SIGN_EXTEND_INREG or SHL (probably from an expanded
+ // SIGN_EXTEND_INREG), then peek through and adjust the TEST bit.
if (Src.getOpcode() == ISD::SHL) {
if (std::optional<unsigned> ShiftAmt = DAG.getValidShiftAmount(Src)) {
Src = Src.getOperand(0);
BitMask.lshrInPlace(*ShiftAmt);
}
+ } else if (Src.getOpcode() == ISD::SIGN_EXTEND_INREG) {
+ EVT ExtVT = cast<VTSDNode>(Src.getOperand(1))->getVT();
+ Src = Src.getOperand(0);
+ BitMask.lshrInPlace(BitMask.getBitWidth() - ExtVT.getScalarSizeInBits());
}
SDValue Mask = DAG.getNode(ISD::AND, DL, SrcVT, Src,
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arsenm
approved these changes
Sep 13, 2025
topperc
commented
Sep 13, 2025
| Hi = DAG.getNode(ISD::SHL, dl, NVT, Hi, | ||
| DAG.getConstant(NVT.getSizeInBits() - ExcessBits, dl, | ||
| TLI.getPointerTy(DAG.getDataLayout()))); | ||
| Hi = DAG.getNode( |
There was a problem hiding this comment.
This one was meant for a different PR with others that didn't change tests.
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LLVM Buildbot has detected a new failure on builder Full details are available at: https://lab.llvm.org/buildbot/#/builders/129/builds/29398 Here is the relevant piece of the build log for the reference |
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This ensures we don't need to fixup the shift amount later.
Unfortunately, this enabled the
(SRA (SHL X, ShlConst), SraConst) -> (SRA (sext_in_reg X), SraConst - ShlConst) combine in combineShiftRightArithmetic for some cases in is_fpclass-fp80.ll.
So we need to also update checkSignTestSetCCCombine to look through sign_extend_inreg to prevent a regression.