[SelectionDAG] Use getShiftAmountConstant. #158395
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Many of the shifts in LegalizeIntegerTypes.cpp were using getPointerTy.
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@llvm/pr-subscribers-llvm-selectiondag Author: Craig Topper (topperc) ChangesMany of the shifts in LegalizeIntegerTypes.cpp were using getPointerTy. Full diff: https://github.com/llvm/llvm-project/pull/158395.diff 4 Files Affected:
diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
index bcfc2c5dc9f83..5fb7e63cfb605 100644
--- a/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
@@ -585,8 +585,7 @@ void SelectionDAGLegalize::LegalizeStoreOps(SDNode *Node) {
DAG.getMemBasePlusOffset(Ptr, TypeSize::getFixed(IncrementSize), dl);
Hi = DAG.getNode(
ISD::SRL, dl, Value.getValueType(), Value,
- DAG.getConstant(RoundWidth, dl,
- TLI.getShiftAmountTy(Value.getValueType(), DL)));
+ DAG.getShiftAmountConstant(RoundWidth, Value.getValueType(), dl));
Hi = DAG.getTruncStore(Chain, dl, Hi, Ptr,
ST->getPointerInfo().getWithOffset(IncrementSize),
ExtraVT, ST->getBaseAlign(), MMOFlags, AAInfo);
@@ -596,8 +595,7 @@ void SelectionDAGLegalize::LegalizeStoreOps(SDNode *Node) {
// Store the top RoundWidth bits.
Hi = DAG.getNode(
ISD::SRL, dl, Value.getValueType(), Value,
- DAG.getConstant(ExtraWidth, dl,
- TLI.getShiftAmountTy(Value.getValueType(), DL)));
+ DAG.getShiftAmountConstant(ExtraWidth, Value.getValueType(), dl));
Hi = DAG.getTruncStore(Chain, dl, Hi, Ptr, ST->getPointerInfo(), RoundVT,
ST->getBaseAlign(), MMOFlags, AAInfo);
@@ -816,8 +814,7 @@ void SelectionDAGLegalize::LegalizeLoadOps(SDNode *Node) {
// Move the top bits to the right place.
Hi = DAG.getNode(
ISD::SHL, dl, Hi.getValueType(), Hi,
- DAG.getConstant(RoundWidth, dl,
- TLI.getShiftAmountTy(Hi.getValueType(), DL)));
+ DAG.getShiftAmountConstant(RoundWidth, Hi.getValueType(), dl));
// Join the hi and lo parts.
Value = DAG.getNode(ISD::OR, dl, Node->getValueType(0), Lo, Hi);
@@ -845,8 +842,7 @@ void SelectionDAGLegalize::LegalizeLoadOps(SDNode *Node) {
// Move the top bits to the right place.
Hi = DAG.getNode(
ISD::SHL, dl, Hi.getValueType(), Hi,
- DAG.getConstant(ExtraWidth, dl,
- TLI.getShiftAmountTy(Hi.getValueType(), DL)));
+ DAG.getShiftAmountConstant(ExtraWidth, Hi.getValueType(), dl));
// Join the hi and lo parts.
Value = DAG.getNode(ISD::OR, dl, Node->getValueType(0), Lo, Hi);
@@ -2767,8 +2763,7 @@ SDValue SelectionDAGLegalize::ExpandLegalINT_TO_FP(SDNode *Node,
SDValue SignBitTest = DAG.getSetCC(
dl, SetCCVT, Op0, DAG.getConstant(0, dl, SrcVT), ISD::SETLT);
- EVT ShiftVT = TLI.getShiftAmountTy(SrcVT, DAG.getDataLayout());
- SDValue ShiftConst = DAG.getConstant(1, dl, ShiftVT);
+ SDValue ShiftConst = DAG.getShiftAmountConstant(1, SrcVT, dl);
SDValue Shr = DAG.getNode(ISD::SRL, dl, SrcVT, Op0, ShiftConst);
SDValue AndConst = DAG.getConstant(1, dl, SrcVT);
SDValue And = DAG.getNode(ISD::AND, dl, SrcVT, Op0, AndConst);
@@ -3350,10 +3345,8 @@ bool SelectionDAGLegalize::ExpandNode(SDNode *Node) {
} else {
Op = DAG.getAnyExtOrTrunc(Op, dl, MVT::i32);
}
- Op = DAG.getNode(
- ISD::SHL, dl, MVT::i32, Op,
- DAG.getConstant(16, dl,
- TLI.getShiftAmountTy(MVT::i32, DAG.getDataLayout())));
+ Op = DAG.getNode(ISD::SHL, dl, MVT::i32, Op,
+ DAG.getShiftAmountConstant(16, MVT::i32, dl));
Op = DAG.getNode(ISD::BITCAST, dl, MVT::f32, Op);
// Add fp_extend in case the output is bigger than f32.
if (Node->getValueType(0) != MVT::f32)
@@ -3370,10 +3363,9 @@ bool SelectionDAGLegalize::ExpandNode(SDNode *Node) {
if (!DAG.isKnownNeverSNaN(Op)) {
Op = DAG.getNode(ISD::FCANONICALIZE, dl, MVT::f32, Op, Node->getFlags());
}
- Op = DAG.getNode(
- ISD::SRL, dl, MVT::i32, DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op),
- DAG.getConstant(16, dl,
- TLI.getShiftAmountTy(MVT::i32, DAG.getDataLayout())));
+ Op = DAG.getNode(ISD::SRL, dl, MVT::i32,
+ DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op),
+ DAG.getShiftAmountConstant(16, MVT::i32, dl));
// The result of this node can be bf16 or an integer type in case bf16 is
// not supported on the target and was softened to i16 for storage.
if (Node->getValueType(0) == MVT::bf16) {
@@ -3431,13 +3423,11 @@ bool SelectionDAGLegalize::ExpandNode(SDNode *Node) {
// NOTE: we could fall back on load/store here too for targets without
// SRA. However, it is doubtful that any exist.
- EVT ShiftAmountTy = TLI.getShiftAmountTy(VT, DAG.getDataLayout());
unsigned BitsDiff = VT.getScalarSizeInBits() -
ExtraVT.getScalarSizeInBits();
- SDValue ShiftCst = DAG.getConstant(BitsDiff, dl, ShiftAmountTy);
- Tmp1 = DAG.getNode(ISD::SHL, dl, Node->getValueType(0),
- Node->getOperand(0), ShiftCst);
- Tmp1 = DAG.getNode(ISD::SRA, dl, Node->getValueType(0), Tmp1, ShiftCst);
+ SDValue ShiftCst = DAG.getShiftAmountConstant(BitsDiff, VT, dl);
+ Tmp1 = DAG.getNode(ISD::SHL, dl, VT, Node->getOperand(0), ShiftCst);
+ Tmp1 = DAG.getNode(ISD::SRA, dl, VT, Tmp1, ShiftCst);
Results.push_back(Tmp1);
break;
}
@@ -3666,11 +3656,9 @@ bool SelectionDAGLegalize::ExpandNode(SDNode *Node) {
EVT OpTy = Node->getOperand(0).getValueType();
if (Node->getConstantOperandVal(1)) {
// 1 -> Hi
- Tmp1 = DAG.getNode(ISD::SRL, dl, OpTy, Node->getOperand(0),
- DAG.getConstant(OpTy.getSizeInBits() / 2, dl,
- TLI.getShiftAmountTy(
- Node->getOperand(0).getValueType(),
- DAG.getDataLayout())));
+ Tmp1 = DAG.getNode(
+ ISD::SRL, dl, OpTy, Node->getOperand(0),
+ DAG.getShiftAmountConstant(OpTy.getSizeInBits() / 2, OpTy, dl));
Tmp1 = DAG.getNode(ISD::TRUNCATE, dl, Node->getValueType(0), Tmp1);
} else {
// 0 -> Lo
@@ -3950,9 +3938,8 @@ bool SelectionDAGLegalize::ExpandNode(SDNode *Node) {
for (unsigned i = 0; i < 2; ++i) {
SDValue Lo = DAG.getNode(ISD::ZERO_EXTEND, dl, VT, Halves[2 * i]);
SDValue Hi = DAG.getNode(ISD::ANY_EXTEND, dl, VT, Halves[2 * i + 1]);
- SDValue Shift = DAG.getConstant(
- HalfType.getScalarSizeInBits(), dl,
- TLI.getShiftAmountTy(HalfType, DAG.getDataLayout()));
+ SDValue Shift =
+ DAG.getShiftAmountConstant(HalfType.getScalarSizeInBits(), VT, dl);
Hi = DAG.getNode(ISD::SHL, dl, VT, Hi, Shift);
Results.push_back(DAG.getNode(ISD::OR, dl, VT, Lo, Hi));
}
@@ -3999,8 +3986,7 @@ bool SelectionDAGLegalize::ExpandNode(SDNode *Node) {
Lo = DAG.getNode(ISD::ZERO_EXTEND, dl, VT, Lo);
Hi = DAG.getNode(ISD::ANY_EXTEND, dl, VT, Hi);
SDValue Shift =
- DAG.getConstant(HalfType.getSizeInBits(), dl,
- TLI.getShiftAmountTy(HalfType, DAG.getDataLayout()));
+ DAG.getShiftAmountConstant(HalfType.getSizeInBits(), VT, dl);
Hi = DAG.getNode(ISD::SHL, dl, VT, Hi, Shift);
Results.push_back(DAG.getNode(ISD::OR, dl, VT, Lo, Hi));
}
@@ -4130,8 +4116,7 @@ bool SelectionDAGLegalize::ExpandNode(SDNode *Node) {
Tmp2 = DAG.getNode(ISD::ANY_EXTEND, dl, PairTy, Node->getOperand(1));
Tmp2 = DAG.getNode(
ISD::SHL, dl, PairTy, Tmp2,
- DAG.getConstant(PairTy.getSizeInBits() / 2, dl,
- TLI.getShiftAmountTy(PairTy, DAG.getDataLayout())));
+ DAG.getShiftAmountConstant(PairTy.getSizeInBits() / 2, PairTy, dl));
Results.push_back(DAG.getNode(ISD::OR, dl, PairTy, Tmp1, Tmp2));
break;
}
@@ -5368,10 +5353,8 @@ void SelectionDAGLegalize::PromoteNode(SDNode *Node) {
unsigned DiffBits = NVT.getSizeInBits() - OVT.getSizeInBits();
Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Node->getOperand(0));
Tmp1 = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1);
- Tmp1 = DAG.getNode(
- ISD::SRL, dl, NVT, Tmp1,
- DAG.getConstant(DiffBits, dl,
- TLI.getShiftAmountTy(NVT, DAG.getDataLayout())));
+ Tmp1 = DAG.getNode(ISD::SRL, dl, NVT, Tmp1,
+ DAG.getShiftAmountConstant(DiffBits, NVT, dl));
Results.push_back(DAG.getNode(ISD::TRUNCATE, dl, OVT, Tmp1));
break;
@@ -5483,11 +5466,9 @@ void SelectionDAGLegalize::PromoteNode(SDNode *Node) {
Tmp2 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(1));
Tmp1 = DAG.getNode(ISD::MUL, dl, NVT, Tmp1, Tmp2);
- auto &DL = DAG.getDataLayout();
unsigned OriginalSize = OVT.getScalarSizeInBits();
- Tmp2 = DAG.getNode(
- ISD::SRL, dl, NVT, Tmp1,
- DAG.getConstant(OriginalSize, dl, TLI.getScalarShiftAmountTy(DL, NVT)));
+ Tmp2 = DAG.getNode(ISD::SRL, dl, NVT, Tmp1,
+ DAG.getShiftAmountConstant(OriginalSize, NVT, dl));
Results.push_back(DAG.getNode(ISD::TRUNCATE, dl, OVT, Tmp1));
Results.push_back(DAG.getNode(ISD::TRUNCATE, dl, OVT, Tmp2));
break;
diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
index 87570e6f44a6f..595fd8d88e0ff 100644
--- a/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
@@ -1938,9 +1938,9 @@ SDValue DAGTypeLegalizer::PromoteIntRes_VAARG(SDNode *N) {
for (unsigned i = 1; i < NumRegs; ++i) {
SDValue Part = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Parts[i]);
// Shift it to the right position and "or" it in.
- Part = DAG.getNode(ISD::SHL, dl, NVT, Part,
- DAG.getConstant(i * RegVT.getSizeInBits(), dl,
- TLI.getPointerTy(DAG.getDataLayout())));
+ Part = DAG.getNode(
+ ISD::SHL, dl, NVT, Part,
+ DAG.getShiftAmountConstant(i * RegVT.getSizeInBits(), NVT, dl));
Res = DAG.getNode(ISD::OR, dl, NVT, Res, Part);
}
@@ -2293,9 +2293,9 @@ SDValue DAGTypeLegalizer::PromoteIntOp_BUILD_PAIR(SDNode *N) {
assert(Lo.getValueType() == N->getValueType(0) && "Operand over promoted?");
SDLoc dl(N);
- Hi = DAG.getNode(ISD::SHL, dl, N->getValueType(0), Hi,
- DAG.getConstant(OVT.getSizeInBits(), dl,
- TLI.getPointerTy(DAG.getDataLayout())));
+ Hi = DAG.getNode(
+ ISD::SHL, dl, N->getValueType(0), Hi,
+ DAG.getShiftAmountConstant(OVT.getSizeInBits(), N->getValueType(0), dl));
return DAG.getNode(ISD::OR, dl, N->getValueType(0), Lo, Hi);
}
@@ -3943,8 +3943,7 @@ void DAGTypeLegalizer::ExpandIntRes_AssertSext(SDNode *N,
Lo = DAG.getNode(ISD::AssertSext, dl, NVT, Lo, DAG.getValueType(EVT));
// The high part replicates the sign bit of Lo, make it explicit.
Hi = DAG.getNode(ISD::SRA, dl, NVT, Lo,
- DAG.getConstant(NVTBits - 1, dl,
- TLI.getPointerTy(DAG.getDataLayout())));
+ DAG.getShiftAmountConstant(NVTBits - 1, NVT, dl));
}
}
@@ -4329,8 +4328,7 @@ void DAGTypeLegalizer::ExpandIntRes_LOAD(LoadSDNode *N,
// lo part.
unsigned LoSize = Lo.getValueSizeInBits();
Hi = DAG.getNode(ISD::SRA, dl, NVT, Lo,
- DAG.getConstant(LoSize - 1, dl,
- TLI.getPointerTy(DAG.getDataLayout())));
+ DAG.getShiftAmountConstant(LoSize - 1, NVT, dl));
} else if (ExtType == ISD::ZEXTLOAD) {
// The high part is just a zero.
Hi = DAG.getConstant(0, dl, NVT);
@@ -4391,13 +4389,12 @@ void DAGTypeLegalizer::ExpandIntRes_LOAD(LoadSDNode *N,
Lo = DAG.getNode(
ISD::OR, dl, NVT, Lo,
DAG.getNode(ISD::SHL, dl, NVT, Hi,
- DAG.getConstant(ExcessBits, dl,
- TLI.getPointerTy(DAG.getDataLayout()))));
+ DAG.getShiftAmountConstant(ExcessBits, NVT, dl)));
// Move high bits to the right position in Hi.
Hi = DAG.getNode(ExtType == ISD::SEXTLOAD ? ISD::SRA : ISD::SRL, dl, NVT,
Hi,
- DAG.getConstant(NVT.getSizeInBits() - ExcessBits, dl,
- TLI.getPointerTy(DAG.getDataLayout())));
+ DAG.getShiftAmountConstant(
+ NVT.getSizeInBits() - ExcessBits, NVT, dl));
}
}
@@ -5166,12 +5163,12 @@ void DAGTypeLegalizer::ExpandIntRes_SREM(SDNode *N,
void DAGTypeLegalizer::ExpandIntRes_TRUNCATE(SDNode *N,
SDValue &Lo, SDValue &Hi) {
EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
+ SDValue InOp = N->getOperand(0);
+ EVT InVT = InOp.getValueType();
SDLoc dl(N);
- Lo = DAG.getNode(ISD::TRUNCATE, dl, NVT, N->getOperand(0));
- Hi = DAG.getNode(ISD::SRL, dl, N->getOperand(0).getValueType(),
- N->getOperand(0),
- DAG.getConstant(NVT.getSizeInBits(), dl,
- TLI.getPointerTy(DAG.getDataLayout())));
+ Lo = DAG.getNode(ISD::TRUNCATE, dl, NVT, InOp);
+ Hi = DAG.getNode(ISD::SRL, dl, InVT, InOp,
+ DAG.getShiftAmountConstant(NVT.getSizeInBits(), InVT, dl));
Hi = DAG.getNode(ISD::TRUNCATE, dl, NVT, Hi);
}
diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.cpp
index 83fade45d1892..a8f979c050b3f 100644
--- a/llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.cpp
@@ -1001,11 +1001,10 @@ SDValue DAGTypeLegalizer::JoinIntegers(SDValue Lo, SDValue Hi) {
EVT NVT = EVT::getIntegerVT(*DAG.getContext(),
LVT.getSizeInBits() + HVT.getSizeInBits());
- EVT ShiftAmtVT = TLI.getShiftAmountTy(NVT, DAG.getDataLayout());
Lo = DAG.getNode(ISD::ZERO_EXTEND, dlLo, NVT, Lo);
Hi = DAG.getNode(ISD::ANY_EXTEND, dlHi, NVT, Hi);
Hi = DAG.getNode(ISD::SHL, dlHi, NVT, Hi,
- DAG.getConstant(LVT.getSizeInBits(), dlHi, ShiftAmtVT));
+ DAG.getShiftAmountConstant(LVT.getSizeInBits(), NVT, dlHi));
return DAG.getNode(ISD::OR, dlHi, NVT, Lo, Hi);
}
diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
index 118fd8418f787..ff7cd665446cc 100644
--- a/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
@@ -5945,10 +5945,8 @@ SDValue DAGTypeLegalizer::WidenVecRes_BITCAST(SDNode *N) {
// interesting bits will end up at the wrong place.
if (DAG.getDataLayout().isBigEndian()) {
unsigned ShiftAmt = NInVT.getSizeInBits() - InVT.getSizeInBits();
- EVT ShiftAmtTy = TLI.getShiftAmountTy(NInVT, DAG.getDataLayout());
- assert(ShiftAmt < WidenVT.getSizeInBits() && "Too large shift amount!");
NInOp = DAG.getNode(ISD::SHL, dl, NInVT, NInOp,
- DAG.getConstant(ShiftAmt, dl, ShiftAmtTy));
+ DAG.getShiftAmountConstant(ShiftAmt, NInVT, dl));
}
return DAG.getNode(ISD::BITCAST, dl, WidenVT, NInOp);
}
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arsenm
approved these changes
Sep 13, 2025
arsenm
approved these changes
Sep 13, 2025
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Many of the shifts in LegalizeIntegerTypes.cpp were using getPointerTy.