<atomic>: Fix ARM64EC and CHPE codegen
#4222
Merged
Conversation
This file contains hidden or bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
CaseyCarter
approved these changes
Dec 1, 2023
Sign up for free
to join this conversation on GitHub.
Already have an account?
Sign in to comment
2 participants
Add this suggestion to a batch that can be applied as a single commit.
This suggestion is invalid because no changes were made to the code.
Suggestions cannot be applied while the pull request is closed.
Suggestions cannot be applied while viewing a subset of changes.
Only one suggestion per line can be applied in a batch.
Add this suggestion to a batch that can be applied as a single commit.
Applying suggestions on deleted lines is not supported.
You must change the existing code in this line in order to create a valid suggestion.
Outdated suggestions cannot be applied.
This suggestion has been applied or marked resolved.
Suggestions cannot be applied from pending reviews.
Suggestions cannot be applied on multi-line comments.
Suggestions cannot be applied while the pull request is queued to merge.
Suggestion cannot be applied right now. Please check back later.
This mirrors @mcfi's MSVC-PR-511288 as of Iteration 10, fixing VSO-1918426 which tracks the following issues reported internally by Geoffrey Antos:
std::atomic<T>::load()is still generating the original/slowldr+barrier instructions and not thelda[p]rinstructions intended by MSVC-PR-449792 /<atomic>: Improve ARM64 performance #3399.std::atomic<T>::load()appears to guarantee sequential consistency when requested for ARM64 CHPE builds.std::atomic_thread_fence()does not appear to guarantee the requested ordering for CHPE builds (other than forstd::memory_order_seq_cst).std::atomic<T>::exchange(),std::atomic<T>::compare_exchange_*()andstd::atomic<T>::fetch_*()appear to force sequentially consistent behavior.