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Name		Name	Last commit message	Last commit date
Latest commit History 414 Commits
doc		doc
software @ e2fbcd1		software @ e2fbcd1
src		src
testbench		testbench
vivado		vivado
.gitlab-ci.yml		.gitlab-ci.yml
.gitmodules		.gitmodules

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MIPS32 CPU implemented in SystemVerilog, with superscalar and branch prediction support

cpu mips systemverilog superscalar

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SystemVerilog 48.6%
Verilog 33.4%
Assembly 7.6%
C 6.3%
C++ 1.7%
Objective-C 1.0%
Other 1.4%