Proposed new feature or change:

Add CPU feature detection for SVE2. On wide CPU cores the Scalable Vector Extension has the potential to increase performance manyfold compared to NEON.

SVE2 is supported on most Armv9 cores, including the Arm Cortex-A510, Cortex-A710, Cortex-X2 and Neoverse N2 CPU designs. This means it's (to be) found in a huge amount of devices.

Arm documentation: https://developer.arm.com/Architectures/SVE

Introducing SVE2

This section introduces the Scalable Vector Extension version two (SVE2) of the Arm AArch64 architecture.

Following the development of the Neon architecture extension, which has a fixed 128-bit vector length for the instruction set, Arm designed the Scalable Vector Extension (SVE). SVE is a new Single Instruction Multiple Data (SIMD) instruction set that is used as an extension to AArch64, to allow for flexible vector length implementations. SVE improves the suitability of the architecture for High Performance Computing (HPC) applications, which require very large quantities of data processing.

SVE2 is a superset of SVE and Neon. SVE2 allows for more function domains in data-level parallelism. SVE2 inherits the concept, vector registers, and operation principles of SVE. SVE and SVE2 define 32 scalable vector registers. Silicon partners can choose a suitable vector length design implementation for hardware that varies between 128 bits and 2048 bits, at 128-bit increments. The advantage of SVE and SVE2 is that only one vector instruction set uses the scalable variables.

This enhancement might be similar to #20821 and #20552.