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@ixgbe ixgbe commented Nov 4, 2025

Test environment: Banana Pi BPI-F3 (SpacemiT K1 8-core RISC-V chip) gcc version 14.2.0
Test command: spin bench --compare HEAD~1 -t "bench_scalar"

(numpy_venv) root@yangwang:/home/yangwang/numpy# gcc -E -dM - </dev/null | grep __riscv_zfh
#define __riscv_zfhmin 1000000
#define __riscv_zfh 1000000

(numpy_venv) root@yangwang:/home/yangwang/numpy# cat /proc/cpuinfo | grep isa
isa : rv64imafdcv_zicbom_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zfhmin_zca_zcd_zba_zbb_zbc_zbs_zkt_zve32f_zve32x_zve64d_zve64f_zve64x_zvfh_zvfhmin_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt

(numpy_venv) root@yangwang:/home/yangwang/numpy# git log -2
commit 3876f75e01076ce5a78e4ea215b4cafa28e9b80b (HEAD -> main)
Author: Wang Yang [email protected]
Date: Tue Nov 4 13:26:57 2025 +0800
ENH: Enable native half-precision scalar conversion operations on RISC-V

commit 1e424da (origin/main, origin/HEAD)
Author: Rafael Laboissière [email protected]
Date: Sun Nov 2 18:46:22 2025 +0100

BUG: Avoid compilation error of wrapper file generated with SWIG >= 4.4 (#30128)

half_float_riscv_zfh

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