Summary

Closes the M-GPU-MOE-1.4 NaN root cause at layer 6 moe_ffn_out identified by the LIVE bisection in PR #1527/#1528 (M83/M84).

Post-fix verified on gx10 Blackwell GB10: ZERO NaN across all 48 layers; L6 moe_ffn_out cos goes from NanGpu → 0.999651 MATCH.

Five-Whys (validated by code inspection)

1. Why NaN at L6 moe_ffn_out? Garbage matvec output for gate or up at L6 overflows in silu(gate) * up product.
2. Why garbage matvec? Q6_K bytes interpreted as Q4_K bytes by GPU.
3. Why wrong byte interpretation? expert_swiglu_cuda calls q4k_matvec UNCONDITIONALLY for both gate AND up (no qtype check).
4. Why no qtype-aware dispatch on GPU? Helper authored after CPU sibling; the qtype detail wasn't ported.
5. Why does CPU sibling have it? Qwen3-Coder-30B-A3B-Instruct Q4_K_M is MIXED quant — expert tensors per layer can be either Q4_K (12) or Q6_K (14). CPU expert_swiglu_quantized dispatches via matvec_for_qtype with explicit comments calling out this exact issue.

Why L0–L5 MATCH

For layers 0-5 of canonical Qwen3-Coder GGUF, gate_exps + up_exps are Q4_K. The unconditional q4k_matvec was correct for those layers (cos > 0.9999 in pre-fix bisection).

Why L6 first NaN

Layer 6 has at least one tensor at Q6_K. GPU feeds Q6_K bytes into Q4_K kernel, which interprets the 256×6-bit super-block layout as 256×4-bit, producing scaled-by-16x garbage that overflows in silu(gate)*up within 1-2 layers.

Fix

• Extended expert_swiglu_cuda signature with 3 qtype parameters (gate_qtype, up_qtype, down_qtype)
• Added private matvec_qtype_cuda dispatch helper that mirrors CPU matvec_for_qtype: Q4_K → q4k_matvec, Q6_K → q6k_gemv, UnsupportedOperation otherwise
• Updated both moe_ffn_forward_layer_cuda + _with_router callers to pass layer.{gate,up,down}_exps.qtype

Verification

$ cargo test -p aprender-serve --features cuda --lib expert_swiglu_cuda
test result: ok. 4 passed; 0 failed; 0 ignored

$ ssh gx10 "cargo test -p aprender-serve --features cuda --release \
    --test qwen3_moe_gpu_per_stage_diff falsify_moe_sub_002_cpu_gpu_traced_per_stage_diff \
    -- --include-ignored --nocapture"
test result: ok. 1 passed; 0 failed; finished in 11.70s

M-MOE-SUB-3 bisection summary (post-fix):
  first NaN_GPU on moe_router  : None
  first NaN_GPU on moe_ffn_out : None    ← KEY: was Some(6); now None

L6 row pre/post comparison:

Discharges

What stays partial

About 7-8 layers (L7, L9, L12, L20, L23, L29, L46, etc.) sit at cos 0.94–0.987 — below the 0.99 threshold. Cause: floating-point accumulator order variance between CPU fused_q6k_parallel_matvec (Rust SIMD via rayon) and GPU q6k_gemv (CUDA warp-shuffle reduction). Both decode the same Q6_K bytes correctly; the f32 sum-of-products is just non-associative. This is M-GPU-MOE-3 territory (throughput-stage kernel refinement), not the step-c NaN bug.

Architecture portability

Fix is purely host-side dispatch logic — same on sm_89 (Ada RTX 4090) and sm_120 (Blackwell GB10). M83 finding ("bug is arch-portable, single fix discharges both") confirmed.

Drift-prevention tests

• expert_swiglu_cuda_signature_has_three_qtype_params (compilation gate)
• falsify_qw3_moe_gpu_qtype_aware_dispatch_rejects_unknown (asserts UnsupportedOperation on non-{Q4_K,Q6_K} qtype)
• All 4 lib tests pass

Test plan

• pv validate 0/0
• cargo test -p aprender-serve --features cuda --lib expert_swiglu_cuda 4/4 pass
• LIVE heavy harness on gx10 produces ZERO NaN; L6 cos 0.999651 MATCH
• Production hot path additive-purity preserved (extends signature; doesn't modify routing logic)
• Evidence captured: evidence/m-gpu-moe-1-4-postfix-gx10-2026-05-06/

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