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| 1 | +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) |
| 2 | +%YAML 1.2 |
| 3 | +--- |
| 4 | +$id: http://devicetree.org/schemas/i2c/opencores,i2c-ocores.yaml# |
| 5 | +$schema: http://devicetree.org/meta-schemas/core.yaml# |
| 6 | + |
| 7 | +title: OpenCores I2C controller |
| 8 | + |
| 9 | +maintainers: |
| 10 | + - Peter Korsgaard <[email protected]> |
| 11 | + |
| 12 | + |
| 13 | +allOf: |
| 14 | + - $ref: /schemas/i2c/i2c-controller.yaml# |
| 15 | + |
| 16 | +properties: |
| 17 | + compatible: |
| 18 | + oneOf: |
| 19 | + - items: |
| 20 | + - enum: |
| 21 | + - sifive,fu740-c000-i2c # Opencore based IP block FU740-C000 SoC |
| 22 | + - sifive,fu540-c000-i2c # Opencore based IP block FU540-C000 SoC |
| 23 | + - const: sifive,i2c0 |
| 24 | + - enum: |
| 25 | + - opencores,i2c-ocores |
| 26 | + - aeroflexgaisler,i2cmst |
| 27 | + |
| 28 | + reg: |
| 29 | + maxItems: 1 |
| 30 | + |
| 31 | + interrupts: |
| 32 | + maxItems: 1 |
| 33 | + |
| 34 | + clocks: |
| 35 | + maxItems: 1 |
| 36 | + |
| 37 | + clock-frequency: |
| 38 | + description: | |
| 39 | + clock-frequency property is meant to control the bus frequency for i2c bus |
| 40 | + drivers, but it was incorrectly used to specify i2c controller input clock |
| 41 | + frequency. So the following rules are set to fix this situation: |
| 42 | + - if clock-frequency is present and neither opencores,ip-clock-frequency nor |
| 43 | + clocks are, then clock-frequency specifies i2c controller clock frequency. |
| 44 | + This is to keep backwards compatibility with setups using old DTB. i2c bus |
| 45 | + frequency is fixed at 100 KHz. |
| 46 | + - if clocks is present it specifies i2c controller clock. clock-frequency |
| 47 | + property specifies i2c bus frequency. |
| 48 | + - if opencores,ip-clock-frequency is present it specifies i2c controller |
| 49 | + clock frequency. clock-frequency property specifies i2c bus frequency. |
| 50 | + default: 100000 |
| 51 | + |
| 52 | + reg-io-width: |
| 53 | + description: | |
| 54 | + io register width in bytes |
| 55 | + enum: [1, 2, 4] |
| 56 | + |
| 57 | + reg-shift: |
| 58 | + description: | |
| 59 | + device register offsets are shifted by this value |
| 60 | + default: 0 |
| 61 | + |
| 62 | + regstep: |
| 63 | + description: | |
| 64 | + deprecated, use reg-shift above |
| 65 | + deprecated: true |
| 66 | + |
| 67 | + opencores,ip-clock-frequency: |
| 68 | + $ref: /schemas/types.yaml#/definitions/uint32 |
| 69 | + description: | |
| 70 | + Frequency of the controller clock in Hz. Mutually exclusive with clocks. |
| 71 | + See the note above. |
| 72 | +
|
| 73 | +required: |
| 74 | + - compatible |
| 75 | + - reg |
| 76 | + - "#address-cells" |
| 77 | + - "#size-cells" |
| 78 | + |
| 79 | +oneOf: |
| 80 | + - required: |
| 81 | + - opencores,ip-clock-frequency |
| 82 | + - required: |
| 83 | + - clocks |
| 84 | + |
| 85 | +unevaluatedProperties: false |
| 86 | + |
| 87 | +examples: |
| 88 | + - | |
| 89 | + i2c@a0000000 { |
| 90 | + compatible = "opencores,i2c-ocores"; |
| 91 | + reg = <0xa0000000 0x8>; |
| 92 | + #address-cells = <1>; |
| 93 | + #size-cells = <0>; |
| 94 | + interrupts = <10>; |
| 95 | + opencores,ip-clock-frequency = <20000000>; |
| 96 | +
|
| 97 | + reg-shift = <0>; /* 8 bit registers */ |
| 98 | + reg-io-width = <1>; /* 8 bit read/write */ |
| 99 | + }; |
| 100 | +
|
| 101 | + i2c@b0000000 { |
| 102 | + compatible = "opencores,i2c-ocores"; |
| 103 | + reg = <0xa0000000 0x8>; |
| 104 | + #address-cells = <1>; |
| 105 | + #size-cells = <0>; |
| 106 | + interrupts = <10>; |
| 107 | + clocks = <&osc>; |
| 108 | + clock-frequency = <400000>; /* i2c bus frequency 400 KHz */ |
| 109 | +
|
| 110 | + reg-shift = <0>; /* 8 bit registers */ |
| 111 | + reg-io-width = <1>; /* 8 bit read/write */ |
| 112 | + }; |
| 113 | +... |
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