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tomasr8 committed May 25, 2023
commit 9499fb7b5e90474846139929b98be479e396891f
3 changes: 2 additions & 1 deletion Doc/library/dis.rst
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Expand Up @@ -406,7 +406,8 @@ details of bytecode instructions as :class:`Instruction` instances:

.. data:: jump_target

bytecode index of the jump target if this is a jump operation, otherwise ``None``
bytecode index of the jump target if this is a jump operation,
otherwise ``None``


.. data:: positions
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2 changes: 1 addition & 1 deletion Lib/dis.py
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Expand Up @@ -400,7 +400,7 @@ def _disassemble(self, lineno_width=3, mark_as_current=False, offset_width=4):
# If opname is longer than _OPNAME_WIDTH, but the total length together with
# oparg is less than _OPNAME_WIDTH + _OPARG_WIDTH (with at least one space in between),
# we allow opname to overflow into the space reserved for oparg.
# This results in fewer misaligned opargs in the disassembly output
# This results in fewer misaligned opargs in the disassembly output.
opname_excess = max(0, len(self.opname) - _OPNAME_WIDTH)
if opname_excess + len(arg) < _OPARG_WIDTH:
fields.append(arg.rjust(_OPARG_WIDTH - opname_excess))
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Original file line number Diff line number Diff line change
@@ -1,3 +1,3 @@
Add fields ``start_offset``, ``cache_offset``, ``end_offset``,
``baseopname``, ``baseopcode``, ``jump_target`` and ``oparg`` to
``dis.Instruction``.
:class:`dis.Instruction`.