Add MIPS asm! support

This patch also: * Add soft-float supports: only f32 * zero-extend i8/i16 to i32 because MIPS only supports register-length arithmetic. * Update table in asm! chapter in unstable book.
rust-lang · jonas-schievink · Sep 8, 2020 · Sep 21, 2020 · Sep 23, 2020 · Sep 24, 2020
commit ecf389547cf4ef5d8b7b18de5264426617e824d3
diff --git a/compiler/rustc_codegen_llvm/src/asm.rs b/compiler/rustc_codegen_llvm/src/asm.rs
@@ -259,6 +259,7 @@ impl AsmBuilderMethods<'tcx> for Builder<'a, 'll, 'tcx> {
                 InlineAsmArch::RiscV32 | InlineAsmArch::RiscV64 => {}
                 InlineAsmArch::Nvptx64 => {}
                 InlineAsmArch::Hexagon => {}
+                InlineAsmArch::Mips => {}
             }
         }
         if !options.contains(InlineAsmOptions::NOMEM) {
@@ -505,6 +506,8 @@ fn reg_to_llvm(reg: InlineAsmRegOrRegClass, layout: Option<&TyAndLayout<'tcx>>)
             InlineAsmRegClass::Arm(ArmInlineAsmRegClass::dreg)
             | InlineAsmRegClass::Arm(ArmInlineAsmRegClass::qreg) => "w",
             InlineAsmRegClass::Hexagon(HexagonInlineAsmRegClass::reg) => "r",
+            InlineAsmRegClass::Mips(MipsInlineAsmRegClass::reg) => "r",
+            InlineAsmRegClass::Mips(MipsInlineAsmRegClass::freg) => "f",
             InlineAsmRegClass::Nvptx(NvptxInlineAsmRegClass::reg16) => "h",
             InlineAsmRegClass::Nvptx(NvptxInlineAsmRegClass::reg32) => "r",
             InlineAsmRegClass::Nvptx(NvptxInlineAsmRegClass::reg64) => "l",
@@ -551,6 +554,7 @@ fn modifier_to_llvm(
             }
         }
         InlineAsmRegClass::Hexagon(_) => None,
+        InlineAsmRegClass::Mips(_) => None,
         InlineAsmRegClass::Nvptx(_) => None,
         InlineAsmRegClass::RiscV(RiscVInlineAsmRegClass::reg)
         | InlineAsmRegClass::RiscV(RiscVInlineAsmRegClass::freg) => None,
@@ -603,6 +607,8 @@ fn dummy_output_type(cx: &CodegenCx<'ll, 'tcx>, reg: InlineAsmRegClass) -> &'ll
             cx.type_vector(cx.type_i64(), 2)
         }
         InlineAsmRegClass::Hexagon(HexagonInlineAsmRegClass::reg) => cx.type_i32(),
+        InlineAsmRegClass::Mips(MipsInlineAsmRegClass::reg) => cx.type_i32(),
+        InlineAsmRegClass::Mips(MipsInlineAsmRegClass::freg) => cx.type_f32(),
         InlineAsmRegClass::Nvptx(NvptxInlineAsmRegClass::reg16) => cx.type_i16(),
         InlineAsmRegClass::Nvptx(NvptxInlineAsmRegClass::reg32) => cx.type_i32(),
         InlineAsmRegClass::Nvptx(NvptxInlineAsmRegClass::reg64) => cx.type_i64(),
@@ -700,6 +706,12 @@ fn llvm_fixup_input(
                 value
             }
         }
+        (InlineAsmRegClass::Mips(MipsInlineAsmRegClass::reg), Abi::Scalar(s)) => match s.value {
+            // MIPS only supports register-length arithmetics.
+            Primitive::Int(Integer::I8 | Integer::I16, _) => bx.zext(value, bx.cx.type_i32()),
+            Primitive::F32 => bx.bitcast(value, bx.cx.type_i32()),
+            _ => value,
+        },
         _ => value,
     }
 }
@@ -768,6 +780,13 @@ fn llvm_fixup_output(
                 value
             }
         }
+        (InlineAsmRegClass::Mips(MipsInlineAsmRegClass::reg), Abi::Scalar(s)) => match s.value {
+            // MIPS only supports register-length arithmetics.
+            Primitive::Int(Integer::I8, _) => bx.trunc(value, bx.cx.type_i8()),
+            Primitive::Int(Integer::I16, _) => bx.trunc(value, bx.cx.type_i16()),
+            Primitive::F32 => bx.bitcast(value, bx.cx.type_f32()),
+            _ => value,
+        },
         _ => value,
     }
 }
@@ -831,6 +850,12 @@ fn llvm_fixup_output_type(
                 layout.llvm_type(cx)
             }
         }
+        (InlineAsmRegClass::Mips(MipsInlineAsmRegClass::reg), Abi::Scalar(s)) => match s.value {
+            // MIPS only supports register-length arithmetics.
+            Primitive::Int(Integer::I8 | Integer::I16, _) => cx.type_i32(),
+            Primitive::F32 => cx.type_i32(),
+            _ => layout.llvm_type(cx),
+        },
         _ => layout.llvm_type(cx),
     }
 }
diff --git a/compiler/rustc_target/src/asm/mips.rs b/compiler/rustc_target/src/asm/mips.rs
@@ -0,0 +1,132 @@
+use super::{InlineAsmArch, InlineAsmType};
+use rustc_macros::HashStable_Generic;
+use std::fmt;
+
+def_reg_class! {
+    Mips MipsInlineAsmRegClass {
+        reg,
+        freg,
+    }
+}
+
+impl MipsInlineAsmRegClass {
+    pub fn valid_modifiers(self, _arch: super::InlineAsmArch) -> &'static [char] {
+        &[]
+    }
+
+    pub fn suggest_class(self, _arch: InlineAsmArch, _ty: InlineAsmType) -> Option<Self> {
+        None
+    }
+
+    pub fn suggest_modifier(
+        self,
+        _arch: InlineAsmArch,
+        _ty: InlineAsmType,
+    ) -> Option<(char, &'static str)> {
+        None
+    }
+
+    pub fn default_modifier(self, _arch: InlineAsmArch) -> Option<(char, &'static str)> {
+        None
+    }
+
+    pub fn supported_types(
+        self,
+        _arch: InlineAsmArch,
+    ) -> &'static [(InlineAsmType, Option<&'static str>)] {
+        match self {
+            Self::reg => types! { _: I8, I16, I32, F32; },
+            Self::freg => types! { _: F32; },
+        }
+    }
+}
+
+// The reserved registers are somewhat taken from <https://git.io/JUR1k#L150>.
+def_regs! {
+    Mips MipsInlineAsmReg MipsInlineAsmRegClass {
+        v0: reg = ["$2", "$v0"],
+        v1: reg = ["$3", "$v1"],
+        a0: reg = ["$4", "$a0"],
+        a1: reg = ["$5", "$a1"],
+        a2: reg = ["$6", "$a2"],
+        a3: reg = ["$7", "$a3"],
+        // FIXME: Reserve $t0, $t1 if in mips16 mode.
+        t0: reg = ["$8", "$t0"],
+        t1: reg = ["$9", "$t1"],
+        t2: reg = ["$10", "$t2"],
+        t3: reg = ["$11", "$t3"],
+        t4: reg = ["$12", "$t4"],
+        t5: reg = ["$13", "$t5"],
+        t6: reg = ["$14", "$t6"],
+        t7: reg = ["$15", "$t7"],
+        s0: reg = ["$16", "$s0"],
+        s1: reg = ["$17", "$s1"],
+        s2: reg = ["$18", "$s2"],
+        s3: reg = ["$19", "$s3"],
+        s4: reg = ["$20", "$s4"],
+        s5: reg = ["$21", "$s5"],
+        s6: reg = ["$22", "$s6"],
+        s7: reg = ["$23", "$s7"],
+        t8: reg = ["$24", "$t8"],
+        t9: reg = ["$25", "$t9"],
+        f0: freg = ["$f0"],
+        f1: freg = ["$f1"],
+        f2: freg = ["$f2"],
+        f3: freg = ["$f3"],
+        f4: freg = ["$f4"],
+        f5: freg = ["$f5"],
+        f6: freg = ["$f6"],
+        f7: freg = ["$f7"],
+        f8: freg = ["$f8"],
+        f9: freg = ["$f9"],
+        f10: freg = ["$f10"],
+        f11: freg = ["$f11"],
+        f12: freg = ["$f12"],
+        f13: freg = ["$f13"],
+        f14: freg = ["$f14"],
+        f15: freg = ["$f15"],
+        f16: freg = ["$f16"],
+        f17: freg = ["$f17"],
+        f18: freg = ["$f18"],
+        f19: freg = ["$f19"],
+        f20: freg = ["$f20"],
+        f21: freg = ["$f21"],
+        f22: freg = ["$f22"],
+        f23: freg = ["$f23"],
+        f24: freg = ["$f24"],
+        f25: freg = ["$f25"],
+        f26: freg = ["$f26"],
+        f27: freg = ["$f27"],
+        f28: freg = ["$f28"],
+        f29: freg = ["$f29"],
+        f30: freg = ["$f30"],
+        f31: freg = ["$f31"],
+        #error = ["$0", "$zero"] =>
+            "constant zero cannot be used as an operand for inline asm",
+        #error = ["$1", "$at"] =>
+            "reserved for assembler (Assembler Temp)",
+        #error = ["$26", "$k0"] =>
+            "OS-reserved register cannot be used as an operand for inline asm",
+        #error = ["$27", "$k1"] =>
+            "OS-reserved register cannot be used as an operand for inline asm",
+        #error = ["$28", "$gp"] =>
+            "the global pointer cannot be used as an operand for inline asm",
+        #error = ["$29", "$sp"] =>
+            "the stack pointer cannot be used as an operand for inline asm",
+        #error = ["$30", "$s8", "$fp"] =>
+            "the frame pointer cannot be used as an operand for inline asm",
+        #error = ["$31", "$ra"] =>
+            "the return address register cannot be used as an operand for inline asm",
+    }
+}
+
+impl MipsInlineAsmReg {
+    pub fn emit(
+        self,
+        out: &mut dyn fmt::Write,
+        _arch: InlineAsmArch,
+        _modifier: Option<char>,
+    ) -> fmt::Result {
+        out.write_str(self.name())
+    }
+}
diff --git a/compiler/rustc_target/src/asm/mod.rs b/compiler/rustc_target/src/asm/mod.rs
@@ -152,13 +152,15 @@ macro_rules! types {
 mod aarch64;
 mod arm;
 mod hexagon;
+mod mips;
 mod nvptx;
 mod riscv;
 mod x86;
 
 pub use aarch64::{AArch64InlineAsmReg, AArch64InlineAsmRegClass};
 pub use arm::{ArmInlineAsmReg, ArmInlineAsmRegClass};
 pub use hexagon::{HexagonInlineAsmReg, HexagonInlineAsmRegClass};
+pub use mips::{MipsInlineAsmReg, MipsInlineAsmRegClass};
 pub use nvptx::{NvptxInlineAsmReg, NvptxInlineAsmRegClass};
 pub use riscv::{RiscVInlineAsmReg, RiscVInlineAsmRegClass};
 pub use x86::{X86InlineAsmReg, X86InlineAsmRegClass};
@@ -173,6 +175,7 @@ pub enum InlineAsmArch {
     RiscV64,
     Nvptx64,
     Hexagon,
+    Mips,
 }
 
 impl FromStr for InlineAsmArch {
@@ -188,6 +191,7 @@ impl FromStr for InlineAsmArch {
             "riscv64" => Ok(Self::RiscV64),
             "nvptx64" => Ok(Self::Nvptx64),
             "hexagon" => Ok(Self::Hexagon),
+            "mips" => Ok(Self::Mips),
             _ => Err(()),
         }
     }
@@ -201,6 +205,7 @@ pub enum InlineAsmReg {
     RiscV(RiscVInlineAsmReg),
     Nvptx(NvptxInlineAsmReg),
     Hexagon(HexagonInlineAsmReg),
+    Mips(MipsInlineAsmReg),
 }
 
 impl InlineAsmReg {
@@ -211,6 +216,7 @@ impl InlineAsmReg {
             Self::AArch64(r) => r.name(),
             Self::RiscV(r) => r.name(),
             Self::Hexagon(r) => r.name(),
+            Self::Mips(r) => r.name(),
         }
     }
 
@@ -221,6 +227,7 @@ impl InlineAsmReg {
             Self::AArch64(r) => InlineAsmRegClass::AArch64(r.reg_class()),
             Self::RiscV(r) => InlineAsmRegClass::RiscV(r.reg_class()),
             Self::Hexagon(r) => InlineAsmRegClass::Hexagon(r.reg_class()),
+            Self::Mips(r) => InlineAsmRegClass::Mips(r.reg_class()),
         }
     }
 
@@ -252,6 +259,9 @@ impl InlineAsmReg {
             InlineAsmArch::Hexagon => {
                 Self::Hexagon(HexagonInlineAsmReg::parse(arch, has_feature, target, &name)?)
             }
+            InlineAsmArch::Mips => {
+                Self::Mips(MipsInlineAsmReg::parse(arch, has_feature, target, &name)?)
+            }
         })
     }
 
@@ -269,6 +279,7 @@ impl InlineAsmReg {
             Self::AArch64(r) => r.emit(out, arch, modifier),
             Self::RiscV(r) => r.emit(out, arch, modifier),
             Self::Hexagon(r) => r.emit(out, arch, modifier),
+            Self::Mips(r) => r.emit(out, arch, modifier),
         }
     }
 
@@ -279,6 +290,7 @@ impl InlineAsmReg {
             Self::AArch64(_) => cb(self),
             Self::RiscV(_) => cb(self),
             Self::Hexagon(r) => r.overlapping_regs(|r| cb(Self::Hexagon(r))),
+            Self::Mips(_) => cb(self),
         }
     }
 }
@@ -291,6 +303,7 @@ pub enum InlineAsmRegClass {
     RiscV(RiscVInlineAsmRegClass),
     Nvptx(NvptxInlineAsmRegClass),
     Hexagon(HexagonInlineAsmRegClass),
+    Mips(MipsInlineAsmRegClass),
 }
 
 impl InlineAsmRegClass {
@@ -302,6 +315,7 @@ impl InlineAsmRegClass {
             Self::RiscV(r) => r.name(),
             Self::Nvptx(r) => r.name(),
             Self::Hexagon(r) => r.name(),
+            Self::Mips(r) => r.name(),
         }
     }
 
@@ -316,6 +330,7 @@ impl InlineAsmRegClass {
             Self::RiscV(r) => r.suggest_class(arch, ty).map(InlineAsmRegClass::RiscV),
             Self::Nvptx(r) => r.suggest_class(arch, ty).map(InlineAsmRegClass::Nvptx),
             Self::Hexagon(r) => r.suggest_class(arch, ty).map(InlineAsmRegClass::Hexagon),
+            Self::Mips(r) => r.suggest_class(arch, ty).map(InlineAsmRegClass::Mips),
         }
     }
 
@@ -337,6 +352,7 @@ impl InlineAsmRegClass {
             Self::RiscV(r) => r.suggest_modifier(arch, ty),
             Self::Nvptx(r) => r.suggest_modifier(arch, ty),
             Self::Hexagon(r) => r.suggest_modifier(arch, ty),
+            Self::Mips(r) => r.suggest_modifier(arch, ty),
         }
     }
 
@@ -354,6 +370,7 @@ impl InlineAsmRegClass {
             Self::RiscV(r) => r.default_modifier(arch),
             Self::Nvptx(r) => r.default_modifier(arch),
             Self::Hexagon(r) => r.default_modifier(arch),
+            Self::Mips(r) => r.default_modifier(arch),
         }
     }
 
@@ -370,6 +387,7 @@ impl InlineAsmRegClass {
             Self::RiscV(r) => r.supported_types(arch),
             Self::Nvptx(r) => r.supported_types(arch),
             Self::Hexagon(r) => r.supported_types(arch),
+            Self::Mips(r) => r.supported_types(arch),
         }
     }
 
@@ -391,6 +409,7 @@ impl InlineAsmRegClass {
                 InlineAsmArch::Hexagon => {
                     Self::Hexagon(HexagonInlineAsmRegClass::parse(arch, name)?)
                 }
+                InlineAsmArch::Mips => Self::Mips(MipsInlineAsmRegClass::parse(arch, name)?),
             })
         })
     }
@@ -405,6 +424,7 @@ impl InlineAsmRegClass {
             Self::RiscV(r) => r.valid_modifiers(arch),
             Self::Nvptx(r) => r.valid_modifiers(arch),
             Self::Hexagon(r) => r.valid_modifiers(arch),
+            Self::Mips(r) => r.valid_modifiers(arch),
         }
     }
 }
@@ -545,5 +565,10 @@ pub fn allocatable_registers(
             hexagon::fill_reg_map(arch, has_feature, target, &mut map);
             map
         }
+        InlineAsmArch::Mips => {
+            let mut map = mips::regclass_map();
+            mips::fill_reg_map(arch, has_feature, target, &mut map);
+            map
+        }
     }
 }