Enable the optimizer with WebAssembly. #4993
Opt/Wasm: Add a number of Wasm-specific intrinsics and transients.
The motivation is mainly to get intrinsics for the bit-conversions between integers and floating point numbers, as well as for `numberLeadingZeros`. These are building blocks for many other low-level operations, and their JS-builtin-based implementation is really bad on Wasm for those use cases. Once we have the infrastructure for those as transients in the Wasm backend, we also take the opportunity to add a series of other methods that have a direct Wasm opcode equivalent.
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| Original file line number | Diff line number | Diff line change |
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| /* | ||
| * Scala.js (https://www.scala-js.org/) | ||
| * | ||
| * Copyright EPFL. | ||
| * | ||
| * Licensed under Apache License 2.0 | ||
| * (https://www.apache.org/licenses/LICENSE-2.0). | ||
| * | ||
| * See the NOTICE file distributed with this work for | ||
| * additional information regarding copyright ownership. | ||
| */ | ||
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| package org.scalajs.linker.backend.wasmemitter | ||
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| import scala.annotation.switch | ||
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| import org.scalajs.ir.Position | ||
| import org.scalajs.ir.Printers._ | ||
| import org.scalajs.ir.Transformers._ | ||
| import org.scalajs.ir.Traversers._ | ||
| import org.scalajs.ir.Trees._ | ||
| import org.scalajs.ir.Types._ | ||
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| import org.scalajs.linker.backend.webassembly.{Instructions => wa} | ||
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| /** Transients generated by the optimizer that only makes sense in Wasm. */ | ||
| object WasmTransients { | ||
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| /** Wasm unary op. | ||
| * | ||
| * Wasm features a number of dedicated opcodes for operations that are not | ||
| * in the IR, but only implemented in user space. We can see `WasmUnaryOp` | ||
| * as an extension of `ir.Trees.UnaryOp` that covers those. | ||
| * | ||
| * Wasm unary ops always preserve pureness. | ||
| */ | ||
| final case class WasmUnaryOp(op: WasmUnaryOp.Code, lhs: Tree) | ||
| extends Transient.Value { | ||
| import WasmUnaryOp._ | ||
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| val tpe: Type = resultTypeOf(op) | ||
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| def traverse(traverser: Traverser): Unit = | ||
| traverser.traverse(lhs) | ||
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| def transform(transformer: Transformer, isStat: Boolean)( | ||
| implicit pos: Position): Tree = { | ||
| Transient(WasmUnaryOp(op, transformer.transformExpr(lhs))) | ||
| } | ||
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| def wasmInstr: wa.SimpleInstr = (op: @switch) match { | ||
| case I32Clz => wa.I32Clz | ||
| case I32Ctz => wa.I32Ctz | ||
| case I32Popcnt => wa.I32Popcnt | ||
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| case I64Clz => wa.I64Clz | ||
| case I64Ctz => wa.I64Ctz | ||
| case I64Popcnt => wa.I64Popcnt | ||
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| case F32Abs => wa.F32Abs | ||
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| case F64Abs => wa.F64Abs | ||
| case F64Ceil => wa.F64Ceil | ||
| case F64Floor => wa.F64Floor | ||
| case F64Nearest => wa.F64Nearest | ||
| case F64Sqrt => wa.F64Sqrt | ||
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| case I32ReinterpretF32 => wa.I32ReinterpretF32 | ||
| case I64ReinterpretF64 => wa.I64ReinterpretF64 | ||
| case F32ReinterpretI32 => wa.F32ReinterpretI32 | ||
| case F64ReinterpretI64 => wa.F64ReinterpretI64 | ||
| } | ||
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| def printIR(out: IRTreePrinter): Unit = { | ||
| out.print("$") | ||
| out.print(wasmInstr.mnemonic) | ||
| out.printArgs(List(lhs)) | ||
| } | ||
| } | ||
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| object WasmUnaryOp { | ||
| /** Codes are raw Ints to be able to write switch matches on them. */ | ||
| type Code = Int | ||
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| final val I32Clz = 1 | ||
| final val I32Ctz = 2 | ||
| final val I32Popcnt = 3 | ||
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| final val I64Clz = 4 | ||
| final val I64Ctz = 5 | ||
| final val I64Popcnt = 6 | ||
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| final val F32Abs = 7 | ||
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| final val F64Abs = 8 | ||
| final val F64Ceil = 9 | ||
| final val F64Floor = 10 | ||
| final val F64Nearest = 11 | ||
| final val F64Sqrt = 12 | ||
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| final val I32ReinterpretF32 = 13 | ||
| final val I64ReinterpretF64 = 14 | ||
| final val F32ReinterpretI32 = 15 | ||
| final val F64ReinterpretI64 = 16 | ||
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| def resultTypeOf(op: Code): Type = (op: @switch) match { | ||
| case I32Clz | I32Ctz | I32Popcnt | I32ReinterpretF32 => | ||
| IntType | ||
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| case I64Clz | I64Ctz | I64Popcnt | I64ReinterpretF64 => | ||
| LongType | ||
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| case F32Abs | F32ReinterpretI32 => | ||
| FloatType | ||
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| case F64Abs | F64Ceil | F64Floor | F64Nearest | F64Sqrt | F64ReinterpretI64 => | ||
| DoubleType | ||
| } | ||
| } | ||
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| /** Wasm binary op. | ||
| * | ||
| * Wasm features a number of dedicated opcodes for operations that are not | ||
| * in the IR, but only implemented in user space. We can see `WasmBinaryOp` | ||
| * as an extension of `ir.Trees.BinaryOp` that covers those. | ||
| * | ||
| * Unsigned divisions and remainders exhibit always-unchecked undefined | ||
| * behavior when their rhs is 0. It is up to code generating those transient | ||
| * nodes to check for 0 themselves if necessary. | ||
| * | ||
| * All other Wasm binary ops preserve pureness. | ||
| */ | ||
| final case class WasmBinaryOp(op: WasmBinaryOp.Code, lhs: Tree, rhs: Tree) | ||
| extends Transient.Value { | ||
| import WasmBinaryOp._ | ||
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| val tpe: Type = resultTypeOf(op) | ||
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| def traverse(traverser: Traverser): Unit = { | ||
| traverser.traverse(lhs) | ||
| traverser.traverse(rhs) | ||
| } | ||
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| def transform(transformer: Transformer, isStat: Boolean)( | ||
| implicit pos: Position): Tree = { | ||
| Transient(WasmBinaryOp(op, transformer.transformExpr(lhs), | ||
| transformer.transformExpr(rhs))) | ||
| } | ||
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| def wasmInstr: wa.SimpleInstr = (op: @switch) match { | ||
| case I32DivU => wa.I32DivU | ||
| case I32RemU => wa.I32RemU | ||
| case I32Rotl => wa.I32Rotl | ||
| case I32Rotr => wa.I32Rotr | ||
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| case I64DivU => wa.I64DivU | ||
| case I64RemU => wa.I64RemU | ||
| case I64Rotl => wa.I64Rotl | ||
| case I64Rotr => wa.I64Rotr | ||
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| case F32Min => wa.F32Min | ||
| case F32Max => wa.F32Max | ||
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| case F64Min => wa.F64Min | ||
| case F64Max => wa.F64Max | ||
| } | ||
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| def printIR(out: IRTreePrinter): Unit = { | ||
| out.print("$") | ||
| out.print(wasmInstr.mnemonic) | ||
| out.printArgs(List(lhs, rhs)) | ||
| } | ||
| } | ||
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| object WasmBinaryOp { | ||
| /** Codes are raw Ints to be able to write switch matches on them. */ | ||
| type Code = Int | ||
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| final val I32DivU = 1 | ||
| final val I32RemU = 2 | ||
| final val I32Rotl = 3 | ||
| final val I32Rotr = 4 | ||
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| final val I64DivU = 5 | ||
| final val I64RemU = 6 | ||
| final val I64Rotl = 7 | ||
| final val I64Rotr = 8 | ||
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| final val F32Min = 9 | ||
| final val F32Max = 10 | ||
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| final val F64Min = 11 | ||
| final val F64Max = 12 | ||
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| def resultTypeOf(op: Code): Type = (op: @switch) match { | ||
| case I32DivU | I32RemU | I32Rotl | I32Rotr => | ||
| IntType | ||
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| case I64DivU | I64RemU | I64Rotl | I64Rotr => | ||
| LongType | ||
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| case F32Min | F32Max => | ||
| FloatType | ||
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| case F64Min | F64Max => | ||
| DoubleType | ||
| } | ||
| } | ||
| } | ||
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