Computer Architecture (COEN 210) Final Project

The modules in this repository make up a single cycle CPU for the MIPS ISA. The following instructions are supported:

Created by Charles Schultz

Name		Name	Last commit message	Last commit date
Latest commit History 7 Commits
ALU.v		ALU.v
ALUControl.v		ALUControl.v
BPC.v		BPC.v
CPU.v		CPU.v
Control.v		Control.v
DM.v		DM.v
IM.v		IM.v
MX2_32.v		MX2_32.v
MX2_5.v		MX2_5.v
PC.v		PC.v
README.md		README.md
RF.v		RF.v
SE.v		SE.v
alu_waveform.vwf		alu_waveform.vwf
aluctrl_waveform.vwf		aluctrl_waveform.vwf
controlunit_waveform.vwf		controlunit_waveform.vwf
cpu.vwf		cpu.vwf
dm_seed.txt		dm_seed.txt
dm_waveform.vwf		dm_waveform.vwf
im_seed.txt		im_seed.txt
im_waveform.vwf		im_waveform.vwf
pc_waveform.vwf		pc_waveform.vwf
rf_seed.txt		rf_seed.txt

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