Tags: smaeul/linux
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riscv: dts: allwinner: d1: Add power controller node The Allwinner D1 family of SoCs contain a PPU power domain controller separate from the PRCM. It can power down the video engine and DSP, and it contains special logic for hardware-assisted CPU idle. Series-to: Chen-Yu Tsai <[email protected]> Series-to: Jernej Skrabec <[email protected]> Series-cc: Krzysztof Kozlowski <[email protected]> Series-cc: Rob Herring <[email protected]> Series-version: 2 Series-changes: 2 - Include a patch adding the device tree node Cover-letter: Allwinner D1 power domain support This series adds support for the power controller found in D1 and other recent Allwinner SoCs. There is no first-party documentation, but there are a couple of vendor drivers for different hardware revisions[1][2], and the register definitions were easy to verify empirically. I have tested this driver on D1 with the video engine. [1]: https://github.com/mangopi-sbc/tina-linux-5.4/blob/main/drivers/soc/sunxi/gpu_domain.c [2]: https://github.com/mangopi-sbc/tina-linux-5.4/blob/main/drivers/soc/sunxi/pm_domains.c END Signed-off-by: Samuel Holland <[email protected]>
riscv: defconfig: Enable the Allwinner D1 platform and drivers Now that several D1-based boards are supported, enable the platform in our defconfig. Build in the drivers which are necessary to boot, such as the pinctrl, MMC, RTC (which provides critical clocks), SPI (for flash), and watchdog (which may be left enabled by the bootloader). Other common onboard peripherals are enabled as modules. Cover-letter: riscv: Allwinner D1/D1s platform support This series adds the Kconfig/defconfig plumbing and devicetrees for a range of Allwinner D1 and D1s-based boards. Many features are already enabled, including USB, Ethernet, and WiFi. This version drops all boards/nodes with missing YAML bindings, so at least some support can get merged for v6.3. $ make ARCH=riscv CROSS_COMPILE=riscv64-linux-musl- dtbs_check LINT Documentation/devicetree/bindings CHKDT Documentation/devicetree/bindings/processed-schema.json SCHEMA Documentation/devicetree/bindings/processed-schema.json DTC_CHK arch/riscv/boot/dts/allwinner/sun20i-d1-dongshan-nezha-stu.dtb DTC_CHK arch/riscv/boot/dts/allwinner/sun20i-d1-lichee-rv-86-panel-480p.dtb DTC_CHK arch/riscv/boot/dts/allwinner/sun20i-d1-lichee-rv-86-panel-720p.dtb DTC_CHK arch/riscv/boot/dts/allwinner/sun20i-d1-lichee-rv-dock.dtb DTC_CHK arch/riscv/boot/dts/allwinner/sun20i-d1-lichee-rv.dtb DTC_CHK arch/riscv/boot/dts/allwinner/sun20i-d1-mangopi-mq-pro.dtb DTC_CHK arch/riscv/boot/dts/allwinner/sun20i-d1-nezha.dtb DTC_CHK arch/riscv/boot/dts/allwinner/sun20i-d1s-mangopi-mq.dtb $ Note that validation requires dt-schema v2022.12 or newer. I thoroughly tested earlier versions of this series (DMIC, Ethernet, LEDs, MMC, PMIC, touch, and USB, where available) on several boards. v4/v5 have trivial changes, and I boot-tested them on sun20i-d1-nezha. END Series-version: 5 Cover-changes: 5 - Drop the ClockworkPi and DevTerm DTS, since it needs the system LDOs Commit-changes: 4 - Rebase on v6.2-rc1 + soc2arch-immutable Series-to: Chen-Yu Tsai <[email protected]> Series-to: Jernej Skrabec <[email protected]> Series-to: [email protected] Series-cc: Palmer Dabbelt <[email protected]> Series-cc: Conor Dooley <[email protected]> Series-cc: [email protected] Series-cc: Andre Przywara <[email protected]> Series-cc: Heiko Stuebner <[email protected]> Series-cc: Jisheng Zhang <[email protected]> Series-cc: Krzysztof Kozlowski <[email protected]> Series-cc: Rob Herring <[email protected]> Series-cc: [email protected] Series-cc: [email protected] Series-cc: [email protected] Acked-by: Conor Dooley <[email protected]> Acked-by: Palmer Dabbelt <[email protected]> Reviewed-by: Guo Ren <[email protected]> Reviewed-by: Heiko Stuebner <[email protected]> Signed-off-by: Samuel Holland <[email protected]>
riscv: dts: allwinner: d1: Add the IOMMU node D1 contains an IOMMU for its video-related hardware. Add the node, and hook it up to the masters which are already described in the devicetree. Cover-letter: iommu/sun50i: Allwinner D1 support D1 is a RISC-V SoC from Allwinner's sunxi family. This series adds IOMMU binding and driver support. The RISC-V architecture code still needs some small updates to use an IOMMU for DMA[1][2]. I will send those separately. [1]: https://lore.kernel.org/linux-riscv/[email protected]/ [2]: https://lore.kernel.org/linux-riscv/[email protected]/ END Series-version: 2 Commit-changes: 2 - New patch for v2 Series-to: Joerg Roedel <[email protected]> Series-to: Will Deacon <[email protected]> Series-to: Robin Murphy <[email protected]> Series-to: Chen-Yu Tsai <[email protected]> Series-to: Jernej Skrabec <[email protected]> Series-to: Krzysztof Kozlowski <[email protected]> Series-to: Rob Herring <[email protected]> Series-cc: Maxime Ripard <[email protected]> Series-cc: [email protected] Series-cc: [email protected] Series-cc: [email protected] Series-cc: [email protected] Series-cc: [email protected] Signed-off-by: Samuel Holland <[email protected]>
nvmem: sunxi_sid: Drop the workaround on A64 Now that the SRAM readout code is fixed by using 32-bit accesses, it always returns the same values as register readout, so the A64 variant no longer needs the workaround. This makes the D1 variant structure redundant, so remove it. Cover-letter: nvmem: sunxi_sid: Fix for D1 variant This is the first two patches from [1], with the stable CC added. The first patch fixes a bug causing incorrect values to be read; the second is a cleanup. I split the series since this bug needs to be fixed regardless of the DT binding discussion. [1]: https://lore.kernel.org/lkml/[email protected]/ END Series-version: 2 Cover-changes: 2 - Split out the driver fix from the other changes Series-to: Srinivas Kandagatla <[email protected]> Series-to: Chen-Yu Tsai <[email protected]> Series-to: Jernej Skrabec <[email protected]> Signed-off-by: Samuel Holland <[email protected]>
clk: sunxi-ng: d1: Add CAN bus gates and resets The D1 CCU contains gates and resets for two CAN buses. While the CAN bus controllers are only documented for the T113 SoC, the CCU is the same across all SoC variants. Series-to: Chen-Yu Tsai <[email protected]> Series-to: Jernej Skrabec <[email protected]> Series-to: Michael Turquette <[email protected]> Series-to: Stephen Boyd <[email protected]> Cover-letter: clk: sunxi-ng: Allwinner R528/T113 clock support R528 and T113 are SoCs based on the same design as D1/D1s, but with ARM CPUs instead of RISC-V. They use the same CCU implementation, meaning the CCU has gates/resets for all peripherals present on any SoC in this family. I verified the CAN bus bits are also present on D1/D1s. Patches 1-2 clean up the Kconfig in preparation for patch 3, which allows building the driver. Patches 4-6 add the missing binding header and driver bits. END Commit-changes: 2 - Move dt-bindings header changes to a separate patch Series-version: 2 Signed-off-by: Fabien Poussin <[email protected]> Reviewed-by: Andre Przywara <[email protected]> Signed-off-by: Samuel Holland <[email protected]>
soc: sunxi: Add Allwinner D1 PPU driver The PPU contains a series of identical MMIO register ranges, one for each power domain. Each range contains control/status bits for a clock gate, reset line, output gates, and a power switch. (The clock and reset are separate from, and in addition to, the bits in the CCU.) It also contains a hardware power sequence engine to control the other bits. Series-to: Chen-Yu Tsai <[email protected]> Series-to: Jernej Skrabec <[email protected]> Series-to: Krzysztof Kozlowski <[email protected]> Series-to: Rob Herring <[email protected]> Cover-letter: Allwinner power domain support This series adds support for the power controller found in D1 and other recent Allwinner SoCs. There is no first-party documentation, but there are a couple of vendor drivers for different hardware revisions[1][2], and the register definitions were easy to verify empirically. I have tested this driver on D1 with the video engine. There is no DT update patch here to avoid dependencies between series. The example in the binding is what will go in the D1 DT. [1]: https://github.com/mangopi-sbc/tina-linux-5.4/blob/main/drivers/soc/sunxi/gpu_domain.c [1]: https://github.com/mangopi-sbc/tina-linux-5.4/blob/main/drivers/soc/sunxi/pm_domains.c END Signed-off-by: Samuel Holland <[email protected]>
riscv: defconfig: Enable the Allwinner D1 platform and drivers Now that several D1-based boards are supported, enable the platform in our defconfig. Build in the drivers which are necessary to boot, such as the pinctrl, MMC, RTC (which provides critical clocks), SPI (for flash), and watchdog (which may be left enabled by the bootloader). Other common onboard peripherals are enabled as modules. Cover-letter: riscv: Allwinner D1/D1s platform support This series adds the Kconfig/defconfig plumbing and devicetrees for a range of Allwinner D1 and D1s-based boards. Many features are already enabled, including USB, Ethernet, and WiFi. The devicetrees use bindings from the following series which have not yet been merged to linux-next: - In-package LDO regulators: https://lore.kernel.org/lkml/[email protected]/ - Ethernet MAC binding fix (not a new issue with D1): https://lore.kernel.org/lkml/[email protected]/ The only remaining DT validation issue is that gpio-fan is missing a YAML conversion, although one is on the list here (v2): https://lore.kernel.org/lkml/[email protected]/ $ make ARCH=riscv CROSS_COMPILE=riscv64-linux-musl- dtbs_check SYNC include/config/auto.conf.cmd LINT Documentation/devicetree/bindings CHKDT Documentation/devicetree/bindings/processed-schema.json SCHEMA Documentation/devicetree/bindings/processed-schema.json DTC_CHK arch/riscv/boot/dts/allwinner/sun20i-d1-clockworkpi-v3.14.dtb DTC_CHK arch/riscv/boot/dts/allwinner/sun20i-d1-devterm-v3.14.dtb DTC_CHK arch/riscv/boot/dts/allwinner/sun20i-d1-dongshan-nezha-stu.dtb DTC_CHK arch/riscv/boot/dts/allwinner/sun20i-d1-lichee-rv-86-panel-480p.dtb DTC_CHK arch/riscv/boot/dts/allwinner/sun20i-d1-lichee-rv-86-panel-720p.dtb DTC_CHK arch/riscv/boot/dts/allwinner/sun20i-d1-lichee-rv-dock.dtb DTC_CHK arch/riscv/boot/dts/allwinner/sun20i-d1-lichee-rv.dtb DTC_CHK arch/riscv/boot/dts/allwinner/sun20i-d1-mangopi-mq-pro.dtb DTC_CHK arch/riscv/boot/dts/allwinner/sun20i-d1-nezha.dtb DTC_CHK arch/riscv/boot/dts/allwinner/sun20i-d1s-mangopi-mq.dtb arch/riscv/boot/dts/allwinner/sun20i-d1-devterm-v3.14.dtb:0:0: /fan: failed to match any schema with compatible: ['gpio-fan'] Note that validation requires dt-schema v2022.12 or newer. I thoroughly tested earlier versions of this series (DMIC, Ethernet, LEDs, MMC, PMIC, touch, and USB, where available) on several boards. v4 has only trivial changes, and I boot-tested it on sun20i-d1-nezha. This series is pretty much just waiting on the regulator binding to land. I do not expect to send another version. For the rest of the hardware blocks, DT additions will be based on top of this series. END Series-version: 4 Commit-changes: 4 - Rebase on v6.2-rc1 + soc2arch-immutable Series-to: Chen-Yu Tsai <[email protected]> Series-to: Jernej Skrabec <[email protected]> Series-to: [email protected] Series-cc: Palmer Dabbelt <[email protected]> Series-cc: Conor Dooley <[email protected]> Series-cc: [email protected] Series-cc: Andre Przywara <[email protected]> Series-cc: Heiko Stuebner <[email protected]> Series-cc: Jisheng Zhang <[email protected]> Series-cc: Krzysztof Kozlowski <[email protected]> Series-cc: Rob Herring <[email protected]> Series-cc: [email protected] Series-cc: [email protected] Series-cc: [email protected] Acked-by: Conor Dooley <[email protected]> Acked-by: Palmer Dabbelt <[email protected]> Reviewed-by: Guo Ren <[email protected]> Reviewed-by: Heiko Stuebner <[email protected]> Signed-off-by: Samuel Holland <[email protected]>
riscv: dts: allwinner: d1: Add crypto engine node D1 contains a crypto engine which is supported by the sun8i-ce driver. Series-version: 2 Commit-changes: 2 - New patch for v2 Series-to: Corentin Labbe <[email protected]> Series-to: Herbert Xu <[email protected]> Series-to: David S. Miller <[email protected]> Series-to: Chen-Yu Tsai <[email protected]> Series-to: Jernej Skrabec <[email protected]> Series-to: Krzysztof Kozlowski <[email protected]> Series-to: Rob Herring <[email protected]> Cover-letter: crypto: Allwinner D1 crypto support This series finishes adding crypto support for the Allwinner D1 SoC. The driver patch from v1 was merged, but not the binding[1]. This turned out to be a good thing, because I later found that the TRNG needed another clock reference in the devicetree. That is fixed in v2. I include the DT update here too, since the SoC DT has been on the list for a while[2]. [1]: https://lore.kernel.org/all/[email protected]/T/ [2]: https://lore.kernel.org/lkml/[email protected]/ END Signed-off-by: Samuel Holland <[email protected]>
clk: sunxi-ng: Avoid computing the rate twice The ccu_*_find_best() functions already compute a best_rate at the same time as the other factors. Return this value so the caller does not need to duplicate the computation. Series-to: Chen-Yu Tsai <[email protected]> Series-to: Jernej Skrabec <[email protected]> Series-version: 2 Series-changes: 2 - Apply the same change also to nk, nkm, nkmp, and nm - Update the commit message Signed-off-by: Samuel Holland <[email protected]>
riscv: dts: allwinner: d1: Add video engine node D1 contains a video engine which is supported by the Cedrus driver. Series-to: Chen-Yu Tsai <[email protected]> Series-to: Jernej Skrabec <[email protected]> Series-to: Paul Kocialkowski <[email protected]> Series-to: Mauro Carvalho Chehab <[email protected]> Series-to: Rob Herring <[email protected]> Series-to: Krzysztof Kozlowski <[email protected]> Cover-letter: Allwinner D1 video engine support This series finishes adding Cedrus support for Allwinner D1. I had tested the hardware and documented the compatible string a while back, but at the time I had a dummy SRAM section in the devicetree. Further testing shows that there is no switchable SRAM section -- there is no need for it, I was unable to guess the address, and the usual bits in the SRAM controller register have no effect on the video engine. So that needs to be made optional in the binding and driver. With that done, the node can be added to the devicetree. END Signed-off-by: Samuel Holland <[email protected]>
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