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Add L0x0 processor family #505

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Merged
merged 21 commits into from
Mar 14, 2021
Merged

Add L0x0 processor family #505

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c87b049
add L0x0 series svd
jglauche Feb 25, 2021
33b359a
migrate l0x1 patches to 0x0
jglauche Feb 25, 2021
004e403
re-enabled patched syscfg file
jglauche Feb 25, 2021
525a006
remove unavailable feature
jglauche Feb 25, 2021
17a1819
Update devices/stm32l0x0.yaml
jglauche Feb 28, 2021
064a22a
Update devices/stm32l0x0.yaml
jglauche Feb 28, 2021
98b860b
Update devices/stm32l0x0.yaml
jglauche Feb 28, 2021
013831b
Update devices/stm32l0x0.yaml
jglauche Feb 28, 2021
0140e1b
Update devices/stm32l0x0.yaml
jglauche Feb 28, 2021
ec7d6c9
Update devices/stm32l0x0.yaml
jglauche Feb 28, 2021
a618761
Update peripherals/syscfg/syscfg_l0x0.yaml
jglauche Feb 28, 2021
7e0d35f
Update devices/stm32l0x0.yaml
jglauche Feb 28, 2021
41b9f61
Update devices/stm32l0x0.yaml
jglauche Feb 28, 2021
876c7b1
Update peripherals/syscfg/syscfg_l0x0.yaml
jglauche Feb 28, 2021
5bcbd53
Update peripherals/syscfg/syscfg_l0x0.yaml
jglauche Feb 28, 2021
0564c34
leave WPROT as it is in the SVD
jglauche Feb 28, 2021
a1e5432
copy rcc_l0 to _l0x0 to remove CRYPSMEN
jglauche Feb 28, 2021
6e27fb6
remove unused I2C FMP bits, remove CAPA
jglauche Feb 28, 2021
4136f4d
rename FWDISEN to FWDIS
jglauche Feb 28, 2021
4b235a3
remove unavailble AF modes 8-15
jglauche Mar 9, 2021
66615c1
Merge branch 'master' of https://github.com/stm32-rs/stm32-rs
jglauche Mar 11, 2021
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remove unused I2C FMP bits, remove CAPA
  • Loading branch information
@jglauche
jglauche committed Feb 28, 2021
commit 6e27fb66ca429b45e92214f15e3426abb4200c82
20 changes: 2 additions & 18 deletions peripherals/syscfg/syscfg_l0x0.yaml
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Expand Up @@ -10,24 +10,8 @@ SYSCFG:
SystemFlash: [1, "System Flash memory mapped at 0x0000_0000"]
SRAM: [3, "Embedded SRAM mapped at 0x0000_0000"]
CFGR2:
I2C2_FMP:
Standard: [0, "FM+ mode is controlled by I2C_Pxx_FMP bits only"]
FMP: [1, "FM+ mode is enabled on all I2C2 pins selected through selection bits in GPIOx_AFR registers"]
I2C1_FMP:
Standard: [0, "FM+ mode is controlled by I2C_Pxx_FMP bits only"]
FMP: [1, "FM+ mode is enabled on all I2C1 pins selected through selection bits in GPIOx_AFR registers"]
I2C_PB9_FMP:
Standard: [0, "PB9 pin operate in standard mode"]
FMP: [1, "I2C FM+ mode enabled on PB9 and the Speed control is bypassed"]
I2C_PB8_FMP:
Standard: [0, "PB8 pin operate in standard mode"]
FMP: [1, "I2C FM+ mode enabled on PB8 and the Speed control is bypassed"]
I2C_PB7_FMP:
Standard: [0, "PB7 pin operate in standard mode"]
FMP: [1, "I2C FM+ mode enabled on PB7 and the Speed control is bypassed"]
I2C_PB6_FMP:
Standard: [0, "PB6 pin operate in standard mode"]
FMP: [1, "I2C FM+ mode enabled on PB6 and the Speed control is bypassed"]
_delete:
CAPA
CFGR3:
REF_LOCK:
ReadWrite: [0, "SYSCFG_CFGR3[31:0] bits are read/write"]
Expand Down