Fix bit offset for RMVF in STM32l0x2 and STM32l0x3 #566
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According to the reference manuals for STM32L0x{2, 3}, the RCC_CSR
register RMVF has the offset 23 and not 24. Offset 24 is occupied by a
Firewall reset which is also added in this change
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The change itself looks good, thanks! Once small regression - you've accidentally over-written the |
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@richardeoin Thanks, pushed a fix. |
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According to the reference manuals for STM32L0x{2, 3}, the RCC_CSR
register RMVF has the offset 23 and not 24. Offset 24 is occupied by a
Firewall reset which is also added in this change
Page 219 in the STM32L0x2 release manual can be used to verify.