stm32wl: add register descriptions for dual-core variants #628
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stm32wl: add register descriptions for dual-core variants
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,145 @@ | ||
| FLASH: | ||
| IPCCBR: | ||
| IPCCDBA: [0, 0x1FFF] | ||
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||
| C2ACR: | ||
| PES: | ||
| Granted: [0, "Flash program and erase operations granted"] | ||
| Suspended: [1, "Any new Flash program and erase operation is suspended until this bit is cleared. The PESD bit in FLASH_C2SR is set when PES bit in FLASH_C2ACR is set"] | ||
| ICRST: | ||
| NotReset: [0, "CPU2 instruction cache is not reset"] | ||
| Reset: [1, "CPU2 instruction cache is reset"] | ||
| ICEN: | ||
| Disabled: [0, "CPU2 instruction cache is disabled"] | ||
| Enabled: [1, "CPU2 instruction cache is enabled"] | ||
| PRFTEN: | ||
| Disabled: [0, "CPU2 prefetch is disabled"] | ||
| Enabled: [1, "CPU2 prefetch is enabled"] | ||
| C2SR: | ||
| _modify: | ||
| MISERR: | ||
| name: MISSERR | ||
| PESD: | ||
| Granted: [0, "Flash program and erase operations granted"] | ||
| Suspended: [1, "Any new Flash program and erase operation is suspended until this bit is cleared. This bit is set when at least one PES bit in FLASH_ACR or FLASH_C2ACR is set."] | ||
| CFGBSY: | ||
| Free: [0, "PG, PNB, PER, MER bits available for writing"] | ||
| Busy: [1, "PG, PNB, PER, MER bits not available for writing (operation ongoing)"] | ||
| BSY: | ||
| Inactive: [0, "No write/erase operation is in progress"] | ||
| Active: [1, "No write/erase operation is in progress"] | ||
| RDERR: | ||
| _read: | ||
| NoError: [0, "No read-only error happened"] | ||
| Error: [1, "Read-only error happened"] | ||
| _write: | ||
| Clear: [1, "Clear the flag"] | ||
| FASTERR: | ||
| _read: | ||
| NoError: [0, "No fast programming error happened"] | ||
| Error: [1, "Fast programming error happened"] | ||
| _write: | ||
| Clear: [1, "Clear the flag"] | ||
| MISSERR: | ||
| _read: | ||
| NoError: [0, "No fast programming data miss error happened"] | ||
| Error: [1, "Fast programming data miss error happened"] | ||
| _write: | ||
| Clear: [1, "Clear the flag"] | ||
| PGSERR: | ||
| _read: | ||
| NoError: [0, "No fast programming sequence error happened"] | ||
| Error: [1, "Fast programming sequence error happened"] | ||
| _write: | ||
| Clear: [1, "Clear the flag"] | ||
| SIZERR: | ||
| _read: | ||
| NoError: [0, "No size error happened"] | ||
| Error: [1, "Size error happened"] | ||
| _write: | ||
| Clear: [1, "Clear the flag"] | ||
| PGAERR: | ||
| _read: | ||
| NoError: [0, "No programming alignment error happened"] | ||
| Error: [1, "Programming alignment error happened"] | ||
| _write: | ||
| Clear: [1, "Clear the flag"] | ||
| WRPERR: | ||
| _read: | ||
| NoError: [0, "No write protection error happened"] | ||
| Error: [1, "Write protection error happened"] | ||
| _write: | ||
| Clear: [1, "Clear the flag"] | ||
| PROGERR: | ||
| _read: | ||
| NoError: [0, "No size programming error happened"] | ||
| Error: [1, "Programming error happened"] | ||
| _write: | ||
| Clear: [1, "Clear the flag"] | ||
| OPERR: | ||
| _read: | ||
| NoError: [0, "No memory opreation error happened"] | ||
| Error: [1, "Memory operation error happened"] | ||
| _write: | ||
| Clear: [1, "Clear the flag"] | ||
| EOP: | ||
| _read: | ||
| NoEvent: [0, "No EOP operation occurred"] | ||
| Event: [1, "An EOP event occurred"] | ||
| _write: | ||
| Clear: [1, "Clear the flag"] | ||
| C2CR: | ||
| RDERRIE: | ||
| Disabled: [0, "PCROP read error interrupt disable"] | ||
| Enabled: [1, "PCROP read error interrupt enable"] | ||
| ERRIE: | ||
| Disabled: [0, "OPERR Error interrupt disable"] | ||
| Enabled: [1, "OPERR Error interrupt enable"] | ||
| EOPIE: | ||
| Disabled: [0, "End of program interrupt disable"] | ||
| Enabled: [1, "End of program interrupt enable"] | ||
| FSTPG: | ||
| Disabled: [0, "Fast programming disabled"] | ||
| Enabled: [1, "Fast programming enabled"] | ||
| STRT: | ||
| _read: | ||
| Done: [0, "Options modification completed or idle"] | ||
| _write: | ||
| Start: [1, "Trigger options programming operation"] | ||
| PNB: [0, 0x7F] | ||
| MER: | ||
| NoErase: [0, "No mass erase"] | ||
| MassErase: [1, "Trigger mass erase"] | ||
| PER: | ||
| Disabled: [0, "Page erase disabled"] | ||
| Enabled: [1, "Page erase enabled"] | ||
| PG: | ||
| Disabled: [0, "Flash programming disabled"] | ||
| Enabled: [1, "Flash programming enabled"] | ||
| SFR: | ||
| SUBGHSPISD: | ||
| Enabled: [0, "sub-GHz radio SPI security enabled"] | ||
| Disabled: [1, "sub-GHz radio SPI security disabled"] | ||
| HDPAD: | ||
| Enabled: [0, "User Flash memory hide protection area enabled. HDPSA[6:0] contains the start address of the first 2-Kbyte page of the user Flash memory hide protection area"] | ||
| Disabled: [1, "User Flash memory hide protection area disabled"] | ||
| HDPSA: [0, 0x7F] | ||
| DDS: | ||
| Enabled: [0, "CPU2 debug access enabled"] | ||
| Disabled: [1, "CPU2 debug access disabled"] | ||
| FSD: | ||
| Secure: [0, "System and Flash memory secure"] | ||
| NonSecure: [1, "System and Flash memory non-secure"] | ||
| SFSA: [0, 0x7F] | ||
| SRRVR: | ||
| C2OPT: | ||
| SRAM: [0, "SBRV offset addresses SRAM1 or SRAM2, from start address 0x2000_0000 + SBRV"] | ||
| Flash: [1, "SBRV offset addresses the Flash memory, from start address 0x0800_0000 + SBRV"] | ||
| NBRSD: | ||
| Secure: [0, 'SRAM1 is secure. SNBRSA[4:0] contains the start address of the first 1-Kbyte page of the secure non-backup SRAM1 area'] | ||
| NonSecure: [1, 'SRAM1 is non-secure'] | ||
| SNBRSA: [0, 0x1F] | ||
| BRSD: | ||
| Secure: [0, 'SRAM2 is secure. SNBRSA[4:0] contains the start address of the first 1-Kbyte page of the secure backup SRAM2 area'] | ||
| NonSecure: [1, 'SRAM2 is non-secure'] | ||
| SBRSA: [0, 0x1F] | ||
| SBRV: [0, 0xFFFF] | ||
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,26 @@ | ||
| IPCC: | ||
| "C[12]CR": | ||
| TXFIE: | ||
| Enabled: [1, "Enable an unmasked processor transmit channel free to generate a TX free interrupt"] | ||
| Disabled: [0, "Processor TX free interrupt disabled"] | ||
| RXOIE: | ||
| Enabled: [1, "Enable an unmasked processor receive channel occupied to generate an RX occupied interrupt"] | ||
| Disabled: [0, "Processor RX occupied interrupt disabled"] | ||
| "C[12]MR": | ||
| "CH[1-6]FM": | ||
| Masked: [1, "Transmit channel n free interrupt masked"] | ||
| Unmasked: [0, "Transmit channel n free interrupt not masked"] | ||
| "CH[1-6]OM": | ||
| Masked: [1, "Receive channel n occupied interrupt masked"] | ||
| Unmasked: [0, "Receive channel n occupied interrupt not masked"] | ||
| "C[12]SCR": | ||
| "CH[1-6]S": | ||
| Clear: [1, "Processor transmit channel n status bit set"] | ||
| NoAction: [0, "No action"] | ||
| "CH[1-6]C": | ||
| Clear: [1, "Processor receive channel n status bit set"] | ||
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| NoAction: [0, "No action"] | ||
| "C[12]TOC[12]SR": | ||
| "CH[1-5]F": | ||
| Occupied: [1, "Channel occupied, data can be read by the receiving processor. Generates a channel RX occupied interrupt to the other processor, when unmasked"] | ||
| Free: [0, "Channel free, data can be written by the sending processor. Generates a channel TX free interrupt to the current processor, when unmasked"] | ||
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,39 @@ | ||
| PWR: | ||
| C2CR1: | ||
| FPDS: | ||
| Idle: [0, "Flash memory in Idle mode when system is in LPSleep mode"] | ||
| PowerDown: [1, "Flash memory in Power-down mode when system is in LPSleep mode"] | ||
| FPDR: | ||
| Idle: [0, "Flash memory in Idle mode when system is in LPRun mode"] | ||
| PowerDown: [1, "Flash memory in Power-down mode when system is in LPRun mode"] | ||
| LPMS: | ||
| Stop0: [0, "Stop 0 mode"] | ||
| Stop1: [1, "Stop 1 mode"] | ||
| Stop2: [2, "Stop 2 mode"] | ||
| Standby: [3, "Standby mode"] | ||
| Shutdown: [4, "Shutdown mode"] | ||
| C2CR3: | ||
| EIWUL: | ||
| Disabled: [0, "Internal wakeup line interrupt to CPU2 disabled"] | ||
| Enabled: [1, "Internal wakeup line interrupt to CPU2 enabled"] | ||
| EWRFIRQ: | ||
| Disabled: [0, "Radio IRQ[2:0] is disabled and does not trigger a wakeup from Standby event to CPU2."] | ||
| Enabled: [1, "Radio IRQ[2:0] is enabled and triggers a wakeup from Standby event to CPU2."] | ||
| EWRFBUSY: | ||
| Disabled: [0, "Radio Busy is disabled and does not trigger a wakeup from Standby event to CPU2 when a rising or a falling edge occurs"] | ||
| Enabled: [1, "Radio Busy is enabled and triggers a wakeup from Standby event to CPU2 when a rising or a falling edge occurs. The active edge is configured via the WRFBUSYP bit in PWR_CR4"] | ||
| APC: | ||
| Disabled: [0, "I/O pull-up and pull-down configurations defined in the PWR_PUCRx and PWR_PDCRx registers are applied"] | ||
| Enabled: [1, "PWR_PUCRx and PWR_PDCRx registers are NOT applied to the I/Os"] | ||
| EWPVD: | ||
| Disabled: [0, "PVD not enabled by the sub-GHz radio active state"] | ||
| Enabled: [1, "PVD enabled while the sub-GHz radio is active"] | ||
| EWUP3: | ||
| Disabled: [0, "WKUP pin 3 is used for general purpose I/Os. An event on the WKUP pin 3 does not wakeup the device from Standby mode"] | ||
| Enabled: [1, "WKUP pin 3 is used for wakeup from Standby mode and forced in input pull down configuration (rising edge on WKUP pin 3wakes-up the system from Standby mode)"] | ||
| EWUP2: | ||
| Disabled: [0, "WKUP pin 2 is used for general purpose I/Os. An event on the WKUP pin 2 does not wakeup the device from Standby mode"] | ||
| Enabled: [1, "WKUP pin 2 is used for wakeup from Standby mode and forced in input pull down configuration (rising edge on WKUP pin 2 wakes-up the system from Standby mode)"] | ||
| EWUP1: | ||
| Disabled: [0, "WKUP pin 1 is used for general purpose I/Os. An event on the WKUP pin 1 does not wakeup the device from Standby mode"] | ||
| Enabled: [1, "WKUP pin 1 is used for wakeup from Standby mode and forced in input pull down configuration (rising edge on WKUP pin 1 wakes-up the system from Standby mode)"] |
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,15 @@ | ||
| RCC: | ||
| "C2A[PH]B[123]ENR": | ||
| "*": | ||
| Disabled: [0, "Clock disabled"] | ||
| Enabled: [1, "Clock enabled"] | ||
|
|
||
| "C2APB[123]ENR?": | ||
| "*": | ||
| Disabled: [0, "Clock disabled"] | ||
| Enabled: [1, "Clock enabled"] | ||
|
|
||
| "C2A[PH]B[123]SMENR?": | ||
| "*": | ||
| Disabled: [0, "Clock disabled"] | ||
| Enabled: [1, "Clock enabled"] |
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I think this is an error in the STM32WLE reference manual, the STM32WLE manual only goes from page 0 - 63 (the value should be 0x3F in that case), but in the STM32WL5X reference manual this goes from 0 - 127.
As far as I can tell the STM32WLE is capable of programming its whole 256K, same as the STM32WL5X.