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Try #3327:
2 parents 39bd622 + 93e9ea2 commit bf891be

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39 files changed

+564
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lines changed

39 files changed

+564
-68
lines changed

boards/apollo3/lora_things_plus/src/io.rs

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -23,9 +23,10 @@ impl Write for Writer {
2323
}
2424

2525
impl IoWrite for Writer {
26-
fn write(&mut self, buf: &[u8]) {
26+
fn write(&mut self, buf: &[u8]) -> usize {
2727
let uart = apollo3::uart::Uart::new_uart_0(); // Aliases memory for uart0. Okay bc we are panicking.
2828
uart.transmit_sync(buf);
29+
buf.len()
2930
}
3031
}
3132

boards/apollo3/redboard_artemis_nano/src/io.rs

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -23,9 +23,10 @@ impl Write for Writer {
2323
}
2424

2525
impl IoWrite for Writer {
26-
fn write(&mut self, buf: &[u8]) {
26+
fn write(&mut self, buf: &[u8]) -> usize {
2727
let uart = apollo3::uart::Uart::new_uart_0(); // Aliases memory for uart0. Okay bc we are panicking.
2828
uart.transmit_sync(buf);
29+
buf.len()
2930
}
3031
}
3132

boards/arty_e21/src/io.rs

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -25,8 +25,9 @@ impl Write for Writer {
2525
}
2626

2727
impl IoWrite for Writer {
28-
fn write(&mut self, buf: &[u8]) {
28+
fn write(&mut self, buf: &[u8]) -> usize {
2929
sifive::uart::Uart::new(arty_e21_chip::uart::UART0_BASE, 32_000_000).transmit_sync(buf);
30+
buf.len()
3031
}
3132
}
3233

boards/clue_nrf52840/src/io.rs

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -46,7 +46,7 @@ impl uart::TransmitClient for DummyUsbClient {
4646
}
4747

4848
impl IoWrite for Writer {
49-
fn write(&mut self, buf: &[u8]) {
49+
fn write(&mut self, buf: &[u8]) -> usize {
5050
if !self.initialized {
5151
self.initialized = true;
5252
}
@@ -114,6 +114,7 @@ impl IoWrite for Writer {
114114
DUMMY.fired.set(false);
115115
});
116116
}
117+
buf.len()
117118
}
118119
}
119120

boards/components/src/console.rs

Lines changed: 81 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -1,11 +1,19 @@
1-
//! Components for Console, the generic serial interface, and for multiplexed access
2-
//! to UART.
1+
//! Components for Console and ConsoleOrdered. These are two alternative implementations of
2+
//! the serial console system call interface. Console allows prints of arbitrary length but does
3+
//! not have ordering or atomicity guarantees. ConsoleOrdered, in contrast, has limits on the
4+
//! maximum lengths of prints but provides a temporal ordering and ensures a print is atomic at
5+
//! least up to particular length (typically 200 bytes). Console is useful when userspace is
6+
//! printing large messages. ConsoleOrdered is useful when you are debugging and there are
7+
//! inter-related messages from the kernel and userspace, whose ordering is important to
8+
//! maintain.
39
//!
410
//!
5-
//! This provides two Components, `ConsoleComponent`, which implements a buffered
6-
//! read/write console over a serial port, and `UartMuxComponent`, which provides
7-
//! multiplexed access to hardware UART. As an example, the serial port used for
8-
//! console on Imix is typically USART3 (the DEBUG USB connector).
11+
//! This provides three Components, `ConsoleComponent` and
12+
//! `ConsoleOrderedComponent`, which implement a buffered read/write
13+
//! console over a serial port, and `UartMuxComponent`, which provides
14+
//! multiplexed access to hardware UART. As an example, the serial
15+
//! port used for console on Imix is typically USART3 (the DEBUG USB
16+
//! connector).
917
//!
1018
//! Usage
1119
//! -----
@@ -20,12 +28,16 @@
2028
// Last modified: 1/08/2020
2129

2230
use capsules_core::console;
31+
use capsules_core::console_ordered::ConsoleOrdered;
32+
33+
use capsules_core::virtualizers::virtual_alarm::{MuxAlarm, VirtualMuxAlarm};
2334
use capsules_core::virtualizers::virtual_uart::{MuxUart, UartDevice};
2435
use core::mem::MaybeUninit;
2536
use kernel::capabilities;
2637
use kernel::component::Component;
2738
use kernel::create_capability;
2839
use kernel::hil;
40+
use kernel::hil::time::{self, Alarm};
2941
use kernel::hil::uart;
3042

3143
use capsules_core::console::DEFAULT_BUF_SIZE;
@@ -148,3 +160,66 @@ impl Component for ConsoleComponent {
148160
console
149161
}
150162
}
163+
#[macro_export]
164+
macro_rules! console_ordered_component_static {
165+
($A:ty $(,)?) => {{
166+
let mux_alarm = kernel::static_buf!(VirtualMuxAlarm<'static, $A>);
167+
let console = kernel::static_buf!(ConsoleOrdered<'static, VirtualMuxAlarm<'static, $A>>);
168+
(mux_alarm, console)
169+
};};
170+
}
171+
172+
pub struct ConsoleOrderedComponent<A: 'static + time::Alarm<'static>> {
173+
board_kernel: &'static kernel::Kernel,
174+
driver_num: usize,
175+
alarm_mux: &'static MuxAlarm<'static, A>,
176+
atomic_size: usize,
177+
retry_timer: u32,
178+
write_timer: u32,
179+
}
180+
181+
impl<A: 'static + time::Alarm<'static>> ConsoleOrderedComponent<A> {
182+
pub fn new(
183+
board_kernel: &'static kernel::Kernel,
184+
driver_num: usize,
185+
alarm_mux: &'static MuxAlarm<'static, A>,
186+
atomic_size: usize,
187+
retry_timer: u32,
188+
write_timer: u32,
189+
) -> ConsoleOrderedComponent<A> {
190+
ConsoleOrderedComponent {
191+
board_kernel: board_kernel,
192+
driver_num: driver_num,
193+
alarm_mux: alarm_mux,
194+
atomic_size: atomic_size,
195+
retry_timer: retry_timer,
196+
write_timer: write_timer,
197+
}
198+
}
199+
}
200+
201+
impl<A: 'static + time::Alarm<'static>> Component for ConsoleOrderedComponent<A> {
202+
type StaticInput = (
203+
&'static mut MaybeUninit<VirtualMuxAlarm<'static, A>>,
204+
&'static mut MaybeUninit<ConsoleOrdered<'static, VirtualMuxAlarm<'static, A>>>,
205+
);
206+
type Output = &'static ConsoleOrdered<'static, VirtualMuxAlarm<'static, A>>;
207+
208+
fn finalize(self, static_buffer: Self::StaticInput) -> Self::Output {
209+
let grant_cap = create_capability!(capabilities::MemoryAllocationCapability);
210+
211+
let virtual_alarm1 = static_buffer.0.write(VirtualMuxAlarm::new(self.alarm_mux));
212+
virtual_alarm1.setup();
213+
214+
let console = static_buffer.1.write(ConsoleOrdered::new(
215+
virtual_alarm1,
216+
self.board_kernel.create_grant(self.driver_num, &grant_cap),
217+
self.atomic_size,
218+
self.retry_timer,
219+
self.write_timer,
220+
));
221+
222+
virtual_alarm1.set_alarm_client(console);
223+
console
224+
}
225+
}

boards/esp32-c3-devkitM-1/src/io.rs

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -20,11 +20,12 @@ impl Write for Writer {
2020
}
2121

2222
impl IoWrite for Writer {
23-
fn write(&mut self, buf: &[u8]) {
23+
fn write(&mut self, buf: &[u8]) -> usize {
2424
let uart = esp32::uart::Uart::new(esp32::uart::UART0_BASE);
2525
uart.disable_tx_interrupt();
2626
uart.disable_rx_interrupt();
2727
uart.transmit_sync(buf);
28+
buf.len()
2829
}
2930
}
3031

boards/hail/src/io.rs

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -25,7 +25,7 @@ impl Write for Writer {
2525
}
2626

2727
impl IoWrite for Writer {
28-
fn write(&mut self, buf: &[u8]) {
28+
fn write(&mut self, buf: &[u8]) -> usize {
2929
// Here, we create a second instance of the USART0 struct.
3030
// This is okay because we only call this during a panic, and
3131
// we will never actually process the interrupts
@@ -47,6 +47,7 @@ impl IoWrite for Writer {
4747
uart.send_byte(regs_manager, c);
4848
while !uart.tx_ready(regs_manager) {}
4949
}
50+
buf.len()
5051
}
5152
}
5253

boards/hifive1/src/io.rs

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -24,9 +24,10 @@ impl Write for Writer {
2424
}
2525

2626
impl IoWrite for Writer {
27-
fn write(&mut self, buf: &[u8]) {
27+
fn write(&mut self, buf: &[u8]) -> usize {
2828
let uart = sifive::uart::Uart::new(e310_g002::uart::UART0_BASE, 16_000_000);
2929
uart.transmit_sync(buf);
30+
buf.len()
3031
}
3132
}
3233

boards/hifive_inventor/src/io.rs

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -23,9 +23,10 @@ impl Write for Writer {
2323
}
2424

2525
impl IoWrite for Writer {
26-
fn write(&mut self, buf: &[u8]) {
26+
fn write(&mut self, buf: &[u8]) -> usize {
2727
let uart = sifive::uart::Uart::new(e310_g003::uart::UART0_BASE, 16_000_000);
2828
uart.transmit_sync(buf);
29+
buf.len()
2930
}
3031
}
3132

boards/imix/src/io.rs

Lines changed: 4 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -25,7 +25,7 @@ impl Write for Writer {
2525
}
2626

2727
impl IoWrite for Writer {
28-
fn write(&mut self, buf: &[u8]) {
28+
fn write(&mut self, buf: &[u8]) -> usize {
2929
// Here, we create a second instance of the USART3 struct.
3030
// This is okay because we only call this during a panic, and
3131
// we will never actually process the interrupts
@@ -43,10 +43,13 @@ impl IoWrite for Writer {
4343
uart.enable_tx(regs_manager);
4444
}
4545
// XXX: I'd like to get this working the "right" way, but I'm not sure how
46+
let mut total = 0;
4647
for &c in buf {
4748
uart.send_byte(regs_manager, c);
4849
while !uart.tx_ready(regs_manager) {}
50+
total = total + 1;
4951
}
52+
total
5053
}
5154
}
5255

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