litex: update LiteX revision, use "Secure"/"TockSecureIMC" cpu variant and integrate PMP #2290
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This switches to using the "Secure" VexRiscv core of [pythondata-cpu-vexriscv](https://github.com/litex-hub/pythondata-cpu-vexriscv/) featuring a physical memory protection unit with 16 slots.
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Great to hear the hardware works, tag me if you find any bugs 🎅 |
This changes the LiteX-ArtyA7 board to use a custom VexRiscv CPU with physical memory protection, hardware multiplication and compressed instruction support. This allows Tock to use the available Rust target architecture "riscv32imc", utilizing the hardware multiplication and compressed instruction support of the CPU.
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Since this PR is still open, I've also switched The "TockSecureIMC" VexRiscv variant is however not contained upstream. I've documented (in the README) where to obtain the patch to The Verilated LiteX simulation ( |
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Given this got one approval, I'd raise the question again whether it'd be a good idea to move lschuermann/tock-litex to the Tock GitHub organisation, given that I point to this repository in the README and we rely on a softcore CPU configuration defined in there. |
I don't see a need to do this, as we generally consider hardware to be outside of Tock and maintained by someone else. |
| build infrastructure in | ||
| [pythondata-cpu-vexriscv](https://github.com/litex-hub/pythondata-cpu-vexriscv), | ||
| using a | ||
| [patch](https://github.com/lschuermann/tock-litex/blob/master/pkgs/pythondata-cpu-vexriscv/0001-Add-TockSecureIMC-cpu-variant.patch) |
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Could this patch be upstreamed?
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I think there might be a chance of getting this CPU configuration upstreamed in the pythondata-cpu-vexriscv, but based on my understanding this repository is simply a default collection of some variants anyways. When you're building some hardware / gateware, or targeting some hardware from an OS, it'd be expected for you to build some custom CPU meeting these requirements anyways. For people who don't feel like using Scala to build it, I upload the patched & built pythondata-cpu-vexriscv along with every release.
Sounds good. Thanks for the clarification! |
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bors r+ |
Pull Request Overview
This pull request
updates the targeted LiteX revision for both boards (
litex/simandlitex/arty)points to a companion repository (tock-litex), which contains prebuilt bitstreams and build scripts for generating these
The board definitions in this repository are tested against bitstreams obtained by these build scripts, so it makes sense to publish the bitstreams themselves as well.
changes the LiteX boards to require the "Secure" / "TockSecureIMC" VexRiscv CPU variant containing a PMP and enables PMP support in the
litex_vexriscvchip crate"TockSecureIMC" is a custom VexRiscv CPU configuration which has support for PMP, hardware multiplication and compressed instructions. It significantly reduces code size and should improve performance. The patch to the upstream
pythondata-cpu-vexriscvcan be found here. Prebuilt Verilog-files and complete bitstreams are published as part of thetock-litexrepository releases.Testing Strategy
This pull request was tested by running the
mputest app with all test cases on both the Arty A7 35T and the Verilated simulation.TODO or Help Wanted
I don't think it's very elegant to point to some outside repository for the generated bitstreams. It might be more trustworthy to have this repository under the Tock GitHub organization, given that we already have the Community GitHub team. I'd be open to moving it, but also fine if it stays in the current location.
Documentation Updated
/docs, or no updates are required.Formatting
make prepush.Acknowledgements
A huge thanks to @lindemer for contributing PMP support to VexRiscv. This must have been a lot of work.
I was also impressed by the PMP infrastructure in Tock. Everything worked flawlessly on the first try. Thanks to @bradjc, @alistair23 and all other contributors!