tock · bors · Jan 7, 2021 · Dec 20, 2020 · Dec 20, 2020 · Dec 20, 2020
diff --git a/boards/litex/arty/Makefile b/boards/litex/arty/Makefile
@@ -1,7 +1,7 @@
 # Makefile for building the tock kernel for a LiteX SoC targeting a
 # Digilent Arty-A7 FPGA development board
 
-TARGET=riscv32i-unknown-none-elf
+TARGET=riscv32imc-unknown-none-elf
 PLATFORM=litex_arty
 
 include ../../Makefile.common

diff --git a/boards/litex/arty/README.md b/boards/litex/arty/README.md
@@ -11,21 +11,40 @@ differ significantly depending on the LiteX release and configuration
 options used. This board definition currently targets and has been
 tested with
 - [the LiteX SoC generator, revision
-  444a605dea](https://github.com/enjoy-digital/litex/tree/444a605deae6a561dbe2c49bf3062eae6f3cd887)
+  4092180662](https://github.com/enjoy-digital/litex/tree/4092180662ec62cf28b9283a020f1ff7f0892c19)
 - using the included [target
-  file](https://github.com/enjoy-digital/litex/blob/444a605deae6a561dbe2c49bf3062eae6f3cd887/litex/boards/targets/arty.py)
-- built around a VexRiscv-CPU
+  file](https://github.com/enjoy-digital/litex/blob/4092180662ec62cf28b9283a020f1ff7f0892c19/litex/boards/targets/arty.py)
+- built around a VexRiscv-CPU with PMP, hardware multiplication and
+  compressed instruction support
 - along with the following configuration options:
 
   ```
   --uart-baudrate=1000000
-  --cpu-variant=full
+  --cpu-variant=tock+secure+imc
   --csr-data-width=32
   --timer-uptime
   --integrated-rom-size=0xb000
   --with-ethernet
   ```
 
+The `tock+secure+imc` is a custom VexRiscv CPU variant, based on the
+build infrastructure in
+[pythondata-cpu-vexriscv](https://github.com/litex-hub/pythondata-cpu-vexriscv),
+using a
+[patch](https://github.com/lschuermann/tock-litex/blob/master/pkgs/pythondata-cpu-vexriscv/0001-Add-TockSecureIMC-cpu-variant.patch)
+to introduce a CPU with physical memory protection, hardware
+multiplication and compressed instruction support (such that it is
+compatible with the `rv32imc` arch).
+
+Prebuilt and tested bitstreams (including the generated VexRiscv CPU
+Verilog files) can be obtained from the [Tock on LiteX companion
+repository
+releases](https://github.com/lschuermann/tock-litex/releases/). The
+current board definition has been verified to work with [release
+2020122201](https://github.com/lschuermann/tock-litex/releases/tag/2020122201). The
+bitstream for this board is located in `arty_a7-35t.zip` under
+`gateware/arty.bin`.
+
 Many bitstream customizations can be represented in the Tock board by
 simply changing the variables in `src/litex_generated.rs`. To support
 a different set of FPGA cores and perform further modifications, the
@@ -35,20 +54,14 @@ a different set of FPGA cores and perform further modifications, the
 Please note
 -----------
 
-This board is still in development. The memory protection (PMP)
-mechanism is not yet integrated into the VexRiscv core and more
-peripherals require drivers. Nonetheless, the Tock kernel works and
-can run multiple userspace applications.
-
-The following on-board components and cores are supported:
+This board is still in development. The following on-board components
+and cores are supported:
 - [X] Timer (with uptime support)
 - [X] UART output via USB-FTDI
 - [X] Green onboard LEDs
 - [X] 100MBit/s Ethernet MAC
 
 The following components and cores require porting:
-- [ ] Memory protection (PMP) support in the VexRiscv CPU ([upstream
-      PR](https://github.com/SpinalHDL/VexRiscv/pull/147))
 - [ ] GPIO Interface
 - [ ] Buttons and Switches
 - [ ] RGB LEDs

diff --git a/boards/litex/sim/README.md b/boards/litex/sim/README.md
@@ -10,16 +10,16 @@ differ significantly depending on the release and configuration
 options used. This board definition currently targets and has been
 tested with
 - [the LiteX SoC generator, revision
-  444a605dea](https://github.com/enjoy-digital/litex/tree/444a605deae6a561dbe2c49bf3062eae6f3cd887)
-- using the included [lx_sim.py](https://github.com/enjoy-digital/litex/blob/444a605deae6a561dbe2c49bf3062eae6f3cd887/litex/tools/litex_sim.py)
+  444a605dea](https://github.com/enjoy-digital/litex/tree/4092180662ec62cf28b9283a020f1ff7f0892c19)
+- using the included [lx_sim.py](https://github.com/enjoy-digital/litex/blob/4092180662ec62cf28b9283a020f1ff7f0892c19/litex/tools/litex_sim.py)
 - built around a VexRiscv-CPU
 - featuring a TIMER0 with 64-bit wide hardware uptime
 - along with the following configuration options:
 
   ```
   --csr-data-width=32
   --integrated-rom-size=1048576
-  --cpu-variant=full
+  --cpu-variant=secure
   --with-ethernet
   --rom-init $PATH_TO_TOCK_BINARY
   ```
@@ -30,23 +30,6 @@ a different set of FPGA cores and perform further modifications, the
 `src/main.rs` file will have to be modified.
 
 
-Please note
------------
-
-This board is still in development. The memory protection (PMP)
-mechanism is not yet integrated into the VexRiscv core. Nonetheless,
-the Tock kernel works and can run multiple userspace applications.
-
-The following on-board components and cores are supported:
-- [X] Timer (with uptime support)
-- [X] UART console output
-- [X] Ethernet MAC
-
-The following components and cores require porting:
-- [ ] Memory protection (PMP) support in the VexRiscv CPU ([upstream
-      PR](https://github.com/SpinalHDL/VexRiscv/pull/147))
-
-
 Building the SoC / Programming the FPGA
 ---------------------------------------
 

diff --git a/chips/litex_vexriscv/src/chip.rs b/chips/litex_vexriscv/src/chip.rs
@@ -15,14 +15,16 @@ use crate::interrupt_controller::VexRiscvInterruptController;
 /// accessible to the raw interrupt handler functions
 static mut INTERRUPT_CONTROLLER: VexRiscvInterruptController = VexRiscvInterruptController::new();
 
-// TODO: Actually implement the PMP
-PMPConfigMacro!(4);
+// The VexRiscv "Secure" variant of
+// [pythondata-cpu-vexriscv](https://github.com/litex-hub/pythondata-cpu-vexriscv)
+// has 16 PMP slots
+PMPConfigMacro!(16);
 
 pub struct LiteXVexRiscv<A: 'static + Alarm<'static>, I: 'static + InterruptService<()>> {
     soc_identifier: &'static str,
     userspace_kernel_boundary: SysCall,
     interrupt_controller: &'static VexRiscvInterruptController,
-    _pmp: PMP,
+    pmp: PMP,
     scheduler_timer: kernel::VirtualSchedulerTimer<A>,
     interrupt_service: &'static I,
 }
@@ -37,7 +39,7 @@ impl<A: 'static + Alarm<'static>, I: 'static + InterruptService<()>> LiteXVexRis
             soc_identifier,
             userspace_kernel_boundary: SysCall::new(),
             interrupt_controller: &INTERRUPT_CONTROLLER,
-            _pmp: PMP::new(),
+            pmp: PMP::new(),
             scheduler_timer: kernel::VirtualSchedulerTimer::new(alarm),
             interrupt_service,
         }
@@ -60,15 +62,13 @@ impl<A: 'static + Alarm<'static>, I: 'static + InterruptService<()>> LiteXVexRis
 impl<A: 'static + Alarm<'static>, I: 'static + InterruptService<()>> kernel::Chip
     for LiteXVexRiscv<A, I>
 {
-    // type MPU = PMP;
-    type MPU = ();
+    type MPU = PMP;
     type UserspaceKernelBoundary = SysCall;
     type SchedulerTimer = kernel::VirtualSchedulerTimer<A>;
     type WatchDog = ();
 
     fn mpu(&self) -> &Self::MPU {
-        //&self.pmp
-        &()
+        &self.pmp
     }
 
     fn scheduler_timer(&self) -> &Self::SchedulerTimer {