Initial support for SweRV EH1 and SweRVolf #2481

alistair23 · 2021-03-12T13:36:00Z

Pull Request Overview

This PR adds support for running Tock on the SweRVolf EH1 Verilator simulator.

This is useful as we can run a RISC-V Tock model fully in software by just using the make scripts. My plan is to use this in CI eventually as well (as long as it isn't too slow).

SweRV EH1

The Western Digital SweRV Core EH1 is a 32-bit, 2-way superscalar, 9 stage pipeline core.

The SweRV Cores will be used in a variety of Western Digital products in the near future. All three cores have been open sourced in CHIPS Alliance github. CHIPS Alliance is an organization that develops open source hardware and open source software design tools. It is a barrier free, collaborative environment which lowers the cost of RTL development. The SweRV Core EH1 is available at https://github.com/chipsalliance/Cores-SweRV

From: https://www.westerndigital.com/company/innovations/risc-v

SweRVolf

SweRVolf is a FuseSoC-based SoC for the SweRV RISC-V core.

New Platform Checklist

Hardware is widely available. (It's a simulation!)
[X I can support the platform, which includes release testing for the platform, at least initially.
Basic features are implemented:
- Console, including debug!() and userspace printf().
- Timers.
- GPIO with interrupts. (There isn't really a GPIO)

Testing Strategy

Running on the SweRVolf EH1 simulation.

TODO or Help Wanted

Documentation Updated

Updated the relevant files in /docs, or no updates are required.

Formatting

Ran make prepush.

alevy · 2021-03-12T16:33:51Z

A very initial review, just trying to run this locally:

Can you please add .gitignores for all the build artifacts? For me these are:
- binary.hex
- build/
- fusesoc.conf
- fusesoc_libraries/
- makehex.py
The board builds and the simulator runs for me, but there is no output after "Releasing reset" after a few minutes of pinning one of my CPUs (no worries, though, I have plenty of those).
I have no idea why the size tool is borking on the build...

hudson-ayers · 2021-03-12T17:56:26Z

the size tool fails whenever a new board is added, because it fails when trying to build the board on current master. It won't block merging though

alistair23 · 2021-03-12T17:57:59Z

I have updated the .gitignore.

Strange, I'm not sure why it's not working. I see prints within about 20 seconds

alistair23 · 2021-03-12T17:58:16Z

Do you have a new enough version of Verilator?

alevy · 2021-03-12T19:06:30Z

Do you have a new enough version of Verilator?

you tell me!

Verilator 4.108 2021-01-10 rev v4.106-158-g484b76e5b

In any case, it's probably an issue with my setup, just flagging it. Since obviously you won't be able to reproduce (it's working for you), we can maybe sync online to try and resolve.

alistair23 · 2021-03-12T19:12:05Z

That looks right. That's strange. I'm on Slack to help debug if you want (or Matrix :) )

boards/swervolf/src/io.rs

chips/swerv/src/eh1_pic.rs

chips/swervolf-eh1/src/syscon.rs

The SweRV Cores will be used in a variety of Western Digital products in the near future. All three cores have been open sourced in CHIPS Alliance github. CHIPS Alliance is an organization that develops open source hardware and open source software design tools. It is a barrier free, collaborative environment which lowers the cost of RTL development. This commit adds initial support for the SweRV chips, with the EH1 PIC. Signed-off-by: Alistair Francis <[email protected]>

Signed-off-by: Alistair Francis <[email protected]>

alistair23 · 2021-03-15T23:04:54Z

@hudson-ayers Fixed your requests

hudson-ayers · 2021-03-15T23:13:58Z

I can confirm that I see prints on my machine (Ubuntu 20.04, only thing I changed was running sudo apt install verilator instead of pacman). Very cool!

Can you add the new platform checklist to the PR description? It seems that this PR does not support GPIO, which maybe is fine given it is meant to be used primarily as a simulation platform anyway, but wanted to flag that for discussion.

alevy · 2021-03-16T03:08:43Z

I can confirm that I see prints on my machine

I must be losing my edge

alevy · 2021-03-16T03:51:10Z

Works for me as well in a Ubuntu container:

Loading RAM contents from /tock/boards/swervolf/binary.hex
Releasing reset
SweRVolf initialisation complete.
Entering main loop

So this is definitely a toolchain thing, hrm....

alevy · 2021-03-16T05:16:34Z

And frustratingly, I'm able to run the example .vh (hex) files in the fusesoc_libraries repo (e.g. zephyr_hello) and get output.

The only difference I can identify between my working Ubuntu version and non-working NixOS version is that on Ubuntu I wasn't using Python's venv to install/use fusesoc while on NixOS I am.

Tested now with several versions of verilator (default on NixOS is more recent than on Ubuntu), including exactly the one on Ubuntu. I have no clue what might be different. Maybe another NixOS user (@lschuermann?) or a Mac user (for some more toolchain diversity) can try and get this working?

hudson-ayers · 2021-03-16T05:44:03Z

The only difference I can identify between my working Ubuntu version and non-working NixOS version is that on Ubuntu I wasn't using Python's venv to install/use fusesoc while on NixOS I am.

I also used venv, though I hope that would not make a difference

alistair23 · 2021-03-16T13:58:48Z

I updated the description with the checklist.

As for the Nix problem I'm not really sure what to do. Maybe file an issue with FuseSoC?

boards/swervolf/README.md

lschuermann

Looks pretty good. Great to see another FPGA / Verilated board in Tock! I think this is reasonably similar to what LiteX can do, so we can probably use all CI infrastructure with both of them! :)

Outlined some minor change requests. Edit: ugh, looks like the GitHub UI bugged out again and lost my review comments.

.gitignore

boards/swervolf/Makefile

SweRVolf is a FuseSoC-based SoC for the SweRV RISC-V core. This is the first commit of the SweRVolf FuseSoC based board. Signed-off-by: Alistair Francis <[email protected]>

Signed-off-by: Alistair Francis <[email protected]>

boards/swervolf/README.md

lschuermann · 2021-03-16T20:10:58Z

boards/swervolf/README.md

+++ b/arch/rv32i/src/lib.rs
+@@ -88,7 +88,7 @@ pub extern "C" fn _start() {
+ /// This moves the data segment from flash to RAM and zeros out the BSS section.
+ pub unsafe fn init_memory() {


Just commenting so that we're aware #2461 is in last-call and this documentation might be outdated very soon.

alevy

I don't really have much to add here. I'm able to build and run the simulator in a Ubuntu docker container, but not natively in NixOS (I can build the board but the simulator just hangs)---a bummer, since it means realistically I won't test it and also Nix is our best documentation (the Makefiles are also good for general tools, but not board specific ones) of which specific versions of different tools in the chain actually work. I am, conversely able to run pre-compiled bare metal example binaries from the fusesoc repo, so it's not as though the toolchain is entirely broken on my end.

I'm fine with merging this. It's about the state of Open titan in terms of runnability (some people seem to be able to) and if I hadn't happened to try it out, we would have likely merged it without waiting for my comment.

bradjc · 2021-03-22T16:26:36Z

bors r+

bors · 2021-03-22T17:23:55Z

Build succeeded:

alistair23 force-pushed the alistair/swervolf branch from 16bd137 to 2542b01 Compare March 12, 2021 17:57

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hudson-ayers reviewed Mar 15, 2021

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alistair23 added 2 commits March 15, 2021 19:00

chips/swervolf-eh1: Initial commit of SweRVolf Chip

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Signed-off-by: Alistair Francis <[email protected]>

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lschuermann reviewed Mar 16, 2021

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boards/swervolf: Initial commit

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SweRVolf is a FuseSoC-based SoC for the SweRV RISC-V core. This is the first commit of the SweRVolf FuseSoC based board. Signed-off-by: Alistair Francis <[email protected]>

chips/swerv: Use custom CSRs and remove inline assembly

477d971

Signed-off-by: Alistair Francis <[email protected]>

alistair23 dismissed hudson-ayers’s stale review via 44cb421 March 16, 2021 20:07

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alistair23 requested a review from hudson-ayers March 17, 2021 13:59

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bradjc approved these changes Mar 19, 2021

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bradjc requested a review from alevy March 22, 2021 14:35

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bors bot merged commit 95910db into tock:master Mar 22, 2021

alistair23 deleted the alistair/swervolf branch March 22, 2021 18:18

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Initial support for SweRV EH1 and SweRVolf #2481

Initial support for SweRV EH1 and SweRVolf #2481

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Pull Request Overview

SweRV EH1

SweRVolf

New Platform Checklist

Testing Strategy

TODO or Help Wanted

Documentation Updated

Formatting

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alevy commented Mar 12, 2021

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hudson-ayers commented Mar 12, 2021

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