SweRVolf: Add support for the platform timers #2499
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Signed-off-by: Alistair Francis <[email protected]>
The RISC-V spec specifies that bits 16 and above are avaliable for custom implementations. To allow chips to use these bits let's specify them in the register bitfield. Signed-off-by: Alistair Francis <[email protected]>
Signed-off-by: Alistair Francis <[email protected]>
Signed-off-by: Alistair Francis <[email protected]>
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For earlgrey, I recall we used a CONFIG option to set a different prescalar based on whether the chip was running on an FPGA or in verilator. Do we need something like that here? |
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I don't have the FPGA board so I haven't tested this on the FPGA. The Tock board readme only talks about the simulation. Apparently the FPGA and simulation have the same frequency though (if I'm reading the system verilog correctly). |
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I think the issue was that using the same frequency in verilator made running anything meaningful unbearably slow. But if this seems to work fine in practice, sounds good to me. |
bradjc
approved these changes
Mar 25, 2021
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Pull Request Overview
This PR adds support for the two internal timers. This means we now don't have to mux the RISC-V mtimer.
Testing Strategy
Running in simulation.
TODO or Help Wanted
Documentation Updated
/docs, or no updates are required.Formatting
make prepush.