nrf52: adc: Add highspeed implementation. #3453
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lschuermann
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May 31, 2023
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lschuermann
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ppannuto
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Jun 28, 2023
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I moved the default VREF setting up a level so that some other caller of adc::new() could set something else if needed. @bradjc I'll leave this for you to click merge in case there was some reason you'd not done that I didn't see.
Not all nRF52840 boards use 3.3 V for VDD.
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Rebased. Looks good to me. |
ppannuto
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Pull Request Overview
This pull request adds an implementation of
hil::adc::AdcHighSpeedfor the nRF52.The main issue is that the internal clock divider for the SAADC only allows dividing a 16 MHz clock by a value in the range 80 to 2047 (so 8 kHz to 200 kHz sampling). So there is a limited range of possible frequencies. This is also why it's hard to implement continuous sampling.
This also adds VDD detection to the calibrate step, since the nRF52840dk uses a 3V reference and I couldn't figure out why my ADC readings were wrong.
Testing Strategy
Using the libtock-c adc app.
TODO or Help Wanted
How good of a driver do we need?
Documentation Updated
/docs, or no updates are required.Formatting
make prepush.