Haskell to VHDL/Verilog/SystemVerilog compiler
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Sep 9, 2025 - Haskell
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hardware-description-language
Verilog is a widely-used hardware description language (HDL) that enables designers to model, simulate, and synthesize digital circuits. It provides a text-based format for specifying the structure and behavior of electronic systems, making it easier to design complex hardware components such as microprocessors, memory, and communication devices.
Here are 272 public repositories matching this topic...
Haskell to VHDL/Verilog/SystemVerilog compiler
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Sep 9, 2025 - Haskell
Hardware Description Languages
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Jul 14, 2025
Hardware Description Languages
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Jul 14, 2025
A C-like hardware description language (HDL) adding high level synthesis(HLS)-like automatic pipelining as a language construct/compiler feature.
python c fpga hls hardware vhdl pipelines open-source-hardware high-level-synthesis hardware-description-language fpga-accelerators fpga-acceleration fpga-programming hardware-description
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Sep 7, 2025 - VHDL
A C-like hardware description language (HDL) adding high level synthesis(HLS)-like automatic pipelining as a language construct/compiler feature.
python c fpga hls hardware vhdl pipelines open-source-hardware high-level-synthesis hardware-description-language fpga-accelerators fpga-acceleration fpga-programming hardware-description
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Sep 7, 2025 - VHDL
一篇全面的 Bluespec SystemVerilog (BSV) 中文教程，介绍了BSV的调度、FIFO数据流、多态等高级特性，展示了BSV相比于传统Verilog开发的优势。
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Sep 15, 2023 - Bluespec
Implementation of a Tensor Processing Unit for embedded systems and the IoT.
linux iot fpga zynq tensorflow assembly vhdl embedded-systems internet-of-things hardware-architectures verilog xilinx vivado tensor hardware-designs hardware-acceleration fpga-accelerator hardware-description-language ip-core tpu
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Jan 5, 2019 - VHDL
Implementation of a Tensor Processing Unit for embedded systems and the IoT.
linux iot fpga zynq tensorflow assembly vhdl embedded-systems internet-of-things hardware-architectures verilog xilinx vivado tensor hardware-designs hardware-acceleration fpga-accelerator hardware-description-language ip-core tpu
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Jan 5, 2019 - VHDL
SystemRDL 2.0 language compiler front-end
asic fpga eda csr registers systemrdl register-descriptions systemrdl-compiler hardware-description-language design-automation register-description-language
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Aug 1, 2025 - C++
SystemRDL 2.0 language compiler front-end
asic fpga eda csr registers systemrdl register-descriptions systemrdl-compiler hardware-description-language design-automation register-description-language
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Aug 1, 2025 - C++
Fearless hardware design
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Aug 20, 2025 - Verilog
A core language for rule-based hardware design 🦑
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Jun 11, 2025 - Rocq Prover
A core language for rule-based hardware design 🦑
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Jun 11, 2025 - Rocq Prover
A Platform for High-Level Parametric Hardware Specification and its Modular Verification
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Jul 14, 2025 - Rocq Prover
A Platform for High-Level Parametric Hardware Specification and its Modular Verification
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Jul 14, 2025 - Rocq Prover
Control and status register code generator toolchain
asic fpga eda verilog csr command-line-tool systemverilog uvm registers axi amba apb register-descriptions systemrdl-compiler hardware-description-language uvm-register-model
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Aug 27, 2025 - Python
Control and status register code generator toolchain
asic fpga eda verilog csr command-line-tool systemverilog uvm registers axi amba apb register-descriptions systemrdl-compiler hardware-description-language uvm-register-model
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Aug 27, 2025 - Python
ACT hardware description language and core tools.
language eda circuit-simulator cad dataflow chp dataflow-programming prs hdl vlsi hardware-description-language production-rules design-automation asynchronous-circuits vlsi-cad asynchronous-vlsi communicating-hardware-processes
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Aug 21, 2025 - C++
ACT hardware description language and core tools.
language eda circuit-simulator cad dataflow chp dataflow-programming prs hdl vlsi hardware-description-language production-rules design-automation asynchronous-circuits vlsi-cad asynchronous-vlsi communicating-hardware-processes
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Aug 21, 2025 - C++
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