risc-v-architecture

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Here are 9 public repositories matching this topic...

jesse-r-s-hines / RISC-V-Graphical-Datapath-Simulator

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A web-based graphical simulator of a simple 32-bit, single-cycle implementation of RISC-V

education riscv risc-v riscv32 risc-v-assembly risc-v-architecture risc-v-simulator

Updated Mar 16, 2025
TypeScript

Fahad-Habib / RISC-V-Single-Cycle-Processor

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Single Cycle Processor written in SystemVerilog for executing machine code of RISC-V ISA

verilog systemverilog risc-v digital-system-design single-cycle-processor risc-v-architecture

Updated Apr 23, 2023
SystemVerilog

tvlad1234 / rv32adventure

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Becoming acquainted with the RISC-V ISA by writing an emulator

emulator vm risc-v rv32i rv32im risc-v-architecture

Updated Sep 13, 2023
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Fahad-Habib / RISC-V-Pipelined-Processor-with-CSR

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3-stage RISC-V Pipelined Processor with interrupt CSR support

systemverilog risc-v digital-system-design risc-v-assembly risc-v-architecture

Updated Jun 2, 2023
SystemVerilog

RISCeirb / Risc-v-processor

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Processor RISC-V and application

pipeline processor assembly riscv modelsim pipeline-processor risc-v ufsm enseirb-matmeca branch-predictor enseirb monocycle-processor risc-v-assembly assembly-risc risc-v-architecture risc-v-architectures assembly-risc-v

Updated Aug 30, 2024
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HafizMutahirAhmed / RV32I-5-Stage-Processor

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A fully pipelined 5-stage RV32I processor implemented in SystemVerilog. This design models instruction-level parallelism with forwarding and hazard detection, and passes all RISCOF compliance tests for the RV32I base ISA.

processor-architecture fpga processor riscv rtl vivado systemverilog hdl risc-v rv32i verilator processor-design fpga-programming arty-a7 risc-v-architecture five-stage riscof pipelined-processor rv32i-processor

Updated Jul 27, 2025
SystemVerilog

Adarsh-Kumar-Nayak / RISC-V-single-cycle-processor-Sum-of-n-numbers

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This project provides an insight into the internal verification of a 32-bit single cycle processor that implements the Reduced Instruction Set-V and displayed on seven segment on Basys3 FPGA board. The hardware structures were realized using Verilog Hardware Description Language.

processor-architecture fpga processor verilog instruction-set-architecture risc-v fpga-board 7-segment-display risc-v-architecture