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Merge pull request #41 from torvalds/master
Sync up with Linus
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‎Documentation/DocBook/kgdb.tmpl‎

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@@ -197,6 +197,7 @@
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may be configured as a kernel built-in or a kernel loadable module.
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You can only make use of <constant>kgdbwait</constant> and early
199199
debugging if you build kgdboc into the kernel as a built-in.
200+
</para>
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<para>Optionally you can elect to activate kms (Kernel Mode
201202
Setting) integration. When you use kms with kgdboc and you have a
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video driver that has atomic mode setting hooks, it is possible to
@@ -206,7 +207,6 @@
206207
crashes or doing analysis of memory with kdb while allowing the
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full graphics console applications to run.
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</para>
209-
</para>
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<sect2 id="kgdbocArgs">
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<title>kgdboc arguments</title>
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<para>Usage: <constant>kgdboc=[kms][[,]kbd][[,]serial_device][,baud]</constant></para>
@@ -284,7 +284,6 @@
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</listitem>
285285
</orderedlist>
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</para>
287-
</sect3>
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<para>NOTE: Kgdboc does not support interrupting the target via the
289288
gdb remote protocol. You must manually send a sysrq-g unless you
290289
have a proxy that splits console output to a terminal program.
@@ -305,6 +304,7 @@
305304
as well as on the initial connect, or to use a debugger proxy that
306305
allows an unmodified gdb to do the debugging.
307306
</para>
307+
</sect3>
308308
</sect2>
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</sect1>
310310
<sect1 id="kgdbwait">
@@ -350,12 +350,12 @@
350350
</para>
351351
</listitem>
352352
</orderedlist>
353+
</para>
353354
<para>IMPORTANT NOTE: You cannot use kgdboc + kgdbcon on a tty that is an
354355
active system console. An example of incorrect usage is <constant>console=ttyS0,115200 kgdboc=ttyS0 kgdbcon</constant>
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</para>
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<para>It is possible to use this option with kgdboc on a tty that is not a system console.
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</para>
358-
</para>
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</sect1>
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<sect1 id="kgdbreboot">
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<title>Run time parameter: kgdbreboot</title>

‎Documentation/clk.txt‎

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@@ -73,6 +73,8 @@ the operations defined in clk.h:
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unsigned long *parent_rate);
7474
long (*determine_rate)(struct clk_hw *hw,
7575
unsigned long rate,
76+
unsigned long min_rate,
77+
unsigned long max_rate,
7678
unsigned long *best_parent_rate,
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struct clk_hw **best_parent_clk);
7880
int (*set_parent)(struct clk_hw *hw, u8 index);

‎Documentation/device-mapper/dm-crypt.txt‎

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@@ -51,7 +51,7 @@ Parameters: <cipher> <key> <iv_offset> <device path> \
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Otherwise #opt_params is the number of following arguments.
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5353
Example of optional parameters section:
54-
1 allow_discards
54+
3 allow_discards same_cpu_crypt submit_from_crypt_cpus
5555

5656
allow_discards
5757
Block discard requests (a.k.a. TRIM) are passed through the crypt device.
@@ -63,6 +63,19 @@ allow_discards
6363
used space etc.) if the discarded blocks can be located easily on the
6464
device later.
6565

66+
same_cpu_crypt
67+
Perform encryption using the same cpu that IO was submitted on.
68+
The default is to use an unbound workqueue so that encryption work
69+
is automatically balanced between available CPUs.
70+
71+
submit_from_crypt_cpus
72+
Disable offloading writes to a separate thread after encryption.
73+
There are some situations where offloading write bios from the
74+
encryption threads to a single thread degrades performance
75+
significantly. The default is to offload write bios to the same
76+
thread because it benefits CFQ to have writes submitted using the
77+
same context.
78+
6679
Example scripts
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===============
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LUKS (Linux Unified Key Setup) is now the preferred way to set up disk

‎Documentation/devicetree/bindings/clock/exynos7-clock.txt‎

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@@ -34,6 +34,8 @@ Required Properties for Clock Controller:
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- "samsung,exynos7-clock-peris"
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- "samsung,exynos7-clock-fsys0"
3636
- "samsung,exynos7-clock-fsys1"
37+
- "samsung,exynos7-clock-mscl"
38+
- "samsung,exynos7-clock-aud"
3739

3840
- reg: physical base address of the controller and the length of
3941
memory mapped region.
@@ -53,6 +55,7 @@ Input clocks for top0 clock controller:
5355
- dout_sclk_bus1_pll
5456
- dout_sclk_cc_pll
5557
- dout_sclk_mfc_pll
58+
- dout_sclk_aud_pll
5659

5760
Input clocks for top1 clock controller:
5861
- fin_pll
@@ -76,6 +79,14 @@ Input clocks for peric1 clock controller:
7679
- sclk_uart1
7780
- sclk_uart2
7881
- sclk_uart3
82+
- sclk_spi0
83+
- sclk_spi1
84+
- sclk_spi2
85+
- sclk_spi3
86+
- sclk_spi4
87+
- sclk_i2s1
88+
- sclk_pcm1
89+
- sclk_spdif
7990

8091
Input clocks for peris clock controller:
8192
- fin_pll
@@ -91,3 +102,7 @@ Input clocks for fsys1 clock controller:
91102
- dout_aclk_fsys1_200
92103
- dout_sclk_mmc0
93104
- dout_sclk_mmc1
105+
106+
Input clocks for aud clock controller:
107+
- fin_pll
108+
- fout_aud_pll

‎Documentation/devicetree/bindings/clock/nvidia,tegra124-car.txt‎

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@@ -1,4 +1,4 @@
1-
NVIDIA Tegra124 Clock And Reset Controller
1+
NVIDIA Tegra124 and Tegra132 Clock And Reset Controller
22

33
This binding uses the common clock binding:
44
Documentation/devicetree/bindings/clock/clock-bindings.txt
@@ -7,14 +7,16 @@ The CAR (Clock And Reset) Controller on Tegra is the HW module responsible
77
for muxing and gating Tegra's clocks, and setting their rates.
88

99
Required properties :
10-
- compatible : Should be "nvidia,tegra124-car"
10+
- compatible : Should be "nvidia,tegra124-car" or "nvidia,tegra132-car"
1111
- reg : Should contain CAR registers location and length
1212
- clocks : Should contain phandle and clock specifiers for two clocks:
1313
the 32 KHz "32k_in", and the board-specific oscillator "osc".
1414
- #clock-cells : Should be 1.
1515
In clock consumers, this cell represents the clock ID exposed by the
16-
CAR. The assignments may be found in header file
17-
<dt-bindings/clock/tegra124-car.h>.
16+
CAR. The assignments may be found in the header files
17+
<dt-bindings/clock/tegra124-car-common.h> (which covers IDs common
18+
to Tegra124 and Tegra132) and <dt-bindings/clock/tegra124-car.h>
19+
(for Tegra124-specific clocks).
1820
- #reset-cells : Should be 1.
1921
In clock consumers, this cell represents the bit number in the CAR's
2022
array of CLK_RST_CONTROLLER_RST_DEVICES_* registers.

‎Documentation/devicetree/bindings/clock/qcom,lcc.txt‎

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1+
Qualcomm LPASS Clock & Reset Controller Binding
2+
------------------------------------------------
3+
4+
Required properties :
5+
- compatible : shall contain only one of the following:
6+
7+
"qcom,lcc-msm8960"
8+
"qcom,lcc-apq8064"
9+
"qcom,lcc-ipq8064"
10+
11+
- reg : shall contain base register location and length
12+
- #clock-cells : shall contain 1
13+
- #reset-cells : shall contain 1
14+
15+
Example:
16+
clock-controller@28000000 {
17+
compatible = "qcom,lcc-ipq8064";
18+
reg = <0x28000000 0x1000>;
19+
#clock-cells = <1>;
20+
#reset-cells = <1>;
21+
};

‎Documentation/devicetree/bindings/clock/qoriq-clock.txt‎

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Original file line numberDiff line numberDiff line change
@@ -1,6 +1,6 @@
1-
* Clock Block on Freescale CoreNet Platforms
1+
* Clock Block on Freescale QorIQ Platforms
22

3-
Freescale CoreNet chips take primary clocking input from the external
3+
Freescale qoriq chips take primary clocking input from the external
44
SYSCLK signal. The SYSCLK input (frequency) is multiplied using
55
multiple phase locked loops (PLL) to create a variety of frequencies
66
which can then be passed to a variety of internal logic, including
@@ -29,6 +29,7 @@ Required properties:
2929
* "fsl,t4240-clockgen"
3030
* "fsl,b4420-clockgen"
3131
* "fsl,b4860-clockgen"
32+
* "fsl,ls1021a-clockgen"
3233
Chassis clock strings include:
3334
* "fsl,qoriq-clockgen-1.0": for chassis 1.0 clocks
3435
* "fsl,qoriq-clockgen-2.0": for chassis 2.0 clocks

‎Documentation/devicetree/bindings/clock/renesas,cpg-mstp-clocks.txt‎

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@@ -11,6 +11,7 @@ Required Properties:
1111

1212
- compatible: Must be one of the following
1313
- "renesas,r7s72100-mstp-clocks" for R7S72100 (RZ) MSTP gate clocks
14+
- "renesas,r8a73a4-mstp-clocks" for R8A73A4 (R-Mobile APE6) MSTP gate clocks
1415
- "renesas,r8a7740-mstp-clocks" for R8A7740 (R-Mobile A1) MSTP gate clocks
1516
- "renesas,r8a7779-mstp-clocks" for R8A7779 (R-Car H1) MSTP gate clocks
1617
- "renesas,r8a7790-mstp-clocks" for R8A7790 (R-Car H2) MSTP gate clocks

‎Documentation/devicetree/bindings/clock/renesas,r8a73a4-cpg-clocks.txt‎

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@@ -0,0 +1,33 @@
1+
* Renesas R8A73A4 Clock Pulse Generator (CPG)
2+
3+
The CPG generates core clocks for the R8A73A4 SoC. It includes five PLLs
4+
and several fixed ratio dividers.
5+
6+
Required Properties:
7+
8+
- compatible: Must be "renesas,r8a73a4-cpg-clocks"
9+
10+
- reg: Base address and length of the memory resource used by the CPG
11+
12+
- clocks: Reference to the parent clocks ("extal1" and "extal2")
13+
14+
- #clock-cells: Must be 1
15+
16+
- clock-output-names: The names of the clocks. Supported clocks are "main",
17+
"pll0", "pll1", "pll2", "pll2s", "pll2h", "z", "z2", "i", "m3", "b",
18+
"m1", "m2", "zx", "zs", and "hp".
19+
20+
21+
Example
22+
-------
23+
24+
cpg_clocks: cpg_clocks@e6150000 {
25+
compatible = "renesas,r8a73a4-cpg-clocks";
26+
reg = <0 0xe6150000 0 0x10000>;
27+
clocks = <&extal1_clk>, <&extal2_clk>;
28+
#clock-cells = <1>;
29+
clock-output-names = "main", "pll0", "pll1", "pll2",
30+
"pll2s", "pll2h", "z", "z2",
31+
"i", "m3", "b", "m1", "m2",
32+
"zx", "zs", "hp";
33+
};

‎Documentation/devicetree/bindings/clock/renesas,rcar-gen2-cpg-clocks.txt‎

Lines changed: 8 additions & 4 deletions
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@@ -8,15 +8,18 @@ Required Properties:
88
- compatible: Must be one of
99
- "renesas,r8a7790-cpg-clocks" for the r8a7790 CPG
1010
- "renesas,r8a7791-cpg-clocks" for the r8a7791 CPG
11+
- "renesas,r8a7793-cpg-clocks" for the r8a7793 CPG
1112
- "renesas,r8a7794-cpg-clocks" for the r8a7794 CPG
1213
- "renesas,rcar-gen2-cpg-clocks" for the generic R-Car Gen2 CPG
1314

1415
- reg: Base address and length of the memory resource used by the CPG
1516

16-
- clocks: Reference to the parent clock
17+
- clocks: References to the parent clocks: first to the EXTAL clock, second
18+
to the USB_EXTAL clock
1719
- #clock-cells: Must be 1
1820
- clock-output-names: The names of the clocks. Supported clocks are "main",
19-
"pll0", "pll1", "pll3", "lb", "qspi", "sdh", "sd0", "sd1" and "z"
21+
"pll0", "pll1", "pll3", "lb", "qspi", "sdh", "sd0", "sd1", "z", "rcan", and
22+
"adsp"
2023

2124

2225
Example
@@ -26,8 +29,9 @@ Example
2629
compatible = "renesas,r8a7790-cpg-clocks",
2730
"renesas,rcar-gen2-cpg-clocks";
2831
reg = <0 0xe6150000 0 0x1000>;
29-
clocks = <&extal_clk>;
32+
clocks = <&extal_clk &usb_extal_clk>;
3033
#clock-cells = <1>;
3134
clock-output-names = "main", "pll0, "pll1", "pll3",
32-
"lb", "qspi", "sdh", "sd0", "sd1", "z";
35+
"lb", "qspi", "sdh", "sd0", "sd1", "z",
36+
"rcan", "adsp";
3337
};

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