33#define DEBUG_TYPE "aarch64-disassembler"
42#define Success MCDisassembler::Success
43#define Fail MCDisassembler::Fail
44#define SoftFail MCDisassembler::SoftFail
46template <
unsigned RegClassID,
unsigned FirstReg,
unsigned NumRegsInClass>
50 if (RegNo > NumRegsInClass - 1)
54 AArch64MCRegisterClasses[RegClassID].getRegister(RegNo + FirstReg);
68 AArch64MCRegisterClasses[AArch64::GPR64x8ClassRegClassID].getRegister(
74template <
unsigned Min,
unsigned Max>
78 unsigned Reg = (RegNo * 2) + Min;
82 AArch64MCRegisterClasses[AArch64::ZPRRegClassID].getRegister(
Reg);
87template <
unsigned Min,
unsigned Max>
90 const void *Decoder) {
91 unsigned Reg = (RegNo * 2) + Min;
96 AArch64MCRegisterClasses[AArch64::ZPR2RegClassID].getRegister(
Reg);
107 AArch64MCRegisterClasses[AArch64::ZPR_KRegClassID].getRegister(RegNo);
114 const void *Decoder) {
118 AArch64MCRegisterClasses[AArch64::ZPR4RegClassID].getRegister(RegNo * 4);
155 AArch64MCRegisterClasses[AArch64::MPR16RegClassID].getRegister(RegNo);
164 AArch64MCRegisterClasses[AArch64::MPR32RegClassID].getRegister(RegNo);
173 AArch64MCRegisterClasses[AArch64::MPR64RegClassID].getRegister(RegNo);
182 AArch64MCRegisterClasses[AArch64::MPR128RegClassID].getRegister(RegNo);
189 const void *Decoder) {
190 if ((RegNo * 2) > 14)
193 AArch64MCRegisterClasses[AArch64::PPR2RegClassID].getRegister(RegNo * 2);
220 if (ImmVal > (1 << 16))
235 Inst, ImmVal * 4, Addr, Inst.
getOpcode() != AArch64::LDRXl, 0, 0, 4))
287 Inst, Rd, Address, Decoder);
289 Inst, Rn, Address, Decoder);
292 Inst, Rd, Address, Decoder);
294 Inst, Rn, Address, Decoder);
389 unsigned shift = (shiftHi << 6) | shiftLo;
393 case AArch64::ADDWrs:
394 case AArch64::ADDSWrs:
395 case AArch64::SUBWrs:
396 case AArch64::SUBSWrs:
401 case AArch64::ANDWrs:
402 case AArch64::ANDSWrs:
403 case AArch64::BICWrs:
404 case AArch64::BICSWrs:
405 case AArch64::ORRWrs:
406 case AArch64::ORNWrs:
407 case AArch64::EORWrs:
408 case AArch64::EONWrs: {
410 if (shiftLo >> 5 == 1)
420 case AArch64::ADDXrs:
421 case AArch64::ADDSXrs:
422 case AArch64::SUBXrs:
423 case AArch64::SUBSXrs:
428 case AArch64::ANDXrs:
429 case AArch64::ANDSXrs:
430 case AArch64::BICXrs:
431 case AArch64::BICSXrs:
432 case AArch64::ORRXrs:
433 case AArch64::ORNXrs:
434 case AArch64::EORXrs:
435 case AArch64::EONXrs:
459 case AArch64::MOVZWi:
460 case AArch64::MOVNWi:
461 case AArch64::MOVKWi:
462 if (shift & (1U << 5))
467 case AArch64::MOVZXi:
468 case AArch64::MOVNXi:
469 case AArch64::MOVKXi:
475 if (Inst.
getOpcode() == AArch64::MOVKWi ||
497 case AArch64::PRFMui:
501 case AArch64::STRBBui:
502 case AArch64::LDRBBui:
503 case AArch64::LDRSBWui:
504 case AArch64::STRHHui:
505 case AArch64::LDRHHui:
506 case AArch64::LDRSHWui:
507 case AArch64::STRWui:
508 case AArch64::LDRWui:
512 case AArch64::LDRSBXui:
513 case AArch64::LDRSHXui:
514 case AArch64::LDRSWui:
515 case AArch64::STRXui:
516 case AArch64::LDRXui:
520 case AArch64::LDRQui:
521 case AArch64::STRQui:
525 case AArch64::LDRDui:
526 case AArch64::STRDui:
530 case AArch64::LDRSui:
531 case AArch64::STRSui:
535 case AArch64::LDRHui:
536 case AArch64::STRHui:
540 case AArch64::LDRBui:
541 case AArch64::STRBui:
565 case AArch64::LDRSBWpre:
566 case AArch64::LDRSHWpre:
567 case AArch64::STRBBpre:
568 case AArch64::LDRBBpre:
569 case AArch64::STRHHpre:
570 case AArch64::LDRHHpre:
571 case AArch64::STRWpre:
572 case AArch64::LDRWpre:
573 case AArch64::LDRSBWpost:
574 case AArch64::LDRSHWpost:
575 case AArch64::STRBBpost:
576 case AArch64::LDRBBpost:
577 case AArch64::STRHHpost:
578 case AArch64::LDRHHpost:
579 case AArch64::STRWpost:
580 case AArch64::LDRWpost:
581 case AArch64::LDRSBXpre:
582 case AArch64::LDRSHXpre:
583 case AArch64::STRXpre:
584 case AArch64::LDRSWpre:
585 case AArch64::LDRXpre:
586 case AArch64::LDRSBXpost:
587 case AArch64::LDRSHXpost:
588 case AArch64::STRXpost:
589 case AArch64::LDRSWpost:
590 case AArch64::LDRXpost:
591 case AArch64::LDRQpre:
592 case AArch64::STRQpre:
593 case AArch64::LDRQpost:
594 case AArch64::STRQpost:
595 case AArch64::LDRDpre:
596 case AArch64::STRDpre:
597 case AArch64::LDRDpost:
598 case AArch64::STRDpost:
599 case AArch64::LDRSpre:
600 case AArch64::STRSpre:
601 case AArch64::LDRSpost:
602 case AArch64::STRSpost:
603 case AArch64::LDRHpre:
604 case AArch64::STRHpre:
605 case AArch64::LDRHpost:
606 case AArch64::STRHpost:
607 case AArch64::LDRBpre:
608 case AArch64::STRBpre:
609 case AArch64::LDRBpost:
610 case AArch64::STRBpost:
619 case AArch64::PRFUMi:
623 case AArch64::STURBBi:
624 case AArch64::LDURBBi:
625 case AArch64::LDURSBWi:
626 case AArch64::STURHHi:
627 case AArch64::LDURHHi:
628 case AArch64::LDURSHWi:
629 case AArch64::STURWi:
630 case AArch64::LDURWi:
631 case AArch64::LDTRSBWi:
632 case AArch64::LDTRSHWi:
633 case AArch64::STTRWi:
634 case AArch64::LDTRWi:
635 case AArch64::STTRHi:
636 case AArch64::LDTRHi:
637 case AArch64::LDTRBi:
638 case AArch64::STTRBi:
639 case AArch64::LDRSBWpre:
640 case AArch64::LDRSHWpre:
641 case AArch64::STRBBpre:
642 case AArch64::LDRBBpre:
643 case AArch64::STRHHpre:
644 case AArch64::LDRHHpre:
645 case AArch64::STRWpre:
646 case AArch64::LDRWpre:
647 case AArch64::LDRSBWpost:
648 case AArch64::LDRSHWpost:
649 case AArch64::STRBBpost:
650 case AArch64::LDRBBpost:
651 case AArch64::STRHHpost:
652 case AArch64::LDRHHpost:
653 case AArch64::STRWpost:
654 case AArch64::LDRWpost:
655 case AArch64::STLURBi:
656 case AArch64::STLURHi:
657 case AArch64::STLURWi:
658 case AArch64::LDAPURBi:
659 case AArch64::LDAPURSBWi:
660 case AArch64::LDAPURHi:
661 case AArch64::LDAPURSHWi:
662 case AArch64::LDAPURi:
666 case AArch64::LDURSBXi:
667 case AArch64::LDURSHXi:
668 case AArch64::LDURSWi:
669 case AArch64::STURXi:
670 case AArch64::LDURXi:
671 case AArch64::LDTRSBXi:
672 case AArch64::LDTRSHXi:
673 case AArch64::LDTRSWi:
674 case AArch64::STTRXi:
675 case AArch64::LDTRXi:
676 case AArch64::LDRSBXpre:
677 case AArch64::LDRSHXpre:
678 case AArch64::STRXpre:
679 case AArch64::LDRSWpre:
680 case AArch64::LDRXpre:
681 case AArch64::LDRSBXpost:
682 case AArch64::LDRSHXpost:
683 case AArch64::STRXpost:
684 case AArch64::LDRSWpost:
685 case AArch64::LDRXpost:
686 case AArch64::LDAPURSWi:
687 case AArch64::LDAPURSHXi:
688 case AArch64::LDAPURSBXi:
689 case AArch64::STLURXi:
690 case AArch64::LDAPURXi:
694 case AArch64::LDURQi:
695 case AArch64::STURQi:
696 case AArch64::LDRQpre:
697 case AArch64::STRQpre:
698 case AArch64::LDRQpost:
699 case AArch64::STRQpost:
703 case AArch64::LDURDi:
704 case AArch64::STURDi:
705 case AArch64::LDRDpre:
706 case AArch64::STRDpre:
707 case AArch64::LDRDpost:
708 case AArch64::STRDpost:
712 case AArch64::LDURSi:
713 case AArch64::STURSi:
714 case AArch64::LDRSpre:
715 case AArch64::STRSpre:
716 case AArch64::LDRSpost:
717 case AArch64::STRSpost:
721 case AArch64::LDURHi:
722 case AArch64::STURHi:
723 case AArch64::LDRHpre:
724 case AArch64::STRHpre:
725 case AArch64::LDRHpost:
726 case AArch64::STRHpost:
730 case AArch64::LDURBi:
731 case AArch64::STURBi:
732 case AArch64::LDRBpre:
733 case AArch64::STRBpre:
734 case AArch64::LDRBpost:
735 case AArch64::STRBpost:
750 if (IsLoad && IsIndexed && !IsFP && Rn != 31 && Rt == Rn)
768 case AArch64::STLXRW:
769 case AArch64::STLXRB:
770 case AArch64::STLXRH:
780 case AArch64::LDAXRW:
781 case AArch64::LDAXRB:
782 case AArch64::LDAXRH:
789 case AArch64::STLLRW:
790 case AArch64::STLLRB:
791 case AArch64::STLLRH:
792 case AArch64::LDLARW:
793 case AArch64::LDLARB:
794 case AArch64::LDLARH:
798 case AArch64::STLXRX:
804 case AArch64::LDAXRX:
807 case AArch64::LDLARX:
808 case AArch64::STLLRX:
812 case AArch64::STLXPW:
817 case AArch64::LDAXPW:
824 case AArch64::STLXPX:
829 case AArch64::LDAXPX:
842 if ((Opcode == AArch64::LDAXPW || Opcode == AArch64::LDXPW ||
843 Opcode == AArch64::LDAXPX || Opcode == AArch64::LDXPX) &&
860 bool NeedsDisjointWritebackTransfer =
false;
866 case AArch64::LDPXpost:
867 case AArch64::STPXpost:
868 case AArch64::LDPSWpost:
869 case AArch64::LDPXpre:
870 case AArch64::STPXpre:
871 case AArch64::LDPSWpre:
872 case AArch64::LDPWpost:
873 case AArch64::STPWpost:
874 case AArch64::LDPWpre:
875 case AArch64::STPWpre:
876 case AArch64::LDPQpost:
877 case AArch64::STPQpost:
878 case AArch64::LDPQpre:
879 case AArch64::STPQpre:
880 case AArch64::LDPDpost:
881 case AArch64::STPDpost:
882 case AArch64::LDPDpre:
883 case AArch64::STPDpre:
884 case AArch64::LDPSpost:
885 case AArch64::STPSpost:
886 case AArch64::LDPSpre:
887 case AArch64::STPSpre:
888 case AArch64::STGPpre:
889 case AArch64::STGPpost:
890 case AArch64::LDTPpre:
891 case AArch64::LDTPpost:
892 case AArch64::LDTPQpost:
893 case AArch64::LDTPQpre:
894 case AArch64::STTPpost:
895 case AArch64::STTPpre:
896 case AArch64::STTPQpost:
897 case AArch64::STTPQpre:
906 case AArch64::LDPXpost:
907 case AArch64::STPXpost:
908 case AArch64::LDPSWpost:
909 case AArch64::LDPXpre:
910 case AArch64::STPXpre:
911 case AArch64::LDPSWpre:
912 case AArch64::STGPpre:
913 case AArch64::STGPpost:
914 case AArch64::LDTPpost:
915 case AArch64::LDTPpre:
916 case AArch64::STTPpost:
917 case AArch64::STTPpre:
918 NeedsDisjointWritebackTransfer =
true;
920 case AArch64::LDNPXi:
921 case AArch64::STNPXi:
924 case AArch64::LDPSWi:
928 case AArch64::STTNPXi:
929 case AArch64::LDTNPXi:
935 case AArch64::LDPWpost:
936 case AArch64::STPWpost:
937 case AArch64::LDPWpre:
938 case AArch64::STPWpre:
939 NeedsDisjointWritebackTransfer =
true;
941 case AArch64::LDNPWi:
942 case AArch64::STNPWi:
950 case AArch64::LDNPQi:
951 case AArch64::STNPQi:
952 case AArch64::LDPQpost:
953 case AArch64::STPQpost:
956 case AArch64::LDPQpre:
957 case AArch64::STPQpre:
958 case AArch64::LDTPQi:
959 case AArch64::LDTPQpost:
960 case AArch64::LDTPQpre:
961 case AArch64::LDTNPQi:
962 case AArch64::STTPQi:
963 case AArch64::STTPQpost:
964 case AArch64::STTPQpre:
965 case AArch64::STTNPQi:
971 case AArch64::LDNPDi:
972 case AArch64::STNPDi:
973 case AArch64::LDPDpost:
974 case AArch64::STPDpost:
977 case AArch64::LDPDpre:
978 case AArch64::STPDpre:
984 case AArch64::LDNPSi:
985 case AArch64::STNPSi:
986 case AArch64::LDPSpost:
987 case AArch64::STPSpost:
990 case AArch64::LDPSpre:
991 case AArch64::STPSpre:
1004 if (IsLoad && Rt == Rt2)
1009 if (NeedsDisjointWritebackTransfer && Rn != 31 && (Rt == Rn || Rt2 == Rn))
1027 case AArch64::LDRAAwriteback:
1028 case AArch64::LDRABwriteback:
1030 Inst, Rn , Addr, Decoder);
1032 case AArch64::LDRAAindexed:
1033 case AArch64::LDRABindexed:
1043 if (writeback && Rt == Rn && Rn != 31) {
1058 unsigned shift = extend & 0x7;
1065 case AArch64::ADDWrx:
1066 case AArch64::SUBWrx:
1074 case AArch64::ADDSWrx:
1075 case AArch64::SUBSWrx:
1083 case AArch64::ADDXrx:
1084 case AArch64::SUBXrx:
1092 case AArch64::ADDSXrx:
1093 case AArch64::SUBSXrx:
1101 case AArch64::ADDXrx64:
1102 case AArch64::SUBXrx64:
1110 case AArch64::SUBSXrx64:
1111 case AArch64::ADDSXrx64:
1134 if (Inst.
getOpcode() == AArch64::ANDSXri)
1139 Inst, Rd, Addr, Decoder);
1146 if (Inst.
getOpcode() == AArch64::ANDSWri)
1151 Inst, Rd, Addr, Decoder);
1182 case AArch64::MOVIv4i16:
1183 case AArch64::MOVIv8i16:
1184 case AArch64::MVNIv4i16:
1185 case AArch64::MVNIv8i16:
1186 case AArch64::MOVIv2i32:
1187 case AArch64::MOVIv4i32:
1188 case AArch64::MVNIv2i32:
1189 case AArch64::MVNIv4i32:
1192 case AArch64::MOVIv2s_msl:
1193 case AArch64::MOVIv4s_msl:
1194 case AArch64::MVNIv2s_msl:
1195 case AArch64::MVNIv4s_msl:
1247 unsigned ShifterVal = (Imm >> 12) & 3;
1248 unsigned ImmVal = Imm & 0xFFF;
1250 if (ShifterVal != 0 && ShifterVal != 1)
1256 Inst, Rd, Addr, Decoder);
1265 Inst, Rd, Addr, Decoder);
1291 return Op1 == 0b000 && (Op2 == 0b000 ||
1302 uint64_t pstate_field = (op1 << 3) | op2;
1310 auto PState = AArch64PState::lookupPStateImm0_15ByEncoding(pstate_field);
1324 uint64_t pstate_field = (crm_high << 6) | (op1 << 3) | op2;
1332 auto PState = AArch64PState::lookupPStateImm0_1ByEncoding(pstate_field);
1368 MCRegister Reg = AArch64MCRegisterClasses[RegClassID].getRegister(RegNo / 2);
1377 Inst, AArch64::WSeqPairsClassRegClassID, RegNo, Addr, Decoder);
1384 Inst, AArch64::XSeqPairsClassRegClassID, RegNo, Addr, Decoder);
1419 if (Inst.
getOpcode() != AArch64::DUPM_ZI)
1434 if (Imm & ~((1LL << Bits) - 1))
1438 if (Imm & (1 << (Bits - 1)))
1439 Imm |= ~((1LL << Bits) - 1);
1446template <
int ElementW
idth>
1450 unsigned Shift = (Imm & 0x100) ? 8 : 0;
1451 if (ElementWidth == 8 && Shift)
1468 if (AArch64SVCR::lookupSVCRByEncoding(Imm)) {
1484 if (Rd == Rs || Rs == Rn || Rd == Rn)
1490 Inst, Rd, Addr, Decoder) ||
1492 Inst, Rs, Addr, Decoder) ||
1494 Inst, Rn, Addr, Decoder) ||
1496 Inst, Rd, Addr, Decoder) ||
1498 Inst, Rs, Addr, Decoder) ||
1500 Inst, Rn, Addr, Decoder))
1515 if (Rd == Rm || Rm == Rn || Rd == Rn)
1521 Inst, Rd, Addr, Decoder) ||
1523 Inst, Rn, Addr, Decoder) ||
1525 Inst, Rd, Addr, Decoder) ||
1527 Inst, Rn, Addr, Decoder) ||
1529 Inst, Rm, Addr, Decoder))
1540 unsigned Mask = 0x18;
1542 if ((Rt & Mask) == Mask)
1557 case AArch64::PRFMroW:
1561 case AArch64::PRFMroX:
1581 Inst, RvBits, Addr, Decoder);
1592#include "AArch64GenDisassemblerTables.inc"
1593#include "AArch64GenInstrInfo.inc"
1610 if (Bytes.
size() < 4)
1616 (Bytes[3] << 24) | (Bytes[2] << 16) | (Bytes[1] << 8) | (Bytes[0] << 0);
1618 const uint8_t *Tables[] = {DecoderTable32, DecoderTableFallback32};
1620 for (
const auto *Table : Tables) {
1622 decodeInstruction(Table,
MI, Insn,
Address,
this,
STI);
1642 std::unique_ptr<MCRelocationInfo> &&RelInfo) {
1644 SymbolLookUp, DisInfo);
static DecodeStatus DecodeUnconditionalBranch(MCInst &Inst, uint32_t insn, uint64_t Addr, const MCDisassembler *Decoder)
static DecodeStatus DecodeMPR32RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodePCRelLabel16(MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)
static DecodeStatus DecodeMPR8RegisterClass(MCInst &Inst, const MCDisassembler *Decoder)
static DecodeStatus DecodeSystemPStateImm0_1Instruction(MCInst &Inst, uint32_t insn, uint64_t Addr, const MCDisassembler *Decoder)
static DecodeStatus DecodeZPRMul2_MinMax(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeMPR64RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeVecShiftL64Imm(MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)
static DecodeStatus DecodeVecShiftL32Imm(MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)
static MCSymbolizer * createAArch64ExternalSymbolizer(const Triple &TT, LLVMOpInfoCallback GetOpInfo, LLVMSymbolLookupCallback SymbolLookUp, void *DisInfo, MCContext *Ctx, std::unique_ptr< MCRelocationInfo > &&RelInfo)
static DecodeStatus DecodeCPYMemOpInstruction(MCInst &Inst, uint32_t insn, uint64_t Addr, const MCDisassembler *Decoder)
static DecodeStatus DecodeVecShiftR8Imm(MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)
static DecodeStatus DecodeUnsignedLdStInstruction(MCInst &Inst, uint32_t insn, uint64_t Addr, const MCDisassembler *Decoder)
static DecodeStatus DecodeMPRRegisterClass(MCInst &Inst, const MCDisassembler *Decoder)
static DecodeStatus DecodeModImmTiedInstruction(MCInst &Inst, uint32_t insn, uint64_t Addr, const MCDisassembler *Decoder)
static DecodeStatus DecodeFixedPointScaleImm64(MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)
static DecodeStatus DecodeSystemPStateImm0_15Instruction(MCInst &Inst, uint32_t insn, uint64_t Addr, const MCDisassembler *Decoder)
static DecodeStatus DecodeModImmInstruction(MCInst &Inst, uint32_t insn, uint64_t Addr, const MCDisassembler *Decoder)
static MCDisassembler * createAArch64Disassembler(const Target &T, const MCSubtargetInfo &STI, MCContext &Ctx)
static DecodeStatus DecodeGPR64x8ClassRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeThreeAddrSRegInstruction(MCInst &Inst, uint32_t insn, uint64_t Addr, const MCDisassembler *Decoder)
static DecodeStatus DecodeXSeqPairsClassRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Addr, const MCDisassembler *Decoder)
static DecodeStatus DecodeExclusiveLdStInstruction(MCInst &Inst, uint32_t insn, uint64_t Addr, const MCDisassembler *Decoder)
static DecodeStatus DecodeVecShiftL16Imm(MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)
static DecodeStatus DecodeTestAndBranch(MCInst &Inst, uint32_t insn, uint64_t Addr, const MCDisassembler *Decoder)
static DecodeStatus DecodeZeroImm(MCInst &Inst, const MCDisassembler *Decoder)
static DecodeStatus DecodeSImm(MCInst &Inst, uint64_t Imm, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeVecShiftR32ImmNarrow(MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)
static DecodeStatus DecodeZK(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeAdrInstruction(MCInst &Inst, uint32_t insn, uint64_t Addr, const MCDisassembler *Decoder)
static DecodeStatus DecodePPR2Mul2RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
static DecodeStatus DecodePairLdStInstruction(MCInst &Inst, uint32_t insn, uint64_t Addr, const MCDisassembler *Decoder)
static DecodeStatus DecodeVecShiftL8Imm(MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)
static DecodeStatus DecodeSVEIncDecImm(MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)
static DecodeStatus DecodeMPR16RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeVecShiftRImm(MCInst &Inst, unsigned Imm, unsigned Add)
static DecodeStatus DecodeFixedPointScaleImm32(MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)
static DecodeStatus DecodeMoveImmInstruction(MCInst &Inst, uint32_t insn, uint64_t Addr, const MCDisassembler *Decoder)
static DecodeStatus DecodeVecShiftR64Imm(MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)
static DecodeStatus DecodePCRelLabel9(MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)
static DecodeStatus DecodeVecShiftLImm(MCInst &Inst, unsigned Imm, unsigned Add)
static DecodeStatus DecodeVecShiftR16ImmNarrow(MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)
static DecodeStatus DecodeSVCROp(MCInst &Inst, unsigned Imm, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeWSeqPairsClassRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Addr, const MCDisassembler *Decoder)
static DecodeStatus DecodeVecShiftR64ImmNarrow(MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)
static DecodeStatus DecodeZPR4Mul4RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeSMESpillFillInstruction(MCInst &Inst, uint32_t Bits, uint64_t Addr, const MCDisassembler *Decoder)
static DecodeStatus DecodeLogicalImmInstruction(MCInst &Inst, uint32_t insn, uint64_t Addr, const MCDisassembler *Decoder)
MCDisassembler::DecodeStatus DecodeStatus
static DecodeStatus DecodeMSRSystemRegister(MCInst &Inst, unsigned Imm, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeZPR2Mul2RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
LLVM_ABI LLVM_EXTERNAL_VISIBILITY void LLVMInitializeAArch64Disassembler()
static DecodeStatus DecodeSETMemOpInstruction(MCInst &Inst, uint32_t insn, uint64_t Addr, const MCDisassembler *Decoder)
static DecodeStatus DecodeSVELogicalImmInstruction(MCInst &Inst, uint32_t insn, uint64_t Addr, const MCDisassembler *Decoder)
static DecodeStatus DecodeMemExtend(MCInst &Inst, unsigned Imm, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeSignedLdStInstruction(MCInst &Inst, uint32_t insn, uint64_t Addr, const MCDisassembler *Decoder)
static DecodeStatus DecodeAuthLoadInstruction(MCInst &Inst, uint32_t insn, uint64_t Addr, const MCDisassembler *Decoder)
static DecodeStatus DecodeSyspXzrInstruction(MCInst &Inst, uint32_t insn, uint64_t Addr, const MCDisassembler *Decoder)
static DecodeStatus DecodeFMOVLaneInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeAddSubERegInstruction(MCInst &Inst, uint32_t insn, uint64_t Addr, const MCDisassembler *Decoder)
static bool isInvalidPState(uint64_t Op1, uint64_t Op2)
static DecodeStatus DecodeSimpleRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeMatrixTileListRegisterClass(MCInst &Inst, unsigned RegMask, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeVecShiftR16Imm(MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)
static DecodeStatus DecodeVecShiftR32Imm(MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)
static DecodeStatus DecodeImm8OptLsl(MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)
static DecodeStatus DecodePRFMRegInstruction(MCInst &Inst, uint32_t insn, uint64_t Addr, const MCDisassembler *Decoder)
static DecodeStatus DecodeAddSubImmShift(MCInst &Inst, uint32_t insn, uint64_t Addr, const MCDisassembler *Decoder)
static DecodeStatus DecodeGPRSeqPairsClassRegisterClass(MCInst &Inst, unsigned RegClassID, unsigned RegNo, uint64_t Addr, const MCDisassembler *Decoder)
static DecodeStatus DecodeMPR128RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeMRSSystemRegister(MCInst &Inst, unsigned Imm, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeZTRRegisterClass(MCInst &Inst, const MCDisassembler *Decoder)
static DecodeStatus DecodePCRelLabel19(MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)
#define LLVM_EXTERNAL_VISIBILITY
MCDisassembler::DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size, ArrayRef< uint8_t > Bytes, uint64_t Address, raw_ostream &CStream) const override
Returns the disassembly of a single instruction.
uint64_t suggestBytesToSkip(ArrayRef< uint8_t > Bytes, uint64_t Address) const override
Suggest a distance to skip in a buffer of data to find the next place to look for the start of an ins...
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
size_t size() const
size - Get the array size.
Context object for machine code objects.
Superclass for all disassemblers.
bool tryAddingSymbolicOperand(MCInst &Inst, int64_t Value, uint64_t Address, bool IsBranch, uint64_t Offset, uint64_t OpSize, uint64_t InstSize) const
const MCSubtargetInfo & getSubtargetInfo() const
const MCSubtargetInfo & STI
raw_ostream * CommentStream
DecodeStatus
Ternary decode status.
Instances of this class represent a single low-level machine instruction.
unsigned getOpcode() const
void addOperand(const MCOperand Op)
const MCOperand & getOperand(unsigned i) const
static MCOperand createReg(MCRegister Reg)
static MCOperand createImm(int64_t Val)
Wrapper class representing physical registers. Should be passed by value.
Generic base class for all target subtargets.
const FeatureBitset & getFeatureBits() const
Symbolize and annotate disassembled instructions.
Wrapper class representing virtual and physical registers.
Target - Wrapper for Target specific information.
Triple - Helper class for working with autoconf configuration names.
This class implements an extremely fast bulk output stream that can only output to a stream.
const char *(* LLVMSymbolLookupCallback)(void *DisInfo, uint64_t ReferenceValue, uint64_t *ReferenceType, uint64_t ReferencePC, const char **ReferenceName)
The type for the symbol lookup function.
int(* LLVMOpInfoCallback)(void *DisInfo, uint64_t PC, uint64_t Offset, uint64_t OpSize, uint64_t InstSize, int TagType, void *TagBuf)
The type for the operand information call back function.
static bool isValidDecodeLogicalImmediate(uint64_t val, unsigned regSize)
isValidDecodeLogicalImmediate - Check to see if the logical immediate value in the form "N:immr:imms"...
std::enable_if_t< std::is_integral_v< IntType >, IntType > fieldFromInstruction(const IntType &Insn, unsigned StartBit, unsigned NumBits)
This is an optimization pass for GlobalISel generic memory operations.
Target & getTheAArch64beTarget()
Target & getTheAArch64leTarget()
Target & getTheAArch64_32Target()
Target & getTheARM64_32Target()
Target & getTheARM64Target()
constexpr int64_t SignExtend64(uint64_t x)
Sign-extend the number in the bottom B bits of X to a 64-bit integer.
static void RegisterMCSymbolizer(Target &T, Target::MCSymbolizerCtorTy Fn)
RegisterMCSymbolizer - Register an MCSymbolizer implementation for the given target.
static void RegisterMCDisassembler(Target &T, Target::MCDisassemblerCtorTy Fn)
RegisterMCDisassembler - Register a MCDisassembler implementation for the given target.