AMDGPUInstructionSelector.cpp File Reference

This file implements the targeting of the InstructionSelector class for AMDGPU. More...

#include "AMDGPUInstructionSelector.h"
#include "AMDGPU.h"
#include "AMDGPUGlobalISelUtils.h"
#include "AMDGPUInstrInfo.h"
#include "AMDGPURegisterBankInfo.h"
#include "AMDGPUTargetMachine.h"
#include "SIMachineFunctionInfo.h"
#include "Utils/AMDGPUBaseInfo.h"
#include "llvm/CodeGen/GlobalISel/GIMatchTableExecutorImpl.h"
#include "llvm/CodeGen/GlobalISel/GISelValueTracking.h"
#include "llvm/CodeGen/GlobalISel/GenericMachineInstrs.h"
#include "llvm/CodeGen/GlobalISel/MIPatternMatch.h"
#include "llvm/CodeGen/GlobalISel/MachineIRBuilder.h"
#include "llvm/CodeGen/MachineFrameInfo.h"
#include "llvm/IR/DiagnosticInfo.h"
#include "llvm/IR/IntrinsicsAMDGPU.h"
#include <optional>
#include "AMDGPUGenGlobalISel.inc"

Go to the source code of this file.

Classes
class	SearchOptions
	This is used to control valid status that current MI supports. More...

Macros
#define	DEBUG_TYPE   "amdgpu-isel"
#define	GET_GLOBALISEL_IMPL
#define	AMDGPUSubtarget   GCNSubtarget
#define	GET_GLOBALISEL_PREDICATES_INIT
#define	GET_GLOBALISEL_TEMPORARIES_INIT

Enumerations
enum class	SrcStatus {   IS_SAME , IS_UPPER_HALF , IS_LOWER_HALF , IS_UPPER_HALF_NEG ,   IS_LOWER_HALF_NEG , IS_HI_NEG , IS_LO_NEG , IS_BOTH_NEG ,   INVALID , NEG_START = IS_UPPER_HALF_NEG , NEG_END = IS_BOTH_NEG , HALF_START = IS_UPPER_HALF ,   HALF_END = IS_LOWER_HALF_NEG }
enum class	TypeClass { VECTOR_OF_TWO , SCALAR , NONE_OF_LISTED }

Functions
static Register	getWaveAddress (const MachineInstr *Def)
static unsigned	getLogicalBitOpcode (unsigned Opc, bool Is64)
static int	getV_CMPOpcode (CmpInst::Predicate P, unsigned Size, const GCNSubtarget &ST)
static bool	isLaneMaskFromSameBlock (Register Reg, MachineRegisterInfo &MRI, MachineBasicBlock *MBB)
static unsigned	gwsIntrinToOpcode (unsigned IntrID)
static bool	parseTexFail (uint64_t TexFailCtrl, bool &TFE, bool &LWE, bool &IsTexFail)
static bool	shouldUseAndMask (unsigned Size, unsigned &Mask)
static Register	stripCopy (Register Reg, MachineRegisterInfo &MRI)
static Register	stripBitCast (Register Reg, MachineRegisterInfo &MRI)
static bool	isExtractHiElt (MachineRegisterInfo &MRI, Register In, Register &Out)
static bool	isConstant (const MachineInstr &MI)
static bool	isVCmpResult (Register Reg, MachineRegisterInfo &MRI)
static std::pair< Register, unsigned >	computeIndirectRegIndex (MachineRegisterInfo &MRI, const SIRegisterInfo &TRI, const TargetRegisterClass *SuperRC, Register IdxReg, unsigned EltSize, GISelValueTracking &ValueTracking)
	Return the register to use for the index value, and the subregister to use for the indirectly accessed register.
static std::pair< unsigned, uint8_t >	BitOp3_Op (Register R, SmallVectorImpl< Register > &Src, const MachineRegisterInfo &MRI)
static bool	isTruncHalf (const MachineInstr *MI, const MachineRegisterInfo &MRI)
	Test if the MI is truncating to half, such as reg0:n = G_TRUNC reg1:2n
static bool	isLshrHalf (const MachineInstr *MI, const MachineRegisterInfo &MRI)
	Test if the MI is logic shift right with half bits, such as reg0:2n =G_LSHR reg1:2n, CONST(n)
static bool	isShlHalf (const MachineInstr *MI, const MachineRegisterInfo &MRI)
	Test if the MI is shift left with half bits, such as reg0:2n =G_SHL reg1:2n, CONST(n)
static bool	isUnmergeHalf (const MachineInstr *MI, const MachineRegisterInfo &MRI)
	Test function, if the MI is reg0:n, reg1:n = G_UNMERGE_VALUES reg2:2n
static TypeClass	isVectorOfTwoOrScalar (Register Reg, const MachineRegisterInfo &MRI)
static SrcStatus	getNegStatus (Register Reg, SrcStatus S, const MachineRegisterInfo &MRI)
static std::optional< std::pair< Register, SrcStatus > >	calcNextStatus (std::pair< Register, SrcStatus > Curr, const MachineRegisterInfo &MRI)
static SmallVector< std::pair< Register, SrcStatus > >	getSrcStats (Register Reg, const MachineRegisterInfo &MRI, SearchOptions SO, int MaxDepth=3)
static std::pair< Register, SrcStatus >	getLastSameOrNeg (Register Reg, const MachineRegisterInfo &MRI, SearchOptions SO, int MaxDepth=3)
static bool	isSameBitWidth (Register Reg1, Register Reg2, const MachineRegisterInfo &MRI)
static unsigned	updateMods (SrcStatus HiStat, SrcStatus LoStat, unsigned Mods)
static bool	isValidToPack (SrcStatus HiStat, SrcStatus LoStat, Register NewReg, Register RootReg, const SIInstrInfo &TII, const MachineRegisterInfo &MRI)
static bool	checkRB (Register Reg, unsigned int RBNo, const AMDGPURegisterBankInfo &RBI, const MachineRegisterInfo &MRI, const TargetRegisterInfo &TRI)
static Register	getLegalRegBank (Register NewReg, Register RootReg, const AMDGPURegisterBankInfo &RBI, MachineRegisterInfo &MRI, const TargetRegisterInfo &TRI, const SIInstrInfo &TII)
static Register	buildRegSequence (SmallVectorImpl< Register > &Elts, MachineInstr *InsertPt, MachineRegisterInfo &MRI)
static void	selectWMMAModsNegAbs (unsigned ModOpcode, unsigned &Mods, SmallVectorImpl< Register > &Elts, Register &Src, MachineInstr *InsertPt, MachineRegisterInfo &MRI)
static bool	isNoUnsignedWrap (MachineInstr *Addr)
static void	addZeroImm (MachineInstrBuilder &MIB)
static Register	buildRSRC (MachineIRBuilder &B, MachineRegisterInfo &MRI, uint32_t FormatLo, uint32_t FormatHi, Register BasePtr)
	Return a resource descriptor for use with an arbitrary 64-bit pointer.
static Register	buildAddr64RSrc (MachineIRBuilder &B, MachineRegisterInfo &MRI, const SIInstrInfo &TII, Register BasePtr)
static Register	buildOffsetSrc (MachineIRBuilder &B, MachineRegisterInfo &MRI, const SIInstrInfo &TII, Register BasePtr)
static std::optional< uint64_t >	getConstantZext32Val (Register Reg, const MachineRegisterInfo &MRI)
	Get an immediate that must be 32-bits, and treated as zero extended.
unsigned	getNamedBarrierOp (bool HasInlineConst, Intrinsic::ID IntrID)

Detailed Description

This file implements the targeting of the InstructionSelector class for AMDGPU.

Todo

This should be generated by TableGen.

Definition in file AMDGPUInstructionSelector.cpp.

Macro Definition Documentation

AMDGPUSubtarget

#define AMDGPUSubtarget   GCNSubtarget

Definition at line 38 of file AMDGPUInstructionSelector.cpp.

DEBUG_TYPE

#define DEBUG_TYPE   "amdgpu-isel"

Definition at line 32 of file AMDGPUInstructionSelector.cpp.

GET_GLOBALISEL_IMPL

#define GET_GLOBALISEL_IMPL

Definition at line 37 of file AMDGPUInstructionSelector.cpp.

GET_GLOBALISEL_PREDICATES_INIT

#define GET_GLOBALISEL_PREDICATES_INIT

GET_GLOBALISEL_TEMPORARIES_INIT

#define GET_GLOBALISEL_TEMPORARIES_INIT

Enumeration Type Documentation

SrcStatus

enum class SrcStatus

strong

Enumerator
IS_SAME
IS_UPPER_HALF
IS_LOWER_HALF
IS_UPPER_HALF_NEG
IS_LOWER_HALF_NEG
IS_HI_NEG
IS_LO_NEG
IS_BOTH_NEG
INVALID
NEG_START
NEG_END
HALF_START
HALF_END

Definition at line 4379 of file AMDGPUInstructionSelector.cpp.

TypeClass

enum class TypeClass

strong

Enumerator
VECTOR_OF_TWO
SCALAR
NONE_OF_LISTED

Definition at line 4451 of file AMDGPUInstructionSelector.cpp.

Function Documentation

addZeroImm()

void addZeroImm ( MachineInstrBuilder & MIB )

static

Definition at line 6286 of file AMDGPUInstructionSelector.cpp.

References llvm::MachineInstrBuilder::addImm().

BitOp3_Op()

std::pair< unsigned, uint8_t > BitOp3_Op ( Register R, SmallVectorImpl< Register > & Src, const MachineRegisterInfo & MRI )

static

Definition at line 3819 of file AMDGPUInstructionSelector.cpp.

References BitOp3_Op(), llvm::getSrcRegIgnoringCopies(), I, LHS, llvm::MIPatternMatch::m_AllOnesInt(), llvm::MIPatternMatch::m_Not(), llvm::MIPatternMatch::m_Reg(), llvm::MIPatternMatch::m_ZeroInt(), MI, llvm::MIPatternMatch::mi_match(), MRI, and RHS.

Referenced by BitOp3_Op(), and BitOp3_Op().

buildAddr64RSrc()

Register buildAddr64RSrc ( MachineIRBuilder & B, MachineRegisterInfo & MRI, const SIInstrInfo & TII, Register BasePtr )

static

Definition at line 6335 of file AMDGPUInstructionSelector.cpp.

References B(), buildRSRC(), llvm::Hi_32(), MRI, and TII.

buildOffsetSrc()

Register buildOffsetSrc ( MachineIRBuilder & B, MachineRegisterInfo & MRI, const SIInstrInfo & TII, Register BasePtr )

static

Definition at line 6344 of file AMDGPUInstructionSelector.cpp.

References B(), buildRSRC(), llvm::Hi_32(), MRI, and TII.

buildRegSequence()

Register buildRegSequence ( SmallVectorImpl< Register > & Elts, MachineInstr * InsertPt, MachineRegisterInfo & MRI )

static

Definition at line 4970 of file AMDGPUInstructionSelector.cpp.

References llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addReg(), B(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), llvm::SIRegisterInfo::getSubRegFromChannel(), llvm_unreachable, MRI, and llvm::SmallVectorTemplateCommon< T, typename >::size().

Referenced by selectWMMAModsNegAbs(), and selectWMMAModsNegAbs().

buildRSRC()

Register buildRSRC ( MachineIRBuilder & B, MachineRegisterInfo & MRI, uint32_t FormatLo, uint32_t FormatHi, Register BasePtr )

static

Return a resource descriptor for use with an arbitrary 64-bit pointer.

If BasePtr is not valid, a null base pointer will be used.

Definition at line 6292 of file AMDGPUInstructionSelector.cpp.

References B(), and MRI.

Referenced by buildAddr64RSrc(), and buildOffsetSrc().

calcNextStatus()

std::optional< std::pair< Register, SrcStatus > > calcNextStatus ( std::pair< Register, SrcStatus > Curr, const MachineRegisterInfo & MRI )

static

Definition at line 4619 of file AMDGPUInstructionSelector.cpp.

References getNegStatus(), INVALID, IS_HI_NEG, IS_LOWER_HALF, IS_LOWER_HALF_NEG, IS_SAME, IS_UPPER_HALF, IS_UPPER_HALF_NEG, isLshrHalf(), isShlHalf(), isTruncHalf(), isUnmergeHalf(), MI, MRI, and Opc.

Referenced by getLastSameOrNeg(), and getSrcStats().

checkRB()

bool checkRB ( Register Reg, unsigned int RBNo, const AMDGPURegisterBankInfo & RBI, const MachineRegisterInfo & MRI, const TargetRegisterInfo & TRI )

static

Definition at line 4886 of file AMDGPUInstructionSelector.cpp.

References llvm::RegisterBank::getID(), llvm::RegisterBankInfo::getRegBank(), MRI, Reg, and TRI.

Referenced by getLegalRegBank().

computeIndirectRegIndex()

std::pair< Register, unsigned > computeIndirectRegIndex ( MachineRegisterInfo & MRI, const SIRegisterInfo & TRI, const TargetRegisterClass * SuperRC, Register IdxReg, unsigned EltSize, GISelValueTracking & ValueTracking )

static

Return the register to use for the index value, and the subregister to use for the indirectly accessed register.

Definition at line 3179 of file AMDGPUInstructionSelector.cpp.

References assert(), llvm::AMDGPU::getBaseWithConstantOffset(), MRI, llvm::Offset, llvm::ArrayRef< T >::size(), and TRI.

getConstantZext32Val()

std::optional< uint64_t > getConstantZext32Val ( Register Reg, const MachineRegisterInfo & MRI )

static

Get an immediate that must be 32-bits, and treated as zero extended.

Definition at line 6565 of file AMDGPUInstructionSelector.cpp.

References llvm::getIConstantVRegSExtVal(), llvm::isInt(), llvm::Lo_32(), MRI, and Reg.

getLastSameOrNeg()

std::pair< Register, SrcStatus > getLastSameOrNeg ( Register Reg, const MachineRegisterInfo & MRI, SearchOptions SO, int MaxDepth = 3 )

static

Definition at line 4762 of file AMDGPUInstructionSelector.cpp.

References calcNextStatus(), SearchOptions::checkOptions(), llvm::Depth, IS_BOTH_NEG, IS_HI_NEG, IS_LO_NEG, IS_SAME, MRI, and Reg.

getLegalRegBank()

Register getLegalRegBank ( Register NewReg, Register RootReg, const AMDGPURegisterBankInfo & RBI, MachineRegisterInfo & MRI, const TargetRegisterInfo & TRI, const SIInstrInfo & TII )

static

Definition at line 4901 of file AMDGPUInstructionSelector.cpp.

References llvm::MachineInstrBuilder::addReg(), llvm::BuildMI(), checkRB(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), MI, MRI, TII, and TRI.

getLogicalBitOpcode()

unsigned getLogicalBitOpcode ( unsigned Opc, bool Is64 )

static

Definition at line 375 of file AMDGPUInstructionSelector.cpp.

References llvm_unreachable, and Opc.

getNamedBarrierOp()

unsigned getNamedBarrierOp	(	bool	HasInlineConst,
		Intrinsic::ID	IntrID )

Definition at line 6756 of file AMDGPUInstructionSelector.cpp.

References llvm_unreachable.

getNegStatus()

SrcStatus getNegStatus ( Register Reg, SrcStatus S, const MachineRegisterInfo & MRI )

static

Definition at line 4463 of file AMDGPUInstructionSelector.cpp.

References INVALID, IS_BOTH_NEG, IS_HI_NEG, IS_LO_NEG, IS_LOWER_HALF, IS_LOWER_HALF_NEG, IS_SAME, IS_UPPER_HALF, IS_UPPER_HALF_NEG, isVectorOfTwoOrScalar(), llvm_unreachable, MRI, Reg, SCALAR, and VECTOR_OF_TWO.

Referenced by calcNextStatus().

getSrcStats()

SmallVector< std::pair< Register, SrcStatus > > getSrcStats ( Register Reg, const MachineRegisterInfo & MRI, SearchOptions SO, int MaxDepth = 3 )

static

Definition at line 4745 of file AMDGPUInstructionSelector.cpp.

References calcNextStatus(), SearchOptions::checkOptions(), llvm::Depth, IS_SAME, MRI, and Reg.

getV_CMPOpcode()

int getV_CMPOpcode ( CmpInst::Predicate P, unsigned Size, const GCNSubtarget & ST )

static

Definition at line 1208 of file AMDGPUInstructionSelector.cpp.

References llvm::CmpInst::FCMP_FALSE, llvm::CmpInst::FCMP_OEQ, llvm::CmpInst::FCMP_OGE, llvm::CmpInst::FCMP_OGT, llvm::CmpInst::FCMP_OLE, llvm::CmpInst::FCMP_OLT, llvm::CmpInst::FCMP_ONE, llvm::CmpInst::FCMP_ORD, llvm::CmpInst::FCMP_TRUE, llvm::CmpInst::FCMP_UEQ, llvm::CmpInst::FCMP_UGE, llvm::CmpInst::FCMP_UGT, llvm::CmpInst::FCMP_ULE, llvm::CmpInst::FCMP_ULT, llvm::CmpInst::FCMP_UNE, llvm::CmpInst::FCMP_UNO, llvm::CmpInst::ICMP_EQ, llvm::CmpInst::ICMP_NE, llvm::CmpInst::ICMP_SGE, llvm::CmpInst::ICMP_SGT, llvm::CmpInst::ICMP_SLE, llvm::CmpInst::ICMP_SLT, llvm::CmpInst::ICMP_UGE, llvm::CmpInst::ICMP_UGT, llvm::CmpInst::ICMP_ULE, llvm::CmpInst::ICMP_ULT, llvm_unreachable, P, Select, and Size.

getWaveAddress()

Register getWaveAddress ( const MachineInstr * Def )

static

Definition at line 71 of file AMDGPUInstructionSelector.cpp.

References Register.

gwsIntrinToOpcode()

unsigned gwsIntrinToOpcode ( unsigned IntrID )

static

Definition at line 1842 of file AMDGPUInstructionSelector.cpp.

References llvm_unreachable.

isConstant()

bool isConstant ( const MachineInstr & MI )

static

Definition at line 2877 of file AMDGPUInstructionSelector.cpp.

References MI.

Referenced by allConstant(), arePointersCompatible(), llvm::buildModuleSummaryIndex(), llvm::MDBuilder::createTBAANode(), llvm::HexagonInstrInfo::expandPostRAPseudo(), llvm::slpvectorizer::BoUpSLP::findReusedOrderedScalars(), getMemcpyLoadsAndStores(), llvm::slpvectorizer::BoUpSLP::getReorderingData(), isSimpleVIDSequence(), llvm::slpvectorizer::BoUpSLP::reorderBottomToTop(), tryFoldHelper(), and tryToFindDuplicates().

isExtractHiElt()

bool isExtractHiElt ( MachineRegisterInfo & MRI, Register In, Register & Out )

static

Definition at line 2719 of file AMDGPUInstructionSelector.cpp.

References assert(), llvm::LLT::fixed_vector(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), llvm::MachineOperand::getShuffleMask(), llvm::MIPatternMatch::m_GLShr(), llvm::MIPatternMatch::m_GTrunc(), llvm::MIPatternMatch::m_Reg(), llvm::MIPatternMatch::m_SpecificICst(), llvm::MIPatternMatch::mi_match(), MRI, stripBitCast(), and stripCopy().

Referenced by buildRegSequence16().

isLaneMaskFromSameBlock()

bool isLaneMaskFromSameBlock ( Register Reg, MachineRegisterInfo & MRI, MachineBasicBlock * MBB )

static

Definition at line 1569 of file AMDGPUInstructionSelector.cpp.

References llvm::RegisterBank::getID(), llvm::isa(), isLaneMaskFromSameBlock(), LHS, llvm::MIPatternMatch::m_GAnd(), llvm::MIPatternMatch::m_Reg(), MBB, MI, llvm::MIPatternMatch::mi_match(), MRI, Reg, and RHS.

Referenced by isLaneMaskFromSameBlock().

isLshrHalf()

bool isLshrHalf ( const MachineInstr * MI, const MachineRegisterInfo & MRI )

static

Test if the MI is logic shift right with half bits, such as reg0:2n =G_LSHR reg1:2n, CONST(n)

Definition at line 4410 of file AMDGPUInstructionSelector.cpp.

References llvm::MIPatternMatch::m_GCst(), llvm::MIPatternMatch::m_GLShr(), llvm::MIPatternMatch::m_Reg(), MI, llvm::MIPatternMatch::mi_match(), and MRI.

Referenced by calcNextStatus().

isNoUnsignedWrap()

bool isNoUnsignedWrap ( MachineInstr * Addr )

static

Definition at line 6007 of file AMDGPUInstructionSelector.cpp.

References llvm::MachineInstr::getFlag(), llvm::MachineInstr::getOpcode(), and llvm::MachineInstr::NoUWrap.

isSameBitWidth()

bool isSameBitWidth ( Register Reg1, Register Reg2, const MachineRegisterInfo & MRI )

static

Definition at line 4782 of file AMDGPUInstructionSelector.cpp.

References MRI.

Referenced by isValidToPack().

isShlHalf()

bool isShlHalf ( const MachineInstr * MI, const MachineRegisterInfo & MRI )

static

Test if the MI is shift left with half bits, such as reg0:2n =G_SHL reg1:2n, CONST(n)

Definition at line 4427 of file AMDGPUInstructionSelector.cpp.

References llvm::MIPatternMatch::m_GCst(), llvm::MIPatternMatch::m_GShl(), llvm::MIPatternMatch::m_Reg(), MI, llvm::MIPatternMatch::mi_match(), and MRI.

Referenced by calcNextStatus().

isTruncHalf()

bool isTruncHalf ( const MachineInstr * MI, const MachineRegisterInfo & MRI )

static

Test if the MI is truncating to half, such as reg0:n = G_TRUNC reg1:2n

Definition at line 4398 of file AMDGPUInstructionSelector.cpp.

References MI, and MRI.

Referenced by calcNextStatus().

isUnmergeHalf()

bool isUnmergeHalf ( const MachineInstr * MI, const MachineRegisterInfo & MRI )

static

Test function, if the MI is reg0:n, reg1:n = G_UNMERGE_VALUES reg2:2n

Definition at line 4443 of file AMDGPUInstructionSelector.cpp.

References MI, and MRI.

Referenced by calcNextStatus().

isValidToPack()

bool isValidToPack ( SrcStatus HiStat, SrcStatus LoStat, Register NewReg, Register RootReg, const SIInstrInfo & TII, const MachineRegisterInfo & MRI )

static

Definition at line 4814 of file AMDGPUInstructionSelector.cpp.

References IS_LOWER_HALF, IS_LOWER_HALF_NEG, IS_UPPER_HALF, IS_UPPER_HALF_NEG, isSameBitWidth(), MRI, and TII.

isVCmpResult()

bool isVCmpResult ( Register Reg, MachineRegisterInfo & MRI )

static

Definition at line 2973 of file AMDGPUInstructionSelector.cpp.

References llvm::dyn_cast(), isVCmpResult(), MI, MRI, and Reg.

Referenced by isVCmpResult().

isVectorOfTwoOrScalar()

TypeClass isVectorOfTwoOrScalar ( Register Reg, const MachineRegisterInfo & MRI )

static

Definition at line 4453 of file AMDGPUInstructionSelector.cpp.

References llvm::LLT::getNumElements(), llvm::LLT::isScalar(), llvm::LLT::isVector(), MRI, NONE_OF_LISTED, Reg, SCALAR, and VECTOR_OF_TWO.

Referenced by getNegStatus().

parseTexFail()

bool parseTexFail ( uint64_t TexFailCtrl, bool & TFE, bool & LWE, bool & IsTexFail )

static

Definition at line 1992 of file AMDGPUInstructionSelector.cpp.

selectWMMAModsNegAbs()

void selectWMMAModsNegAbs ( unsigned ModOpcode, unsigned & Mods, SmallVectorImpl< Register > & Elts, Register & Src, MachineInstr * InsertPt, MachineRegisterInfo & MRI )

static

Definition at line 4998 of file AMDGPUInstructionSelector.cpp.

References assert(), buildRegSequence(), llvm::MIPatternMatch::m_GFabs(), llvm::MIPatternMatch::m_Reg(), llvm::MIPatternMatch::mi_match(), MRI, llvm::SISrcMods::NEG, llvm::SISrcMods::NEG_HI, llvm::SmallVectorTemplateBase< T, bool >::push_back(), and llvm::SmallVectorTemplateCommon< T, typename >::size().

shouldUseAndMask()

bool shouldUseAndMask ( unsigned Size, unsigned & Mask )

static

Returns

true if a bitmask for Size bits will be an inline immediate.

Definition at line 2538 of file AMDGPUInstructionSelector.cpp.

References llvm::maskTrailingOnes(), and Size.

stripBitCast()

Register stripBitCast ( Register Reg, MachineRegisterInfo & MRI )

static

Definition at line 2712 of file AMDGPUInstructionSelector.cpp.

References llvm::MIPatternMatch::m_GBitcast(), llvm::MIPatternMatch::m_Reg(), llvm::MIPatternMatch::mi_match(), MRI, and Reg.

Referenced by isExtractHiElt().

stripCopy()

Register stripCopy ( Register Reg, MachineRegisterInfo & MRI )

static

Definition at line 2708 of file AMDGPUInstructionSelector.cpp.

References llvm::getDefSrcRegIgnoringCopies(), MRI, and Reg.

Referenced by isExtractHiElt().

updateMods()

unsigned updateMods ( SrcStatus HiStat, SrcStatus LoStat, unsigned Mods )

static

Definition at line 4789 of file AMDGPUInstructionSelector.cpp.

References IS_HI_NEG, IS_LOWER_HALF_NEG, IS_UPPER_HALF, IS_UPPER_HALF_NEG, llvm::SISrcMods::NEG, llvm::SISrcMods::NEG_HI, llvm::SISrcMods::OP_SEL_0, and llvm::SISrcMods::OP_SEL_1.