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ARMDisassembler.cpp
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1//===- ARMDisassembler.cpp - Disassembler for ARM/Thumb ISA ---------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8
9#include "ARMBaseInstrInfo.h"
14#include "Utils/ARMBaseInfo.h"
15#include "llvm/MC/MCContext.h"
16#include "llvm/MC/MCDecoder.h"
19#include "llvm/MC/MCInst.h"
20#include "llvm/MC/MCInstrDesc.h"
21#include "llvm/MC/MCInstrInfo.h"
29#include <algorithm>
30#include <cassert>
31#include <cstdint>
32#include <vector>
33
34using namespace llvm;
35using namespace llvm::MCD;
36
37#define DEBUG_TYPE "arm-disassembler"
38
40
41namespace {
42
43// Handles the condition code status of instructions in IT blocks
44class ITStatus {
45public:
46 // Returns the condition code for instruction in IT block
47 unsigned getITCC() {
48 unsigned CC = ARMCC::AL;
49 if (instrInITBlock())
50 CC = ITStates.back();
51 return CC;
52 }
53
54 // Advances the IT block state to the next T or E
55 void advanceITState() { ITStates.pop_back(); }
56
57 // Returns true if the current instruction is in an IT block
58 bool instrInITBlock() { return !ITStates.empty(); }
59
60 // Returns true if current instruction is the last instruction in an IT block
61 bool instrLastInITBlock() { return ITStates.size() == 1; }
62
63 // Called when decoding an IT instruction. Sets the IT state for
64 // the following instructions that for the IT block. Firstcond
65 // corresponds to the field in the IT instruction encoding; Mask
66 // is in the MCOperand format in which 1 means 'else' and 0 'then'.
67 void setITState(char Firstcond, char Mask) {
68 // (3 - the number of trailing zeros) is the number of then / else.
69 unsigned NumTZ = llvm::countr_zero<uint8_t>(Mask);
70 unsigned char CCBits = static_cast<unsigned char>(Firstcond & 0xf);
71 assert(NumTZ <= 3 && "Invalid IT mask!");
72 // push condition codes onto the stack the correct order for the pops
73 for (unsigned Pos = NumTZ + 1; Pos <= 3; ++Pos) {
74 unsigned Else = (Mask >> Pos) & 1;
75 ITStates.push_back(CCBits ^ Else);
76 }
77 ITStates.push_back(CCBits);
78 }
79
80private:
81 std::vector<unsigned char> ITStates;
82};
83
84class VPTStatus {
85public:
86 unsigned getVPTPred() {
87 unsigned Pred = ARMVCC::None;
88 if (instrInVPTBlock())
89 Pred = VPTStates.back();
90 return Pred;
91 }
92
93 void advanceVPTState() { VPTStates.pop_back(); }
94
95 bool instrInVPTBlock() { return !VPTStates.empty(); }
96
97 bool instrLastInVPTBlock() { return VPTStates.size() == 1; }
98
99 void setVPTState(char Mask) {
100 // (3 - the number of trailing zeros) is the number of then / else.
101 unsigned NumTZ = llvm::countr_zero<uint8_t>(Mask);
102 assert(NumTZ <= 3 && "Invalid VPT mask!");
103 // push predicates onto the stack the correct order for the pops
104 for (unsigned Pos = NumTZ + 1; Pos <= 3; ++Pos) {
105 bool T = ((Mask >> Pos) & 1) == 0;
106 if (T)
107 VPTStates.push_back(ARMVCC::Then);
108 else
109 VPTStates.push_back(ARMVCC::Else);
110 }
111 VPTStates.push_back(ARMVCC::Then);
112 }
113
114private:
116};
117
118/// ARM disassembler for all ARM platforms.
119class ARMDisassembler : public MCDisassembler {
120public:
121 std::unique_ptr<const MCInstrInfo> MCII;
122 mutable ITStatus ITBlock;
123 mutable VPTStatus VPTBlock;
124
125 ARMDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx,
126 const MCInstrInfo *MCII)
127 : MCDisassembler(STI, Ctx), MCII(MCII) {
128 InstructionEndianness = STI.hasFeature(ARM::ModeBigEndianInstructions)
131 }
132
133 ~ARMDisassembler() override = default;
134
135 DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size,
136 ArrayRef<uint8_t> Bytes, uint64_t Address,
137 raw_ostream &CStream) const override;
138
139 uint64_t suggestBytesToSkip(ArrayRef<uint8_t> Bytes,
140 uint64_t Address) const override;
141
142private:
143 DecodeStatus getARMInstruction(MCInst &Instr, uint64_t &Size,
144 ArrayRef<uint8_t> Bytes, uint64_t Address,
145 raw_ostream &CStream) const;
146
147 DecodeStatus getThumbInstruction(MCInst &Instr, uint64_t &Size,
148 ArrayRef<uint8_t> Bytes, uint64_t Address,
149 raw_ostream &CStream) const;
150
151 bool isVectorPredicable(const MCInst &MI) const;
152 DecodeStatus AddThumbPredicate(MCInst&) const;
153 void UpdateThumbPredicate(DecodeStatus &S, MCInst &MI) const;
154
155 llvm::endianness InstructionEndianness;
156};
157
158} // end anonymous namespace
159
160typedef DecodeStatus OperandDecoder(MCInst &Inst, unsigned Val,
161 uint64_t Address,
162 const MCDisassembler *Decoder);
163
164/// tryAddingSymbolicOperand - trys to add a symbolic operand in place of the
165/// immediate Value in the MCInst. The immediate Value has had any PC
166/// adjustment made by the caller. If the instruction is a branch instruction
167/// then isBranch is true, else false. If the getOpInfo() function was set as
168/// part of the setupForSymbolicDisassembly() call then that function is called
169/// to get any symbolic information at the Address for this instruction. If
170/// that returns non-zero then the symbolic information it returns is used to
171/// create an MCExpr and that is added as an operand to the MCInst. If
172/// getOpInfo() returns zero and isBranch is true then a symbol look up for
173/// Value is done and if a symbol is found an MCExpr is created with that, else
174/// an MCExpr with Value is created. This function returns true if it adds an
175/// operand to the MCInst and false otherwise.
176static bool tryAddingSymbolicOperand(uint64_t Address, int32_t Value,
177 bool isBranch, uint64_t InstSize,
178 MCInst &MI,
179 const MCDisassembler *Decoder) {
180 // FIXME: Does it make sense for value to be negative?
181 return Decoder->tryAddingSymbolicOperand(MI, (uint32_t)Value, Address,
182 isBranch, /*Offset=*/0, /*OpSize=*/0,
183 InstSize);
184}
185
186/// tryAddingPcLoadReferenceComment - trys to add a comment as to what is being
187/// referenced by a load instruction with the base register that is the Pc.
188/// These can often be values in a literal pool near the Address of the
189/// instruction. The Address of the instruction and its immediate Value are
190/// used as a possible literal pool entry. The SymbolLookUp call back will
191/// return the name of a symbol referenced by the literal pool's entry if
192/// the referenced address is that of a symbol. Or it will return a pointer to
193/// a literal 'C' string if the referenced address of the literal pool's entry
194/// is an address into a section with 'C' string literals.
196 const MCDisassembler *Decoder) {
197 Decoder->tryAddingPcLoadReferenceComment(Value, Address);
198}
199
200// Register class decoding functions.
201
202static const uint16_t GPRDecoderTable[] = {
203 ARM::R0, ARM::R1, ARM::R2, ARM::R3,
204 ARM::R4, ARM::R5, ARM::R6, ARM::R7,
205 ARM::R8, ARM::R9, ARM::R10, ARM::R11,
206 ARM::R12, ARM::SP, ARM::LR, ARM::PC
207};
208
210 ARM::R0, ARM::R1, ARM::R2, ARM::R3,
211 ARM::R4, ARM::R5, ARM::R6, ARM::R7,
212 ARM::R8, ARM::R9, ARM::R10, ARM::R11,
213 ARM::R12, 0, ARM::LR, ARM::APSR
214};
215
216static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo,
217 uint64_t Address,
218 const MCDisassembler *Decoder) {
219 if (RegNo > 15)
221
222 unsigned Register = GPRDecoderTable[RegNo];
225}
226
227static DecodeStatus DecodeCLRMGPRRegisterClass(MCInst &Inst, unsigned RegNo,
228 uint64_t Address,
229 const MCDisassembler *Decoder) {
230 if (RegNo > 15)
232
233 unsigned Register = CLRMGPRDecoderTable[RegNo];
234 if (Register == 0)
236
239}
240
241static DecodeStatus DecodeGPRnopcRegisterClass(MCInst &Inst, unsigned RegNo,
242 uint64_t Address,
243 const MCDisassembler *Decoder) {
245
246 if (RegNo == 15)
248
249 Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder));
250
251 return S;
252}
253
254static DecodeStatus DecodeGPRnospRegisterClass(MCInst &Inst, unsigned RegNo,
255 uint64_t Address,
256 const MCDisassembler *Decoder) {
258
259 if (RegNo == 13)
261
262 Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder));
263
264 return S;
265}
266
267static DecodeStatus
268DecodeGPRwithAPSRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address,
269 const MCDisassembler *Decoder) {
271
272 if (RegNo == 15)
273 {
274 Inst.addOperand(MCOperand::createReg(ARM::APSR_NZCV));
276 }
277
278 Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder));
279 return S;
280}
281
282static DecodeStatus
283DecodeGPRwithZRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address,
284 const MCDisassembler *Decoder) {
286
287 if (RegNo == 15)
288 {
289 Inst.addOperand(MCOperand::createReg(ARM::ZR));
291 }
292
293 if (RegNo == 13)
295
296 Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder));
297 return S;
298}
299
300static DecodeStatus
301DecodeGPRwithZRnospRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address,
302 const MCDisassembler *Decoder) {
304 if (RegNo == 13)
306 Check(S, DecodeGPRwithZRRegisterClass(Inst, RegNo, Address, Decoder));
307 return S;
308}
309
310static DecodeStatus DecodetGPRRegisterClass(MCInst &Inst, unsigned RegNo,
311 uint64_t Address,
312 const MCDisassembler *Decoder) {
313 if (RegNo > 7)
315 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder);
316}
317
319 ARM::R0_R1, ARM::R2_R3, ARM::R4_R5, ARM::R6_R7,
320 ARM::R8_R9, ARM::R10_R11, ARM::R12_SP
321};
322
323static DecodeStatus DecodeGPRPairRegisterClass(MCInst &Inst, unsigned RegNo,
324 uint64_t Address,
325 const MCDisassembler *Decoder) {
327
328 // According to the Arm ARM RegNo = 14 is undefined, but we return fail
329 // rather than SoftFail as there is no GPRPair table entry for index 7.
330 if (RegNo > 13)
332
333 if (RegNo & 1)
335
336 unsigned RegisterPair = GPRPairDecoderTable[RegNo/2];
337 Inst.addOperand(MCOperand::createReg(RegisterPair));
338 return S;
339}
340
341static DecodeStatus
342DecodeGPRPairnospRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address,
343 const MCDisassembler *Decoder) {
344 if (RegNo > 13)
346
347 unsigned RegisterPair = GPRPairDecoderTable[RegNo/2];
348 Inst.addOperand(MCOperand::createReg(RegisterPair));
349
350 if ((RegNo & 1) || RegNo > 10)
353}
354
355static DecodeStatus DecodeGPRspRegisterClass(MCInst &Inst, unsigned RegNo,
356 uint64_t Address,
357 const MCDisassembler *Decoder) {
358 if (RegNo != 13)
360
361 unsigned Register = GPRDecoderTable[RegNo];
364}
365
366static DecodeStatus DecodetcGPRRegisterClass(MCInst &Inst, unsigned RegNo,
367 uint64_t Address,
368 const MCDisassembler *Decoder) {
369 unsigned Register = 0;
370 switch (RegNo) {
371 case 0:
372 Register = ARM::R0;
373 break;
374 case 1:
375 Register = ARM::R1;
376 break;
377 case 2:
378 Register = ARM::R2;
379 break;
380 case 3:
381 Register = ARM::R3;
382 break;
383 case 9:
384 Register = ARM::R9;
385 break;
386 case 12:
387 Register = ARM::R12;
388 break;
389 default:
391 }
392
395}
396
397static DecodeStatus DecoderGPRRegisterClass(MCInst &Inst, unsigned RegNo,
398 uint64_t Address,
399 const MCDisassembler *Decoder) {
401
402 const FeatureBitset &featureBits =
403 Decoder->getSubtargetInfo().getFeatureBits();
404
405 if ((RegNo == 13 && !featureBits[ARM::HasV8Ops]) || RegNo == 15)
407
408 Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder));
409 return S;
410}
411
412static const MCPhysReg SPRDecoderTable[] = {
413 ARM::S0, ARM::S1, ARM::S2, ARM::S3,
414 ARM::S4, ARM::S5, ARM::S6, ARM::S7,
415 ARM::S8, ARM::S9, ARM::S10, ARM::S11,
416 ARM::S12, ARM::S13, ARM::S14, ARM::S15,
417 ARM::S16, ARM::S17, ARM::S18, ARM::S19,
418 ARM::S20, ARM::S21, ARM::S22, ARM::S23,
419 ARM::S24, ARM::S25, ARM::S26, ARM::S27,
420 ARM::S28, ARM::S29, ARM::S30, ARM::S31
421};
422
423static DecodeStatus DecodeSPRRegisterClass(MCInst &Inst, unsigned RegNo,
424 uint64_t Address,
425 const MCDisassembler *Decoder) {
426 if (RegNo > 31)
428
429 unsigned Register = SPRDecoderTable[RegNo];
432}
433
434static DecodeStatus DecodeHPRRegisterClass(MCInst &Inst, unsigned RegNo,
435 uint64_t Address,
436 const MCDisassembler *Decoder) {
437 return DecodeSPRRegisterClass(Inst, RegNo, Address, Decoder);
438}
439
440static const MCPhysReg DPRDecoderTable[] = {
441 ARM::D0, ARM::D1, ARM::D2, ARM::D3,
442 ARM::D4, ARM::D5, ARM::D6, ARM::D7,
443 ARM::D8, ARM::D9, ARM::D10, ARM::D11,
444 ARM::D12, ARM::D13, ARM::D14, ARM::D15,
445 ARM::D16, ARM::D17, ARM::D18, ARM::D19,
446 ARM::D20, ARM::D21, ARM::D22, ARM::D23,
447 ARM::D24, ARM::D25, ARM::D26, ARM::D27,
448 ARM::D28, ARM::D29, ARM::D30, ARM::D31
449};
450
451// Does this instruction/subtarget permit use of registers d16-d31?
452static bool PermitsD32(const MCInst &Inst, const MCDisassembler *Decoder) {
453 if (Inst.getOpcode() == ARM::VSCCLRMD || Inst.getOpcode() == ARM::VSCCLRMS)
454 return true;
455 const FeatureBitset &featureBits =
456 Decoder->getSubtargetInfo().getFeatureBits();
457 return featureBits[ARM::FeatureD32];
458}
459
460static DecodeStatus DecodeDPRRegisterClass(MCInst &Inst, unsigned RegNo,
461 uint64_t Address,
462 const MCDisassembler *Decoder) {
463 if (RegNo > (PermitsD32(Inst, Decoder) ? 31u : 15u))
465
466 unsigned Register = DPRDecoderTable[RegNo];
469}
470
471static DecodeStatus DecodeDPR_8RegisterClass(MCInst &Inst, unsigned RegNo,
472 uint64_t Address,
473 const MCDisassembler *Decoder) {
474 if (RegNo > 7)
476 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder);
477}
478
479static DecodeStatus DecodeSPR_8RegisterClass(MCInst &Inst, unsigned RegNo,
480 uint64_t Address,
481 const MCDisassembler *Decoder) {
482 if (RegNo > 15)
484 return DecodeSPRRegisterClass(Inst, RegNo, Address, Decoder);
485}
486
488 uint64_t Address,
489 const MCDisassembler *Decoder) {
490 if (RegNo > 15)
492 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder);
493}
494
495static const MCPhysReg QPRDecoderTable[] = {
496 ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3,
497 ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7,
498 ARM::Q8, ARM::Q9, ARM::Q10, ARM::Q11,
499 ARM::Q12, ARM::Q13, ARM::Q14, ARM::Q15
500};
501
502static DecodeStatus DecodeQPRRegisterClass(MCInst &Inst, unsigned RegNo,
503 uint64_t Address,
504 const MCDisassembler *Decoder) {
505 if (RegNo > 31 || (RegNo & 1) != 0)
507 RegNo >>= 1;
508
509 unsigned Register = QPRDecoderTable[RegNo];
512}
513
514static const MCPhysReg DPairDecoderTable[] = {
515 ARM::Q0, ARM::D1_D2, ARM::Q1, ARM::D3_D4, ARM::Q2, ARM::D5_D6,
516 ARM::Q3, ARM::D7_D8, ARM::Q4, ARM::D9_D10, ARM::Q5, ARM::D11_D12,
517 ARM::Q6, ARM::D13_D14, ARM::Q7, ARM::D15_D16, ARM::Q8, ARM::D17_D18,
518 ARM::Q9, ARM::D19_D20, ARM::Q10, ARM::D21_D22, ARM::Q11, ARM::D23_D24,
519 ARM::Q12, ARM::D25_D26, ARM::Q13, ARM::D27_D28, ARM::Q14, ARM::D29_D30,
520 ARM::Q15
521};
522
523static DecodeStatus DecodeDPairRegisterClass(MCInst &Inst, unsigned RegNo,
524 uint64_t Address,
525 const MCDisassembler *Decoder) {
526 if (RegNo > 30)
528
529 unsigned Register = DPairDecoderTable[RegNo];
532}
533
535 ARM::D0_D2, ARM::D1_D3, ARM::D2_D4, ARM::D3_D5,
536 ARM::D4_D6, ARM::D5_D7, ARM::D6_D8, ARM::D7_D9,
537 ARM::D8_D10, ARM::D9_D11, ARM::D10_D12, ARM::D11_D13,
538 ARM::D12_D14, ARM::D13_D15, ARM::D14_D16, ARM::D15_D17,
539 ARM::D16_D18, ARM::D17_D19, ARM::D18_D20, ARM::D19_D21,
540 ARM::D20_D22, ARM::D21_D23, ARM::D22_D24, ARM::D23_D25,
541 ARM::D24_D26, ARM::D25_D27, ARM::D26_D28, ARM::D27_D29,
542 ARM::D28_D30, ARM::D29_D31
543};
544
545static DecodeStatus
546DecodeDPairSpacedRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address,
547 const MCDisassembler *Decoder) {
548 if (RegNo > 29)
550
551 unsigned Register = DPairSpacedDecoderTable[RegNo];
554}
555
556static DecodeStatus DecodeMQPRRegisterClass(MCInst &Inst, unsigned RegNo,
557 uint64_t Address,
558 const MCDisassembler *Decoder) {
559 if (RegNo > 7)
561
562 unsigned Register = QPRDecoderTable[RegNo];
565}
566
567static const MCPhysReg QQPRDecoderTable[] = {
568 ARM::Q0_Q1, ARM::Q1_Q2, ARM::Q2_Q3, ARM::Q3_Q4,
569 ARM::Q4_Q5, ARM::Q5_Q6, ARM::Q6_Q7
570};
571
572static DecodeStatus DecodeMQQPRRegisterClass(MCInst &Inst, unsigned RegNo,
573 uint64_t Address,
574 const MCDisassembler *Decoder) {
575 if (RegNo > 6)
577
578 unsigned Register = QQPRDecoderTable[RegNo];
581}
582
584 ARM::Q0_Q1_Q2_Q3, ARM::Q1_Q2_Q3_Q4, ARM::Q2_Q3_Q4_Q5,
585 ARM::Q3_Q4_Q5_Q6, ARM::Q4_Q5_Q6_Q7
586};
587
588static DecodeStatus DecodeMQQQQPRRegisterClass(MCInst &Inst, unsigned RegNo,
589 uint64_t Address,
590 const MCDisassembler *Decoder) {
591 if (RegNo > 4)
593
594 unsigned Register = QQQQPRDecoderTable[RegNo];
597}
598
599// Operand decoding functions.
600
601static DecodeStatus DecodePredicateOperand(MCInst &Inst, unsigned Val,
602 uint64_t Address,
603 const MCDisassembler *Decoder) {
605 if (Val == 0xF) return MCDisassembler::Fail;
606 // AL predicate is not allowed on Thumb1 branches.
607 if (Inst.getOpcode() == ARM::tBcc && Val == 0xE)
609 const MCInstrInfo *MCII =
610 static_cast<const ARMDisassembler *>(Decoder)->MCII.get();
611 if (Val != ARMCC::AL && !MCII->get(Inst.getOpcode()).isPredicable())
614 if (Val == ARMCC::AL) {
615 Inst.addOperand(MCOperand::createReg(ARM::NoRegister));
616 } else
617 Inst.addOperand(MCOperand::createReg(ARM::CPSR));
618 return S;
619}
620
621static DecodeStatus DecodeCCOutOperand(MCInst &Inst, unsigned Val,
622 uint64_t Address,
623 const MCDisassembler *Decoder) {
624 if (Val)
625 Inst.addOperand(MCOperand::createReg(ARM::CPSR));
626 else
627 Inst.addOperand(MCOperand::createReg(ARM::NoRegister));
629}
630
631// This overload is called when decoding `s_cc_out` operand, which is not
632// encoded into instruction. It is only used in Thumb1 instructions.
634 const MCDisassembler *Decoder) {
635 const auto *D = static_cast<const ARMDisassembler *>(Decoder);
636 // Thumb1 instructions define CPSR unless they are inside an IT block.
637 MCRegister CCR = D->ITBlock.instrInITBlock() ? ARM::NoRegister : ARM::CPSR;
640}
641
642static DecodeStatus DecodeSORegImmOperand(MCInst &Inst, unsigned Val,
643 uint64_t Address,
644 const MCDisassembler *Decoder) {
646
647 unsigned Rm = fieldFromInstruction(Val, 0, 4);
648 unsigned type = fieldFromInstruction(Val, 5, 2);
649 unsigned imm = fieldFromInstruction(Val, 7, 5);
650
651 // Register-immediate
652 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder)))
654
656 switch (type) {
657 case 0:
658 Shift = ARM_AM::lsl;
659 break;
660 case 1:
661 Shift = ARM_AM::lsr;
662 break;
663 case 2:
664 Shift = ARM_AM::asr;
665 break;
666 case 3:
667 Shift = ARM_AM::ror;
668 break;
669 }
670
671 if (Shift == ARM_AM::ror && imm == 0)
672 Shift = ARM_AM::rrx;
673
674 unsigned Op = Shift | (imm << 3);
676
677 return S;
678}
679
680static DecodeStatus DecodeSORegRegOperand(MCInst &Inst, unsigned Val,
681 uint64_t Address,
682 const MCDisassembler *Decoder) {
684
685 unsigned Rm = fieldFromInstruction(Val, 0, 4);
686 unsigned type = fieldFromInstruction(Val, 5, 2);
687 unsigned Rs = fieldFromInstruction(Val, 8, 4);
688
689 // Register-register
690 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
692 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rs, Address, Decoder)))
694
696 switch (type) {
697 case 0:
698 Shift = ARM_AM::lsl;
699 break;
700 case 1:
701 Shift = ARM_AM::lsr;
702 break;
703 case 2:
704 Shift = ARM_AM::asr;
705 break;
706 case 3:
707 Shift = ARM_AM::ror;
708 break;
709 }
710
711 Inst.addOperand(MCOperand::createImm(Shift));
712
713 return S;
714}
715
716static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Val,
717 uint64_t Address,
718 const MCDisassembler *Decoder) {
720
721 bool NeedDisjointWriteback = false;
722 MCRegister WritebackReg;
723 bool CLRM = false;
724 switch (Inst.getOpcode()) {
725 default:
726 break;
727 case ARM::LDMIA_UPD:
728 case ARM::LDMDB_UPD:
729 case ARM::LDMIB_UPD:
730 case ARM::LDMDA_UPD:
731 case ARM::t2LDMIA_UPD:
732 case ARM::t2LDMDB_UPD:
733 case ARM::t2STMIA_UPD:
734 case ARM::t2STMDB_UPD:
735 NeedDisjointWriteback = true;
736 WritebackReg = Inst.getOperand(0).getReg();
737 break;
738 case ARM::t2CLRM:
739 CLRM = true;
740 break;
741 }
742
743 // Empty register lists are not allowed.
744 if (Val == 0) return MCDisassembler::Fail;
745 for (unsigned i = 0; i < 16; ++i) {
746 if (Val & (1 << i)) {
747 if (CLRM) {
748 if (!Check(S, DecodeCLRMGPRRegisterClass(Inst, i, Address, Decoder))) {
750 }
751 } else {
752 if (!Check(S, DecodeGPRRegisterClass(Inst, i, Address, Decoder)))
754 // Writeback not allowed if Rn is in the target list.
755 if (NeedDisjointWriteback && WritebackReg == Inst.end()[-1].getReg())
757 }
758 }
759 }
760
761 return S;
762}
763
764static DecodeStatus DecodeSPRRegListOperand(MCInst &Inst, unsigned Val,
765 uint64_t Address,
766 const MCDisassembler *Decoder) {
768
769 unsigned Vd = fieldFromInstruction(Val, 8, 5);
770 unsigned regs = fieldFromInstruction(Val, 0, 8);
771
772 // In case of unpredictable encoding, tweak the operands.
773 if (regs == 0 || (Vd + regs) > 32) {
774 regs = Vd + regs > 32 ? 32 - Vd : regs;
775 regs = std::max( 1u, regs);
777 }
778
779 if (!Check(S, DecodeSPRRegisterClass(Inst, Vd, Address, Decoder)))
781 for (unsigned i = 0; i < (regs - 1); ++i) {
782 if (!Check(S, DecodeSPRRegisterClass(Inst, ++Vd, Address, Decoder)))
784 }
785
786 return S;
787}
788
789static DecodeStatus DecodeDPRRegListOperand(MCInst &Inst, unsigned Val,
790 uint64_t Address,
791 const MCDisassembler *Decoder) {
793
794 unsigned Vd = fieldFromInstruction(Val, 8, 5);
795 unsigned regs = fieldFromInstruction(Val, 1, 7);
796
797 // In case of unpredictable encoding, tweak the operands.
798 unsigned MaxReg = PermitsD32(Inst, Decoder) ? 32 : 16;
799 if (regs == 0 || (Vd + regs) > MaxReg) {
800 regs = Vd + regs > MaxReg ? MaxReg - Vd : regs;
801 regs = std::max( 1u, regs);
802 regs = std::min(MaxReg, regs);
804 }
805
806 if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder)))
808 for (unsigned i = 0; i < (regs - 1); ++i) {
809 if (!Check(S, DecodeDPRRegisterClass(Inst, ++Vd, Address, Decoder)))
811 }
812
813 return S;
814}
815
817 uint64_t Address,
818 const MCDisassembler *Decoder) {
819 // This operand encodes a mask of contiguous zeros between a specified MSB
820 // and LSB. To decode it, we create the mask of all bits MSB-and-lower,
821 // the mask of all bits LSB-and-lower, and then xor them to create
822 // the mask of that's all ones on [msb, lsb]. Finally we not it to
823 // create the final mask.
824 unsigned msb = fieldFromInstruction(Val, 5, 5);
825 unsigned lsb = fieldFromInstruction(Val, 0, 5);
826
828 if (lsb > msb) {
830 // The check above will cause the warning for the "potentially undefined
831 // instruction encoding" but we can't build a bad MCOperand value here
832 // with a lsb > msb or else printing the MCInst will cause a crash.
833 lsb = msb;
834 }
835
836 uint32_t msb_mask = 0xFFFFFFFF;
837 if (msb != 31) msb_mask = (1U << (msb+1)) - 1;
838 uint32_t lsb_mask = (1U << lsb) - 1;
839
840 Inst.addOperand(MCOperand::createImm(~(msb_mask ^ lsb_mask)));
841 return S;
842}
843
844static DecodeStatus DecodeCopMemInstruction(MCInst &Inst, unsigned Insn,
845 uint64_t Address,
846 const MCDisassembler *Decoder) {
848
849 unsigned pred = fieldFromInstruction(Insn, 28, 4);
850 unsigned CRd = fieldFromInstruction(Insn, 12, 4);
851 unsigned coproc = fieldFromInstruction(Insn, 8, 4);
852 unsigned imm = fieldFromInstruction(Insn, 0, 8);
853 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
854 unsigned U = fieldFromInstruction(Insn, 23, 1);
855 const FeatureBitset &featureBits =
856 Decoder->getSubtargetInfo().getFeatureBits();
857
858 switch (Inst.getOpcode()) {
859 case ARM::LDC_OFFSET:
860 case ARM::LDC_PRE:
861 case ARM::LDC_POST:
862 case ARM::LDC_OPTION:
863 case ARM::LDCL_OFFSET:
864 case ARM::LDCL_PRE:
865 case ARM::LDCL_POST:
866 case ARM::LDCL_OPTION:
867 case ARM::STC_OFFSET:
868 case ARM::STC_PRE:
869 case ARM::STC_POST:
870 case ARM::STC_OPTION:
871 case ARM::STCL_OFFSET:
872 case ARM::STCL_PRE:
873 case ARM::STCL_POST:
874 case ARM::STCL_OPTION:
875 case ARM::t2LDC_OFFSET:
876 case ARM::t2LDC_PRE:
877 case ARM::t2LDC_POST:
878 case ARM::t2LDC_OPTION:
879 case ARM::t2LDCL_OFFSET:
880 case ARM::t2LDCL_PRE:
881 case ARM::t2LDCL_POST:
882 case ARM::t2LDCL_OPTION:
883 case ARM::t2STC_OFFSET:
884 case ARM::t2STC_PRE:
885 case ARM::t2STC_POST:
886 case ARM::t2STC_OPTION:
887 case ARM::t2STCL_OFFSET:
888 case ARM::t2STCL_PRE:
889 case ARM::t2STCL_POST:
890 case ARM::t2STCL_OPTION:
891 case ARM::t2LDC2_OFFSET:
892 case ARM::t2LDC2L_OFFSET:
893 case ARM::t2LDC2_PRE:
894 case ARM::t2LDC2L_PRE:
895 case ARM::t2STC2_OFFSET:
896 case ARM::t2STC2L_OFFSET:
897 case ARM::t2STC2_PRE:
898 case ARM::t2STC2L_PRE:
899 case ARM::LDC2_OFFSET:
900 case ARM::LDC2L_OFFSET:
901 case ARM::LDC2_PRE:
902 case ARM::LDC2L_PRE:
903 case ARM::STC2_OFFSET:
904 case ARM::STC2L_OFFSET:
905 case ARM::STC2_PRE:
906 case ARM::STC2L_PRE:
907 case ARM::t2LDC2_OPTION:
908 case ARM::t2STC2_OPTION:
909 case ARM::t2LDC2_POST:
910 case ARM::t2LDC2L_POST:
911 case ARM::t2STC2_POST:
912 case ARM::t2STC2L_POST:
913 case ARM::LDC2_POST:
914 case ARM::LDC2L_POST:
915 case ARM::STC2_POST:
916 case ARM::STC2L_POST:
917 if (coproc == 0xA || coproc == 0xB ||
918 (featureBits[ARM::HasV8_1MMainlineOps] &&
919 (coproc == 0x8 || coproc == 0x9 || coproc == 0xA || coproc == 0xB ||
920 coproc == 0xE || coproc == 0xF)))
922 break;
923 default:
924 break;
925 }
926
927 if (featureBits[ARM::HasV8Ops] && (coproc != 14))
929
930 Inst.addOperand(MCOperand::createImm(coproc));
932 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
934
935 switch (Inst.getOpcode()) {
936 case ARM::t2LDC2_OFFSET:
937 case ARM::t2LDC2L_OFFSET:
938 case ARM::t2LDC2_PRE:
939 case ARM::t2LDC2L_PRE:
940 case ARM::t2STC2_OFFSET:
941 case ARM::t2STC2L_OFFSET:
942 case ARM::t2STC2_PRE:
943 case ARM::t2STC2L_PRE:
944 case ARM::LDC2_OFFSET:
945 case ARM::LDC2L_OFFSET:
946 case ARM::LDC2_PRE:
947 case ARM::LDC2L_PRE:
948 case ARM::STC2_OFFSET:
949 case ARM::STC2L_OFFSET:
950 case ARM::STC2_PRE:
951 case ARM::STC2L_PRE:
952 case ARM::t2LDC_OFFSET:
953 case ARM::t2LDCL_OFFSET:
954 case ARM::t2LDC_PRE:
955 case ARM::t2LDCL_PRE:
956 case ARM::t2STC_OFFSET:
957 case ARM::t2STCL_OFFSET:
958 case ARM::t2STC_PRE:
959 case ARM::t2STCL_PRE:
960 case ARM::LDC_OFFSET:
961 case ARM::LDCL_OFFSET:
962 case ARM::LDC_PRE:
963 case ARM::LDCL_PRE:
964 case ARM::STC_OFFSET:
965 case ARM::STCL_OFFSET:
966 case ARM::STC_PRE:
967 case ARM::STCL_PRE:
968 imm = ARM_AM::getAM5Opc(U ? ARM_AM::add : ARM_AM::sub, imm);
970 break;
971 case ARM::t2LDC2_POST:
972 case ARM::t2LDC2L_POST:
973 case ARM::t2STC2_POST:
974 case ARM::t2STC2L_POST:
975 case ARM::LDC2_POST:
976 case ARM::LDC2L_POST:
977 case ARM::STC2_POST:
978 case ARM::STC2L_POST:
979 case ARM::t2LDC_POST:
980 case ARM::t2LDCL_POST:
981 case ARM::t2STC_POST:
982 case ARM::t2STCL_POST:
983 case ARM::LDC_POST:
984 case ARM::LDCL_POST:
985 case ARM::STC_POST:
986 case ARM::STCL_POST:
987 imm |= U << 8;
988 [[fallthrough]];
989 default:
990 // The 'option' variant doesn't encode 'U' in the immediate since
991 // the immediate is unsigned [0,255].
993 break;
994 }
995
996 switch (Inst.getOpcode()) {
997 case ARM::LDC_OFFSET:
998 case ARM::LDC_PRE:
999 case ARM::LDC_POST:
1000 case ARM::LDC_OPTION:
1001 case ARM::LDCL_OFFSET:
1002 case ARM::LDCL_PRE:
1003 case ARM::LDCL_POST:
1004 case ARM::LDCL_OPTION:
1005 case ARM::STC_OFFSET:
1006 case ARM::STC_PRE:
1007 case ARM::STC_POST:
1008 case ARM::STC_OPTION:
1009 case ARM::STCL_OFFSET:
1010 case ARM::STCL_PRE:
1011 case ARM::STCL_POST:
1012 case ARM::STCL_OPTION:
1013 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1014 return MCDisassembler::Fail;
1015 break;
1016 default:
1017 break;
1018 }
1019
1020 return S;
1021}
1022
1023static DecodeStatus
1024DecodeAddrMode2IdxInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
1025 const MCDisassembler *Decoder) {
1027
1028 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
1029 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
1030 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
1031 unsigned imm = fieldFromInstruction(Insn, 0, 12);
1032 unsigned pred = fieldFromInstruction(Insn, 28, 4);
1033 unsigned reg = fieldFromInstruction(Insn, 25, 1);
1034 unsigned P = fieldFromInstruction(Insn, 24, 1);
1035 unsigned W = fieldFromInstruction(Insn, 21, 1);
1036
1037 // On stores, the writeback operand precedes Rt.
1038 switch (Inst.getOpcode()) {
1039 case ARM::STR_POST_IMM:
1040 case ARM::STR_POST_REG:
1041 case ARM::STRB_POST_IMM:
1042 case ARM::STRB_POST_REG:
1043 case ARM::STRT_POST_REG:
1044 case ARM::STRT_POST_IMM:
1045 case ARM::STRBT_POST_REG:
1046 case ARM::STRBT_POST_IMM:
1047 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1048 return MCDisassembler::Fail;
1049 break;
1050 default:
1051 break;
1052 }
1053
1054 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
1055 return MCDisassembler::Fail;
1056
1057 // On loads, the writeback operand comes after Rt.
1058 switch (Inst.getOpcode()) {
1059 case ARM::LDR_POST_IMM:
1060 case ARM::LDR_POST_REG:
1061 case ARM::LDRB_POST_IMM:
1062 case ARM::LDRB_POST_REG:
1063 case ARM::LDRBT_POST_REG:
1064 case ARM::LDRBT_POST_IMM:
1065 case ARM::LDRT_POST_REG:
1066 case ARM::LDRT_POST_IMM:
1067 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1068 return MCDisassembler::Fail;
1069 break;
1070 default:
1071 break;
1072 }
1073
1074 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1075 return MCDisassembler::Fail;
1076
1078 if (!fieldFromInstruction(Insn, 23, 1))
1079 Op = ARM_AM::sub;
1080
1081 bool writeback = (P == 0) || (W == 1);
1082 unsigned idx_mode = 0;
1083 if (P && writeback)
1084 idx_mode = ARMII::IndexModePre;
1085 else if (!P && writeback)
1086 idx_mode = ARMII::IndexModePost;
1087
1088 if (writeback && (Rn == 15 || Rn == Rt))
1089 S = MCDisassembler::SoftFail; // UNPREDICTABLE
1090
1091 if (reg) {
1092 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
1093 return MCDisassembler::Fail;
1095 switch( fieldFromInstruction(Insn, 5, 2)) {
1096 case 0:
1097 Opc = ARM_AM::lsl;
1098 break;
1099 case 1:
1100 Opc = ARM_AM::lsr;
1101 break;
1102 case 2:
1103 Opc = ARM_AM::asr;
1104 break;
1105 case 3:
1106 Opc = ARM_AM::ror;
1107 break;
1108 default:
1109 return MCDisassembler::Fail;
1110 }
1111 unsigned amt = fieldFromInstruction(Insn, 7, 5);
1112 if (Opc == ARM_AM::ror && amt == 0)
1113 Opc = ARM_AM::rrx;
1114 unsigned imm = ARM_AM::getAM2Opc(Op, amt, Opc, idx_mode);
1115
1117 } else {
1119 unsigned tmp = ARM_AM::getAM2Opc(Op, imm, ARM_AM::lsl, idx_mode);
1121 }
1122
1123 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1124 return MCDisassembler::Fail;
1125
1126 return S;
1127}
1128
1129static DecodeStatus DecodeSORegMemOperand(MCInst &Inst, unsigned Val,
1130 uint64_t Address,
1131 const MCDisassembler *Decoder) {
1133
1134 unsigned Rn = fieldFromInstruction(Val, 13, 4);
1135 unsigned Rm = fieldFromInstruction(Val, 0, 4);
1136 unsigned type = fieldFromInstruction(Val, 5, 2);
1137 unsigned imm = fieldFromInstruction(Val, 7, 5);
1138 unsigned U = fieldFromInstruction(Val, 12, 1);
1139
1141 switch (type) {
1142 case 0:
1143 ShOp = ARM_AM::lsl;
1144 break;
1145 case 1:
1146 ShOp = ARM_AM::lsr;
1147 break;
1148 case 2:
1149 ShOp = ARM_AM::asr;
1150 break;
1151 case 3:
1152 ShOp = ARM_AM::ror;
1153 break;
1154 }
1155
1156 if (ShOp == ARM_AM::ror && imm == 0)
1157 ShOp = ARM_AM::rrx;
1158
1159 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1160 return MCDisassembler::Fail;
1161 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
1162 return MCDisassembler::Fail;
1163 unsigned shift;
1164 if (U)
1165 shift = ARM_AM::getAM2Opc(ARM_AM::add, imm, ShOp);
1166 else
1167 shift = ARM_AM::getAM2Opc(ARM_AM::sub, imm, ShOp);
1168 Inst.addOperand(MCOperand::createImm(shift));
1169
1170 return S;
1171}
1172
1173static DecodeStatus DecodeTSBInstruction(MCInst &Inst, unsigned Insn,
1174 uint64_t Address,
1175 const MCDisassembler *Decoder) {
1176 if (Inst.getOpcode() != ARM::TSB && Inst.getOpcode() != ARM::t2TSB)
1177 return MCDisassembler::Fail;
1178
1179 // The "csync" operand is not encoded into the "tsb" instruction (as this is
1180 // the only available operand), but LLVM expects the instruction to have one
1181 // operand, so we need to add the csync when decoding.
1184}
1185
1187 uint64_t Address,
1188 const MCDisassembler *Decoder) {
1190
1191 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
1192 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
1193 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
1194 unsigned type = fieldFromInstruction(Insn, 22, 1);
1195 unsigned imm = fieldFromInstruction(Insn, 8, 4);
1196 unsigned U = ((~fieldFromInstruction(Insn, 23, 1)) & 1) << 8;
1197 unsigned pred = fieldFromInstruction(Insn, 28, 4);
1198 unsigned W = fieldFromInstruction(Insn, 21, 1);
1199 unsigned P = fieldFromInstruction(Insn, 24, 1);
1200 unsigned Rt2 = Rt + 1;
1201
1202 bool writeback = (W == 1) | (P == 0);
1203
1204 // For {LD,ST}RD, Rt must be even, else undefined.
1205 switch (Inst.getOpcode()) {
1206 case ARM::STRD:
1207 case ARM::STRD_PRE:
1208 case ARM::STRD_POST:
1209 case ARM::LDRD:
1210 case ARM::LDRD_PRE:
1211 case ARM::LDRD_POST:
1212 if (Rt & 0x1) S = MCDisassembler::SoftFail;
1213 break;
1214 default:
1215 break;
1216 }
1217 switch (Inst.getOpcode()) {
1218 case ARM::STRD:
1219 case ARM::STRD_PRE:
1220 case ARM::STRD_POST:
1221 if (P == 0 && W == 1)
1223
1224 if (writeback && (Rn == 15 || Rn == Rt || Rn == Rt2))
1226 if (type && Rm == 15)
1228 if (Rt2 == 15)
1230 if (!type && fieldFromInstruction(Insn, 8, 4))
1232 break;
1233 case ARM::STRH:
1234 case ARM::STRH_PRE:
1235 case ARM::STRH_POST:
1236 if (Rt == 15)
1238 if (writeback && (Rn == 15 || Rn == Rt))
1240 if (!type && Rm == 15)
1242 break;
1243 case ARM::LDRD:
1244 case ARM::LDRD_PRE:
1245 case ARM::LDRD_POST:
1246 if (type && Rn == 15) {
1247 if (Rt2 == 15)
1249 break;
1250 }
1251 if (P == 0 && W == 1)
1253 if (!type && (Rt2 == 15 || Rm == 15 || Rm == Rt || Rm == Rt2))
1255 if (!type && writeback && Rn == 15)
1257 if (writeback && (Rn == Rt || Rn == Rt2))
1259 break;
1260 case ARM::LDRH:
1261 case ARM::LDRH_PRE:
1262 case ARM::LDRH_POST:
1263 if (type && Rn == 15) {
1264 if (Rt == 15)
1266 break;
1267 }
1268 if (Rt == 15)
1270 if (!type && Rm == 15)
1272 if (!type && writeback && (Rn == 15 || Rn == Rt))
1274 break;
1275 case ARM::LDRSH:
1276 case ARM::LDRSH_PRE:
1277 case ARM::LDRSH_POST:
1278 case ARM::LDRSB:
1279 case ARM::LDRSB_PRE:
1280 case ARM::LDRSB_POST:
1281 if (type && Rn == 15) {
1282 if (Rt == 15)
1284 break;
1285 }
1286 if (type && (Rt == 15 || (writeback && Rn == Rt)))
1288 if (!type && (Rt == 15 || Rm == 15))
1290 if (!type && writeback && (Rn == 15 || Rn == Rt))
1292 break;
1293 default:
1294 break;
1295 }
1296
1297 if (writeback) { // Writeback
1298 if (P)
1299 U |= ARMII::IndexModePre << 9;
1300 else
1301 U |= ARMII::IndexModePost << 9;
1302
1303 // On stores, the writeback operand precedes Rt.
1304 switch (Inst.getOpcode()) {
1305 case ARM::STRD:
1306 case ARM::STRD_PRE:
1307 case ARM::STRD_POST:
1308 case ARM::STRH:
1309 case ARM::STRH_PRE:
1310 case ARM::STRH_POST:
1311 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1312 return MCDisassembler::Fail;
1313 break;
1314 default:
1315 break;
1316 }
1317 }
1318
1319 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
1320 return MCDisassembler::Fail;
1321 switch (Inst.getOpcode()) {
1322 case ARM::STRD:
1323 case ARM::STRD_PRE:
1324 case ARM::STRD_POST:
1325 case ARM::LDRD:
1326 case ARM::LDRD_PRE:
1327 case ARM::LDRD_POST:
1328 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder)))
1329 return MCDisassembler::Fail;
1330 break;
1331 default:
1332 break;
1333 }
1334
1335 if (writeback) {
1336 // On loads, the writeback operand comes after Rt.
1337 switch (Inst.getOpcode()) {
1338 case ARM::LDRD:
1339 case ARM::LDRD_PRE:
1340 case ARM::LDRD_POST:
1341 case ARM::LDRH:
1342 case ARM::LDRH_PRE:
1343 case ARM::LDRH_POST:
1344 case ARM::LDRSH:
1345 case ARM::LDRSH_PRE:
1346 case ARM::LDRSH_POST:
1347 case ARM::LDRSB:
1348 case ARM::LDRSB_PRE:
1349 case ARM::LDRSB_POST:
1350 case ARM::LDRHTr:
1351 case ARM::LDRSBTr:
1352 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1353 return MCDisassembler::Fail;
1354 break;
1355 default:
1356 break;
1357 }
1358 }
1359
1360 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1361 return MCDisassembler::Fail;
1362
1363 if (type) {
1365 Inst.addOperand(MCOperand::createImm(U | (imm << 4) | Rm));
1366 } else {
1367 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
1368 return MCDisassembler::Fail;
1370 }
1371
1372 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1373 return MCDisassembler::Fail;
1374
1375 return S;
1376}
1377
1378static DecodeStatus DecodeRFEInstruction(MCInst &Inst, unsigned Insn,
1379 uint64_t Address,
1380 const MCDisassembler *Decoder) {
1382
1383 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
1384 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1385 return MCDisassembler::Fail;
1386
1387 return S;
1388}
1389
1390static DecodeStatus DecodeCPSInstruction(MCInst &Inst, unsigned Insn,
1391 uint64_t Address,
1392 const MCDisassembler *Decoder) {
1393 unsigned imod = fieldFromInstruction(Insn, 18, 2);
1394 unsigned M = fieldFromInstruction(Insn, 17, 1);
1395 unsigned iflags = fieldFromInstruction(Insn, 6, 3);
1396 unsigned mode = fieldFromInstruction(Insn, 0, 5);
1397
1399
1400 // This decoder is called from multiple location that do not check
1401 // the full encoding is valid before they do.
1402 if (fieldFromInstruction(Insn, 5, 1) != 0 ||
1403 fieldFromInstruction(Insn, 16, 1) != 0 ||
1404 fieldFromInstruction(Insn, 20, 8) != 0x10)
1405 return MCDisassembler::Fail;
1406
1407 // imod == '01' --> UNPREDICTABLE
1408 // NOTE: Even though this is technically UNPREDICTABLE, we choose to
1409 // return failure here. The '01' imod value is unprintable, so there's
1410 // nothing useful we could do even if we returned UNPREDICTABLE.
1411
1412 if (imod == 1) return MCDisassembler::Fail;
1413
1414 if (imod && M) {
1415 Inst.setOpcode(ARM::CPS3p);
1416 Inst.addOperand(MCOperand::createImm(imod));
1417 Inst.addOperand(MCOperand::createImm(iflags));
1419 } else if (imod && !M) {
1420 Inst.setOpcode(ARM::CPS2p);
1421 Inst.addOperand(MCOperand::createImm(imod));
1422 Inst.addOperand(MCOperand::createImm(iflags));
1424 } else if (!imod && M) {
1425 Inst.setOpcode(ARM::CPS1p);
1427 if (iflags) S = MCDisassembler::SoftFail;
1428 } else {
1429 // imod == '00' && M == '0' --> UNPREDICTABLE
1430 Inst.setOpcode(ARM::CPS1p);
1433 }
1434
1435 return S;
1436}
1437
1438static DecodeStatus DecodeQADDInstruction(MCInst &Inst, unsigned Insn,
1439 uint64_t Address,
1440 const MCDisassembler *Decoder) {
1442
1443 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
1444 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
1445 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
1446 unsigned pred = fieldFromInstruction(Insn, 28, 4);
1447
1448 if (pred == 0xF)
1449 return DecodeCPSInstruction(Inst, Insn, Address, Decoder);
1450
1451 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)))
1452 return MCDisassembler::Fail;
1453 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
1454 return MCDisassembler::Fail;
1455 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
1456 return MCDisassembler::Fail;
1457 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1458 return MCDisassembler::Fail;
1459 return S;
1460}
1461
1462static DecodeStatus
1464 uint64_t Address,
1465 const MCDisassembler *Decoder) {
1467
1468 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
1469 unsigned pred = fieldFromInstruction(Insn, 28, 4);
1470 unsigned reglist = fieldFromInstruction(Insn, 0, 16);
1471
1472 if (pred == 0xF) {
1473 // Ambiguous with RFE and SRS
1474 switch (Inst.getOpcode()) {
1475 case ARM::LDMDA:
1476 Inst.setOpcode(ARM::RFEDA);
1477 break;
1478 case ARM::LDMDA_UPD:
1479 Inst.setOpcode(ARM::RFEDA_UPD);
1480 break;
1481 case ARM::LDMDB:
1482 Inst.setOpcode(ARM::RFEDB);
1483 break;
1484 case ARM::LDMDB_UPD:
1485 Inst.setOpcode(ARM::RFEDB_UPD);
1486 break;
1487 case ARM::LDMIA:
1488 Inst.setOpcode(ARM::RFEIA);
1489 break;
1490 case ARM::LDMIA_UPD:
1491 Inst.setOpcode(ARM::RFEIA_UPD);
1492 break;
1493 case ARM::LDMIB:
1494 Inst.setOpcode(ARM::RFEIB);
1495 break;
1496 case ARM::LDMIB_UPD:
1497 Inst.setOpcode(ARM::RFEIB_UPD);
1498 break;
1499 case ARM::STMDA:
1500 Inst.setOpcode(ARM::SRSDA);
1501 break;
1502 case ARM::STMDA_UPD:
1503 Inst.setOpcode(ARM::SRSDA_UPD);
1504 break;
1505 case ARM::STMDB:
1506 Inst.setOpcode(ARM::SRSDB);
1507 break;
1508 case ARM::STMDB_UPD:
1509 Inst.setOpcode(ARM::SRSDB_UPD);
1510 break;
1511 case ARM::STMIA:
1512 Inst.setOpcode(ARM::SRSIA);
1513 break;
1514 case ARM::STMIA_UPD:
1515 Inst.setOpcode(ARM::SRSIA_UPD);
1516 break;
1517 case ARM::STMIB:
1518 Inst.setOpcode(ARM::SRSIB);
1519 break;
1520 case ARM::STMIB_UPD:
1521 Inst.setOpcode(ARM::SRSIB_UPD);
1522 break;
1523 default:
1524 return MCDisassembler::Fail;
1525 }
1526
1527 // For stores (which become SRS's, the only operand is the mode.
1528 if (fieldFromInstruction(Insn, 20, 1) == 0) {
1529 // Check SRS encoding constraints
1530 if (!(fieldFromInstruction(Insn, 22, 1) == 1 &&
1531 fieldFromInstruction(Insn, 20, 1) == 0))
1532 return MCDisassembler::Fail;
1533
1534 Inst.addOperand(
1536 return S;
1537 }
1538
1539 return DecodeRFEInstruction(Inst, Insn, Address, Decoder);
1540 }
1541
1542 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1543 return MCDisassembler::Fail;
1544 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1545 return MCDisassembler::Fail; // Tied
1546 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1547 return MCDisassembler::Fail;
1548 if (!Check(S, DecodeRegListOperand(Inst, reglist, Address, Decoder)))
1549 return MCDisassembler::Fail;
1550
1551 return S;
1552}
1553
1554// Check for UNPREDICTABLE predicated ESB instruction
1555static DecodeStatus DecodeHINTInstruction(MCInst &Inst, unsigned Insn,
1556 uint64_t Address,
1557 const MCDisassembler *Decoder) {
1558 unsigned pred = fieldFromInstruction(Insn, 28, 4);
1559 unsigned imm8 = fieldFromInstruction(Insn, 0, 8);
1560 const FeatureBitset &FeatureBits =
1561 Decoder->getSubtargetInfo().getFeatureBits();
1562
1564
1565 Inst.addOperand(MCOperand::createImm(imm8));
1566
1567 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1568 return MCDisassembler::Fail;
1569
1570 // ESB is unpredictable if pred != AL. Without the RAS extension, it is a NOP,
1571 // so all predicates should be allowed.
1572 if (imm8 == 0x10 && pred != 0xe && ((FeatureBits[ARM::FeatureRAS]) != 0))
1574
1575 return S;
1576}
1577
1578static DecodeStatus DecodeT2CPSInstruction(MCInst &Inst, unsigned Insn,
1579 uint64_t Address,
1580 const MCDisassembler *Decoder) {
1581 unsigned imod = fieldFromInstruction(Insn, 9, 2);
1582 unsigned M = fieldFromInstruction(Insn, 8, 1);
1583 unsigned iflags = fieldFromInstruction(Insn, 5, 3);
1584 unsigned mode = fieldFromInstruction(Insn, 0, 5);
1585
1587
1588 // imod == '01' --> UNPREDICTABLE
1589 // NOTE: Even though this is technically UNPREDICTABLE, we choose to
1590 // return failure here. The '01' imod value is unprintable, so there's
1591 // nothing useful we could do even if we returned UNPREDICTABLE.
1592
1593 if (imod == 1) return MCDisassembler::Fail;
1594
1595 if (imod && M) {
1596 Inst.setOpcode(ARM::t2CPS3p);
1597 Inst.addOperand(MCOperand::createImm(imod));
1598 Inst.addOperand(MCOperand::createImm(iflags));
1600 } else if (imod && !M) {
1601 Inst.setOpcode(ARM::t2CPS2p);
1602 Inst.addOperand(MCOperand::createImm(imod));
1603 Inst.addOperand(MCOperand::createImm(iflags));
1605 } else if (!imod && M) {
1606 Inst.setOpcode(ARM::t2CPS1p);
1608 if (iflags) S = MCDisassembler::SoftFail;
1609 } else {
1610 // imod == '00' && M == '0' --> this is a HINT instruction
1611 int imm = fieldFromInstruction(Insn, 0, 8);
1612 // HINT are defined only for immediate in [0..4]
1613 if(imm > 4) return MCDisassembler::Fail;
1614 Inst.setOpcode(ARM::t2HINT);
1616 }
1617
1618 return S;
1619}
1620
1621static DecodeStatus
1622DecodeT2HintSpaceInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
1623 const MCDisassembler *Decoder) {
1624 unsigned imm = fieldFromInstruction(Insn, 0, 8);
1625
1626 unsigned Opcode = ARM::t2HINT;
1627
1628 if (imm == 0x0D) {
1629 Opcode = ARM::t2PACBTI;
1630 } else if (imm == 0x1D) {
1631 Opcode = ARM::t2PAC;
1632 } else if (imm == 0x2D) {
1633 Opcode = ARM::t2AUT;
1634 } else if (imm == 0x0F) {
1635 Opcode = ARM::t2BTI;
1636 }
1637
1638 Inst.setOpcode(Opcode);
1639 if (Opcode == ARM::t2HINT) {
1641 }
1642
1644}
1645
1647 uint64_t Address,
1648 const MCDisassembler *Decoder) {
1650
1651 unsigned Rd = fieldFromInstruction(Insn, 8, 4);
1652 unsigned imm = 0;
1653
1654 imm |= (fieldFromInstruction(Insn, 0, 8) << 0);
1655 imm |= (fieldFromInstruction(Insn, 12, 3) << 8);
1656 imm |= (fieldFromInstruction(Insn, 16, 4) << 12);
1657 imm |= (fieldFromInstruction(Insn, 26, 1) << 11);
1658
1659 if (Inst.getOpcode() == ARM::t2MOVTi16)
1660 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder)))
1661 return MCDisassembler::Fail;
1662 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder)))
1663 return MCDisassembler::Fail;
1664
1665 if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder))
1667
1668 return S;
1669}
1670
1672 uint64_t Address,
1673 const MCDisassembler *Decoder) {
1675
1676 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
1677 unsigned pred = fieldFromInstruction(Insn, 28, 4);
1678 unsigned imm = 0;
1679
1680 imm |= (fieldFromInstruction(Insn, 0, 12) << 0);
1681 imm |= (fieldFromInstruction(Insn, 16, 4) << 12);
1682
1683 if (Inst.getOpcode() == ARM::MOVTi16)
1684 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)))
1685 return MCDisassembler::Fail;
1686
1687 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)))
1688 return MCDisassembler::Fail;
1689
1690 if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder))
1692
1693 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1694 return MCDisassembler::Fail;
1695
1696 return S;
1697}
1698
1699static DecodeStatus DecodeSMLAInstruction(MCInst &Inst, unsigned Insn,
1700 uint64_t Address,
1701 const MCDisassembler *Decoder) {
1703
1704 unsigned Rd = fieldFromInstruction(Insn, 16, 4);
1705 unsigned Rn = fieldFromInstruction(Insn, 0, 4);
1706 unsigned Rm = fieldFromInstruction(Insn, 8, 4);
1707 unsigned Ra = fieldFromInstruction(Insn, 12, 4);
1708 unsigned pred = fieldFromInstruction(Insn, 28, 4);
1709
1710 if (pred == 0xF)
1711 return DecodeCPSInstruction(Inst, Insn, Address, Decoder);
1712
1713 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)))
1714 return MCDisassembler::Fail;
1715 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
1716 return MCDisassembler::Fail;
1717 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
1718 return MCDisassembler::Fail;
1719 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Ra, Address, Decoder)))
1720 return MCDisassembler::Fail;
1721
1722 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1723 return MCDisassembler::Fail;
1724
1725 return S;
1726}
1727
1728static DecodeStatus DecodeSETPANInstruction(MCInst &Inst, unsigned Insn,
1729 uint64_t Address,
1730 const MCDisassembler *Decoder) {
1732
1733 unsigned Imm = fieldFromInstruction(Insn, 9, 1);
1734
1735 const FeatureBitset &FeatureBits =
1736 Decoder->getSubtargetInfo().getFeatureBits();
1737
1738 if (!FeatureBits[ARM::HasV8_1aOps] ||
1739 !FeatureBits[ARM::HasV8Ops])
1740 return MCDisassembler::Fail;
1741
1742 // Decoder can be called from DecodeTST, which does not check the full
1743 // encoding is valid.
1744 if (fieldFromInstruction(Insn, 20,12) != 0xf11 ||
1745 fieldFromInstruction(Insn, 4,4) != 0)
1746 return MCDisassembler::Fail;
1747 if (fieldFromInstruction(Insn, 10,10) != 0 ||
1748 fieldFromInstruction(Insn, 0,4) != 0)
1750
1751 Inst.setOpcode(ARM::SETPAN);
1753
1754 return S;
1755}
1756
1757static DecodeStatus DecodeTSTInstruction(MCInst &Inst, unsigned Insn,
1758 uint64_t Address,
1759 const MCDisassembler *Decoder) {
1761
1762 unsigned Pred = fieldFromInstruction(Insn, 28, 4);
1763 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
1764 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
1765
1766 if (Pred == 0xF)
1767 return DecodeSETPANInstruction(Inst, Insn, Address, Decoder);
1768
1769 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1770 return MCDisassembler::Fail;
1771 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
1772 return MCDisassembler::Fail;
1773 if (!Check(S, DecodePredicateOperand(Inst, Pred, Address, Decoder)))
1774 return MCDisassembler::Fail;
1775
1776 return S;
1777}
1778
1780 uint64_t Address,
1781 const MCDisassembler *Decoder) {
1783
1784 unsigned add = fieldFromInstruction(Val, 12, 1);
1785 unsigned imm = fieldFromInstruction(Val, 0, 12);
1786 unsigned Rn = fieldFromInstruction(Val, 13, 4);
1787
1788 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1789 return MCDisassembler::Fail;
1790
1791 if (!add) imm *= -1;
1792 if (imm == 0 && !add) imm = INT32_MIN;
1794 if (Rn == 15)
1795 tryAddingPcLoadReferenceComment(Address, Address + imm + 8, Decoder);
1796
1797 return S;
1798}
1799
1800static DecodeStatus DecodeAddrMode5Operand(MCInst &Inst, unsigned Val,
1801 uint64_t Address,
1802 const MCDisassembler *Decoder) {
1804
1805 unsigned Rn = fieldFromInstruction(Val, 9, 4);
1806 // U == 1 to add imm, 0 to subtract it.
1807 unsigned U = fieldFromInstruction(Val, 8, 1);
1808 unsigned imm = fieldFromInstruction(Val, 0, 8);
1809
1810 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1811 return MCDisassembler::Fail;
1812
1813 if (U)
1815 else
1817
1818 return S;
1819}
1820
1822 uint64_t Address,
1823 const MCDisassembler *Decoder) {
1825
1826 unsigned Rn = fieldFromInstruction(Val, 9, 4);
1827 // U == 1 to add imm, 0 to subtract it.
1828 unsigned U = fieldFromInstruction(Val, 8, 1);
1829 unsigned imm = fieldFromInstruction(Val, 0, 8);
1830
1831 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1832 return MCDisassembler::Fail;
1833
1834 if (U)
1836 else
1838
1839 return S;
1840}
1841
1842static DecodeStatus DecodeAddrMode7Operand(MCInst &Inst, unsigned Val,
1843 uint64_t Address,
1844 const MCDisassembler *Decoder) {
1845 return DecodeGPRRegisterClass(Inst, Val, Address, Decoder);
1846}
1847
1848static DecodeStatus DecodeT2BInstruction(MCInst &Inst, unsigned Insn,
1849 uint64_t Address,
1850 const MCDisassembler *Decoder) {
1852
1853 // Note the J1 and J2 values are from the encoded instruction. So here
1854 // change them to I1 and I2 values via as documented:
1855 // I1 = NOT(J1 EOR S);
1856 // I2 = NOT(J2 EOR S);
1857 // and build the imm32 with one trailing zero as documented:
1858 // imm32 = SignExtend(S:I1:I2:imm10:imm11:'0', 32);
1859 unsigned S = fieldFromInstruction(Insn, 26, 1);
1860 unsigned J1 = fieldFromInstruction(Insn, 13, 1);
1861 unsigned J2 = fieldFromInstruction(Insn, 11, 1);
1862 unsigned I1 = !(J1 ^ S);
1863 unsigned I2 = !(J2 ^ S);
1864 unsigned imm10 = fieldFromInstruction(Insn, 16, 10);
1865 unsigned imm11 = fieldFromInstruction(Insn, 0, 11);
1866 unsigned tmp = (S << 23) | (I1 << 22) | (I2 << 21) | (imm10 << 11) | imm11;
1867 int imm32 = SignExtend32<25>(tmp << 1);
1868 if (!tryAddingSymbolicOperand(Address, Address + imm32 + 4,
1869 true, 4, Inst, Decoder))
1870 Inst.addOperand(MCOperand::createImm(imm32));
1871
1872 return Status;
1873}
1874
1876 uint64_t Address,
1877 const MCDisassembler *Decoder) {
1879
1880 unsigned pred = fieldFromInstruction(Insn, 28, 4);
1881 unsigned imm = fieldFromInstruction(Insn, 0, 24) << 2;
1882
1883 if (pred == 0xF) {
1884 Inst.setOpcode(ARM::BLXi);
1885 imm |= fieldFromInstruction(Insn, 24, 1) << 1;
1886 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<26>(imm) + 8,
1887 true, 4, Inst, Decoder))
1889 return S;
1890 }
1891
1892 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<26>(imm) + 8,
1893 true, 4, Inst, Decoder))
1895
1896 // We already have BL_pred for BL w/ predicate, no need to add addition
1897 // predicate opreands for BL
1898 if (Inst.getOpcode() != ARM::BL)
1899 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1900 return MCDisassembler::Fail;
1901
1902 return S;
1903}
1904
1905static DecodeStatus DecodeAddrMode6Operand(MCInst &Inst, unsigned Val,
1906 uint64_t Address,
1907 const MCDisassembler *Decoder) {
1909
1910 unsigned Rm = fieldFromInstruction(Val, 0, 4);
1911 unsigned align = fieldFromInstruction(Val, 4, 2);
1912
1913 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
1914 return MCDisassembler::Fail;
1915 if (!align)
1917 else
1918 Inst.addOperand(MCOperand::createImm(4 << align));
1919
1920 return S;
1921}
1922
1923static DecodeStatus DecodeVLDInstruction(MCInst &Inst, unsigned Insn,
1924 uint64_t Address,
1925 const MCDisassembler *Decoder) {
1927
1928 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
1929 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
1930 unsigned wb = fieldFromInstruction(Insn, 16, 4);
1931 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
1932 Rn |= fieldFromInstruction(Insn, 4, 2) << 4;
1933 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
1934
1935 // First output register
1936 switch (Inst.getOpcode()) {
1937 case ARM::VLD1q16: case ARM::VLD1q32: case ARM::VLD1q64: case ARM::VLD1q8:
1938 case ARM::VLD1q16wb_fixed: case ARM::VLD1q16wb_register:
1939 case ARM::VLD1q32wb_fixed: case ARM::VLD1q32wb_register:
1940 case ARM::VLD1q64wb_fixed: case ARM::VLD1q64wb_register:
1941 case ARM::VLD1q8wb_fixed: case ARM::VLD1q8wb_register:
1942 case ARM::VLD2d16: case ARM::VLD2d32: case ARM::VLD2d8:
1943 case ARM::VLD2d16wb_fixed: case ARM::VLD2d16wb_register:
1944 case ARM::VLD2d32wb_fixed: case ARM::VLD2d32wb_register:
1945 case ARM::VLD2d8wb_fixed: case ARM::VLD2d8wb_register:
1946 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder)))
1947 return MCDisassembler::Fail;
1948 break;
1949 case ARM::VLD2b16:
1950 case ARM::VLD2b32:
1951 case ARM::VLD2b8:
1952 case ARM::VLD2b16wb_fixed:
1953 case ARM::VLD2b16wb_register:
1954 case ARM::VLD2b32wb_fixed:
1955 case ARM::VLD2b32wb_register:
1956 case ARM::VLD2b8wb_fixed:
1957 case ARM::VLD2b8wb_register:
1958 if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder)))
1959 return MCDisassembler::Fail;
1960 break;
1961 default:
1962 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
1963 return MCDisassembler::Fail;
1964 }
1965
1966 // Second output register
1967 switch (Inst.getOpcode()) {
1968 case ARM::VLD3d8:
1969 case ARM::VLD3d16:
1970 case ARM::VLD3d32:
1971 case ARM::VLD3d8_UPD:
1972 case ARM::VLD3d16_UPD:
1973 case ARM::VLD3d32_UPD:
1974 case ARM::VLD4d8:
1975 case ARM::VLD4d16:
1976 case ARM::VLD4d32:
1977 case ARM::VLD4d8_UPD:
1978 case ARM::VLD4d16_UPD:
1979 case ARM::VLD4d32_UPD:
1980 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder)))
1981 return MCDisassembler::Fail;
1982 break;
1983 case ARM::VLD3q8:
1984 case ARM::VLD3q16:
1985 case ARM::VLD3q32:
1986 case ARM::VLD3q8_UPD:
1987 case ARM::VLD3q16_UPD:
1988 case ARM::VLD3q32_UPD:
1989 case ARM::VLD4q8:
1990 case ARM::VLD4q16:
1991 case ARM::VLD4q32:
1992 case ARM::VLD4q8_UPD:
1993 case ARM::VLD4q16_UPD:
1994 case ARM::VLD4q32_UPD:
1995 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
1996 return MCDisassembler::Fail;
1997 break;
1998 default:
1999 break;
2000 }
2001
2002 // Third output register
2003 switch(Inst.getOpcode()) {
2004 case ARM::VLD3d8:
2005 case ARM::VLD3d16:
2006 case ARM::VLD3d32:
2007 case ARM::VLD3d8_UPD:
2008 case ARM::VLD3d16_UPD:
2009 case ARM::VLD3d32_UPD:
2010 case ARM::VLD4d8:
2011 case ARM::VLD4d16:
2012 case ARM::VLD4d32:
2013 case ARM::VLD4d8_UPD:
2014 case ARM::VLD4d16_UPD:
2015 case ARM::VLD4d32_UPD:
2016 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
2017 return MCDisassembler::Fail;
2018 break;
2019 case ARM::VLD3q8:
2020 case ARM::VLD3q16:
2021 case ARM::VLD3q32:
2022 case ARM::VLD3q8_UPD:
2023 case ARM::VLD3q16_UPD:
2024 case ARM::VLD3q32_UPD:
2025 case ARM::VLD4q8:
2026 case ARM::VLD4q16:
2027 case ARM::VLD4q32:
2028 case ARM::VLD4q8_UPD:
2029 case ARM::VLD4q16_UPD:
2030 case ARM::VLD4q32_UPD:
2031 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder)))
2032 return MCDisassembler::Fail;
2033 break;
2034 default:
2035 break;
2036 }
2037
2038 // Fourth output register
2039 switch (Inst.getOpcode()) {
2040 case ARM::VLD4d8:
2041 case ARM::VLD4d16:
2042 case ARM::VLD4d32:
2043 case ARM::VLD4d8_UPD:
2044 case ARM::VLD4d16_UPD:
2045 case ARM::VLD4d32_UPD:
2046 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder)))
2047 return MCDisassembler::Fail;
2048 break;
2049 case ARM::VLD4q8:
2050 case ARM::VLD4q16:
2051 case ARM::VLD4q32:
2052 case ARM::VLD4q8_UPD:
2053 case ARM::VLD4q16_UPD:
2054 case ARM::VLD4q32_UPD:
2055 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder)))
2056 return MCDisassembler::Fail;
2057 break;
2058 default:
2059 break;
2060 }
2061
2062 // Writeback operand
2063 switch (Inst.getOpcode()) {
2064 case ARM::VLD1d8wb_fixed:
2065 case ARM::VLD1d16wb_fixed:
2066 case ARM::VLD1d32wb_fixed:
2067 case ARM::VLD1d64wb_fixed:
2068 case ARM::VLD1d8wb_register:
2069 case ARM::VLD1d16wb_register:
2070 case ARM::VLD1d32wb_register:
2071 case ARM::VLD1d64wb_register:
2072 case ARM::VLD1q8wb_fixed:
2073 case ARM::VLD1q16wb_fixed:
2074 case ARM::VLD1q32wb_fixed:
2075 case ARM::VLD1q64wb_fixed:
2076 case ARM::VLD1q8wb_register:
2077 case ARM::VLD1q16wb_register:
2078 case ARM::VLD1q32wb_register:
2079 case ARM::VLD1q64wb_register:
2080 case ARM::VLD1d8Twb_fixed:
2081 case ARM::VLD1d8Twb_register:
2082 case ARM::VLD1d16Twb_fixed:
2083 case ARM::VLD1d16Twb_register:
2084 case ARM::VLD1d32Twb_fixed:
2085 case ARM::VLD1d32Twb_register:
2086 case ARM::VLD1d64Twb_fixed:
2087 case ARM::VLD1d64Twb_register:
2088 case ARM::VLD1d8Qwb_fixed:
2089 case ARM::VLD1d8Qwb_register:
2090 case ARM::VLD1d16Qwb_fixed:
2091 case ARM::VLD1d16Qwb_register:
2092 case ARM::VLD1d32Qwb_fixed:
2093 case ARM::VLD1d32Qwb_register:
2094 case ARM::VLD1d64Qwb_fixed:
2095 case ARM::VLD1d64Qwb_register:
2096 case ARM::VLD2d8wb_fixed:
2097 case ARM::VLD2d16wb_fixed:
2098 case ARM::VLD2d32wb_fixed:
2099 case ARM::VLD2q8wb_fixed:
2100 case ARM::VLD2q16wb_fixed:
2101 case ARM::VLD2q32wb_fixed:
2102 case ARM::VLD2d8wb_register:
2103 case ARM::VLD2d16wb_register:
2104 case ARM::VLD2d32wb_register:
2105 case ARM::VLD2q8wb_register:
2106 case ARM::VLD2q16wb_register:
2107 case ARM::VLD2q32wb_register:
2108 case ARM::VLD2b8wb_fixed:
2109 case ARM::VLD2b16wb_fixed:
2110 case ARM::VLD2b32wb_fixed:
2111 case ARM::VLD2b8wb_register:
2112 case ARM::VLD2b16wb_register:
2113 case ARM::VLD2b32wb_register:
2115 break;
2116 case ARM::VLD3d8_UPD:
2117 case ARM::VLD3d16_UPD:
2118 case ARM::VLD3d32_UPD:
2119 case ARM::VLD3q8_UPD:
2120 case ARM::VLD3q16_UPD:
2121 case ARM::VLD3q32_UPD:
2122 case ARM::VLD4d8_UPD:
2123 case ARM::VLD4d16_UPD:
2124 case ARM::VLD4d32_UPD:
2125 case ARM::VLD4q8_UPD:
2126 case ARM::VLD4q16_UPD:
2127 case ARM::VLD4q32_UPD:
2128 if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder)))
2129 return MCDisassembler::Fail;
2130 break;
2131 default:
2132 break;
2133 }
2134
2135 // AddrMode6 Base (register+alignment)
2136 if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder)))
2137 return MCDisassembler::Fail;
2138
2139 // AddrMode6 Offset (register)
2140 switch (Inst.getOpcode()) {
2141 default:
2142 // The below have been updated to have explicit am6offset split
2143 // between fixed and register offset. For those instructions not
2144 // yet updated, we need to add an additional reg0 operand for the
2145 // fixed variant.
2146 //
2147 // The fixed offset encodes as Rm == 0xd, so we check for that.
2148 if (Rm == 0xd) {
2150 break;
2151 }
2152 // Fall through to handle the register offset variant.
2153 [[fallthrough]];
2154 case ARM::VLD1d8wb_fixed:
2155 case ARM::VLD1d16wb_fixed:
2156 case ARM::VLD1d32wb_fixed:
2157 case ARM::VLD1d64wb_fixed:
2158 case ARM::VLD1d8Twb_fixed:
2159 case ARM::VLD1d16Twb_fixed:
2160 case ARM::VLD1d32Twb_fixed:
2161 case ARM::VLD1d64Twb_fixed:
2162 case ARM::VLD1d8Qwb_fixed:
2163 case ARM::VLD1d16Qwb_fixed:
2164 case ARM::VLD1d32Qwb_fixed:
2165 case ARM::VLD1d64Qwb_fixed:
2166 case ARM::VLD1d8wb_register:
2167 case ARM::VLD1d16wb_register:
2168 case ARM::VLD1d32wb_register:
2169 case ARM::VLD1d64wb_register:
2170 case ARM::VLD1q8wb_fixed:
2171 case ARM::VLD1q16wb_fixed:
2172 case ARM::VLD1q32wb_fixed:
2173 case ARM::VLD1q64wb_fixed:
2174 case ARM::VLD1q8wb_register:
2175 case ARM::VLD1q16wb_register:
2176 case ARM::VLD1q32wb_register:
2177 case ARM::VLD1q64wb_register:
2178 // The fixed offset post-increment encodes Rm == 0xd. The no-writeback
2179 // variant encodes Rm == 0xf. Anything else is a register offset post-
2180 // increment and we need to add the register operand to the instruction.
2181 if (Rm != 0xD && Rm != 0xF &&
2182 !Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2183 return MCDisassembler::Fail;
2184 break;
2185 case ARM::VLD2d8wb_fixed:
2186 case ARM::VLD2d16wb_fixed:
2187 case ARM::VLD2d32wb_fixed:
2188 case ARM::VLD2b8wb_fixed:
2189 case ARM::VLD2b16wb_fixed:
2190 case ARM::VLD2b32wb_fixed:
2191 case ARM::VLD2q8wb_fixed:
2192 case ARM::VLD2q16wb_fixed:
2193 case ARM::VLD2q32wb_fixed:
2194 break;
2195 }
2196
2197 return S;
2198}
2199
2200static DecodeStatus DecodeVSTInstruction(MCInst &Inst, unsigned Insn,
2201 uint64_t Address,
2202 const MCDisassembler *Decoder) {
2204
2205 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
2206 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
2207 unsigned wb = fieldFromInstruction(Insn, 16, 4);
2208 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
2209 Rn |= fieldFromInstruction(Insn, 4, 2) << 4;
2210 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
2211
2212 // Writeback Operand
2213 switch (Inst.getOpcode()) {
2214 case ARM::VST1d8wb_fixed:
2215 case ARM::VST1d16wb_fixed:
2216 case ARM::VST1d32wb_fixed:
2217 case ARM::VST1d64wb_fixed:
2218 case ARM::VST1d8wb_register:
2219 case ARM::VST1d16wb_register:
2220 case ARM::VST1d32wb_register:
2221 case ARM::VST1d64wb_register:
2222 case ARM::VST1q8wb_fixed:
2223 case ARM::VST1q16wb_fixed:
2224 case ARM::VST1q32wb_fixed:
2225 case ARM::VST1q64wb_fixed:
2226 case ARM::VST1q8wb_register:
2227 case ARM::VST1q16wb_register:
2228 case ARM::VST1q32wb_register:
2229 case ARM::VST1q64wb_register:
2230 case ARM::VST1d8Twb_fixed:
2231 case ARM::VST1d16Twb_fixed:
2232 case ARM::VST1d32Twb_fixed:
2233 case ARM::VST1d64Twb_fixed:
2234 case ARM::VST1d8Twb_register:
2235 case ARM::VST1d16Twb_register:
2236 case ARM::VST1d32Twb_register:
2237 case ARM::VST1d64Twb_register:
2238 case ARM::VST1d8Qwb_fixed:
2239 case ARM::VST1d16Qwb_fixed:
2240 case ARM::VST1d32Qwb_fixed:
2241 case ARM::VST1d64Qwb_fixed:
2242 case ARM::VST1d8Qwb_register:
2243 case ARM::VST1d16Qwb_register:
2244 case ARM::VST1d32Qwb_register:
2245 case ARM::VST1d64Qwb_register:
2246 case ARM::VST2d8wb_fixed:
2247 case ARM::VST2d16wb_fixed:
2248 case ARM::VST2d32wb_fixed:
2249 case ARM::VST2d8wb_register:
2250 case ARM::VST2d16wb_register:
2251 case ARM::VST2d32wb_register:
2252 case ARM::VST2q8wb_fixed:
2253 case ARM::VST2q16wb_fixed:
2254 case ARM::VST2q32wb_fixed:
2255 case ARM::VST2q8wb_register:
2256 case ARM::VST2q16wb_register:
2257 case ARM::VST2q32wb_register:
2258 case ARM::VST2b8wb_fixed:
2259 case ARM::VST2b16wb_fixed:
2260 case ARM::VST2b32wb_fixed:
2261 case ARM::VST2b8wb_register:
2262 case ARM::VST2b16wb_register:
2263 case ARM::VST2b32wb_register:
2264 if (Rm == 0xF)
2265 return MCDisassembler::Fail;
2267 break;
2268 case ARM::VST3d8_UPD:
2269 case ARM::VST3d16_UPD:
2270 case ARM::VST3d32_UPD:
2271 case ARM::VST3q8_UPD:
2272 case ARM::VST3q16_UPD:
2273 case ARM::VST3q32_UPD:
2274 case ARM::VST4d8_UPD:
2275 case ARM::VST4d16_UPD:
2276 case ARM::VST4d32_UPD:
2277 case ARM::VST4q8_UPD:
2278 case ARM::VST4q16_UPD:
2279 case ARM::VST4q32_UPD:
2280 if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder)))
2281 return MCDisassembler::Fail;
2282 break;
2283 default:
2284 break;
2285 }
2286
2287 // AddrMode6 Base (register+alignment)
2288 if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder)))
2289 return MCDisassembler::Fail;
2290
2291 // AddrMode6 Offset (register)
2292 switch (Inst.getOpcode()) {
2293 default:
2294 if (Rm == 0xD)
2296 else if (Rm != 0xF) {
2297 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2298 return MCDisassembler::Fail;
2299 }
2300 break;
2301 case ARM::VST1d8wb_fixed:
2302 case ARM::VST1d16wb_fixed:
2303 case ARM::VST1d32wb_fixed:
2304 case ARM::VST1d64wb_fixed:
2305 case ARM::VST1q8wb_fixed:
2306 case ARM::VST1q16wb_fixed:
2307 case ARM::VST1q32wb_fixed:
2308 case ARM::VST1q64wb_fixed:
2309 case ARM::VST1d8Twb_fixed:
2310 case ARM::VST1d16Twb_fixed:
2311 case ARM::VST1d32Twb_fixed:
2312 case ARM::VST1d64Twb_fixed:
2313 case ARM::VST1d8Qwb_fixed:
2314 case ARM::VST1d16Qwb_fixed:
2315 case ARM::VST1d32Qwb_fixed:
2316 case ARM::VST1d64Qwb_fixed:
2317 case ARM::VST2d8wb_fixed:
2318 case ARM::VST2d16wb_fixed:
2319 case ARM::VST2d32wb_fixed:
2320 case ARM::VST2q8wb_fixed:
2321 case ARM::VST2q16wb_fixed:
2322 case ARM::VST2q32wb_fixed:
2323 case ARM::VST2b8wb_fixed:
2324 case ARM::VST2b16wb_fixed:
2325 case ARM::VST2b32wb_fixed:
2326 break;
2327 }
2328
2329 // First input register
2330 switch (Inst.getOpcode()) {
2331 case ARM::VST1q16:
2332 case ARM::VST1q32:
2333 case ARM::VST1q64:
2334 case ARM::VST1q8:
2335 case ARM::VST1q16wb_fixed:
2336 case ARM::VST1q16wb_register:
2337 case ARM::VST1q32wb_fixed:
2338 case ARM::VST1q32wb_register:
2339 case ARM::VST1q64wb_fixed:
2340 case ARM::VST1q64wb_register:
2341 case ARM::VST1q8wb_fixed:
2342 case ARM::VST1q8wb_register:
2343 case ARM::VST2d16:
2344 case ARM::VST2d32:
2345 case ARM::VST2d8:
2346 case ARM::VST2d16wb_fixed:
2347 case ARM::VST2d16wb_register:
2348 case ARM::VST2d32wb_fixed:
2349 case ARM::VST2d32wb_register:
2350 case ARM::VST2d8wb_fixed:
2351 case ARM::VST2d8wb_register:
2352 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder)))
2353 return MCDisassembler::Fail;
2354 break;
2355 case ARM::VST2b16:
2356 case ARM::VST2b32:
2357 case ARM::VST2b8:
2358 case ARM::VST2b16wb_fixed:
2359 case ARM::VST2b16wb_register:
2360 case ARM::VST2b32wb_fixed:
2361 case ARM::VST2b32wb_register:
2362 case ARM::VST2b8wb_fixed:
2363 case ARM::VST2b8wb_register:
2364 if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder)))
2365 return MCDisassembler::Fail;
2366 break;
2367 default:
2368 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2369 return MCDisassembler::Fail;
2370 }
2371
2372 // Second input register
2373 switch (Inst.getOpcode()) {
2374 case ARM::VST3d8:
2375 case ARM::VST3d16:
2376 case ARM::VST3d32:
2377 case ARM::VST3d8_UPD:
2378 case ARM::VST3d16_UPD:
2379 case ARM::VST3d32_UPD:
2380 case ARM::VST4d8:
2381 case ARM::VST4d16:
2382 case ARM::VST4d32:
2383 case ARM::VST4d8_UPD:
2384 case ARM::VST4d16_UPD:
2385 case ARM::VST4d32_UPD:
2386 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder)))
2387 return MCDisassembler::Fail;
2388 break;
2389 case ARM::VST3q8:
2390 case ARM::VST3q16:
2391 case ARM::VST3q32:
2392 case ARM::VST3q8_UPD:
2393 case ARM::VST3q16_UPD:
2394 case ARM::VST3q32_UPD:
2395 case ARM::VST4q8:
2396 case ARM::VST4q16:
2397 case ARM::VST4q32:
2398 case ARM::VST4q8_UPD:
2399 case ARM::VST4q16_UPD:
2400 case ARM::VST4q32_UPD:
2401 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
2402 return MCDisassembler::Fail;
2403 break;
2404 default:
2405 break;
2406 }
2407
2408 // Third input register
2409 switch (Inst.getOpcode()) {
2410 case ARM::VST3d8:
2411 case ARM::VST3d16:
2412 case ARM::VST3d32:
2413 case ARM::VST3d8_UPD:
2414 case ARM::VST3d16_UPD:
2415 case ARM::VST3d32_UPD:
2416 case ARM::VST4d8:
2417 case ARM::VST4d16:
2418 case ARM::VST4d32:
2419 case ARM::VST4d8_UPD:
2420 case ARM::VST4d16_UPD:
2421 case ARM::VST4d32_UPD:
2422 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
2423 return MCDisassembler::Fail;
2424 break;
2425 case ARM::VST3q8:
2426 case ARM::VST3q16:
2427 case ARM::VST3q32:
2428 case ARM::VST3q8_UPD:
2429 case ARM::VST3q16_UPD:
2430 case ARM::VST3q32_UPD:
2431 case ARM::VST4q8:
2432 case ARM::VST4q16:
2433 case ARM::VST4q32:
2434 case ARM::VST4q8_UPD:
2435 case ARM::VST4q16_UPD:
2436 case ARM::VST4q32_UPD:
2437 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder)))
2438 return MCDisassembler::Fail;
2439 break;
2440 default:
2441 break;
2442 }
2443
2444 // Fourth input register
2445 switch (Inst.getOpcode()) {
2446 case ARM::VST4d8:
2447 case ARM::VST4d16:
2448 case ARM::VST4d32:
2449 case ARM::VST4d8_UPD:
2450 case ARM::VST4d16_UPD:
2451 case ARM::VST4d32_UPD:
2452 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder)))
2453 return MCDisassembler::Fail;
2454 break;
2455 case ARM::VST4q8:
2456 case ARM::VST4q16:
2457 case ARM::VST4q32:
2458 case ARM::VST4q8_UPD:
2459 case ARM::VST4q16_UPD:
2460 case ARM::VST4q32_UPD:
2461 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder)))
2462 return MCDisassembler::Fail;
2463 break;
2464 default:
2465 break;
2466 }
2467
2468 return S;
2469}
2470
2471static DecodeStatus DecodeVLDST1Instruction(MCInst &Inst, unsigned Insn,
2472 uint64_t Address,
2473 const MCDisassembler *Decoder) {
2474 unsigned type = fieldFromInstruction(Insn, 8, 4);
2475 unsigned align = fieldFromInstruction(Insn, 4, 2);
2476 if (type == 6 && (align & 2)) return MCDisassembler::Fail;
2477 if (type == 7 && (align & 2)) return MCDisassembler::Fail;
2478 if (type == 10 && align == 3) return MCDisassembler::Fail;
2479
2480 unsigned load = fieldFromInstruction(Insn, 21, 1);
2481 return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder)
2482 : DecodeVSTInstruction(Inst, Insn, Address, Decoder);
2483}
2484
2485static DecodeStatus DecodeVLDST2Instruction(MCInst &Inst, unsigned Insn,
2486 uint64_t Address,
2487 const MCDisassembler *Decoder) {
2488 unsigned size = fieldFromInstruction(Insn, 6, 2);
2489 if (size == 3) return MCDisassembler::Fail;
2490
2491 unsigned type = fieldFromInstruction(Insn, 8, 4);
2492 unsigned align = fieldFromInstruction(Insn, 4, 2);
2493 if (type == 8 && align == 3) return MCDisassembler::Fail;
2494 if (type == 9 && align == 3) return MCDisassembler::Fail;
2495
2496 unsigned load = fieldFromInstruction(Insn, 21, 1);
2497 return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder)
2498 : DecodeVSTInstruction(Inst, Insn, Address, Decoder);
2499}
2500
2501static DecodeStatus DecodeVLDST3Instruction(MCInst &Inst, unsigned Insn,
2502 uint64_t Address,
2503 const MCDisassembler *Decoder) {
2504 unsigned size = fieldFromInstruction(Insn, 6, 2);
2505 if (size == 3) return MCDisassembler::Fail;
2506
2507 unsigned align = fieldFromInstruction(Insn, 4, 2);
2508 if (align & 2) return MCDisassembler::Fail;
2509
2510 unsigned load = fieldFromInstruction(Insn, 21, 1);
2511 return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder)
2512 : DecodeVSTInstruction(Inst, Insn, Address, Decoder);
2513}
2514
2515static DecodeStatus DecodeVLDST4Instruction(MCInst &Inst, unsigned Insn,
2516 uint64_t Address,
2517 const MCDisassembler *Decoder) {
2518 unsigned size = fieldFromInstruction(Insn, 6, 2);
2519 if (size == 3) return MCDisassembler::Fail;
2520
2521 unsigned load = fieldFromInstruction(Insn, 21, 1);
2522 return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder)
2523 : DecodeVSTInstruction(Inst, Insn, Address, Decoder);
2524}
2525
2527 uint64_t Address,
2528 const MCDisassembler *Decoder) {
2530
2531 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
2532 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
2533 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
2534 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
2535 unsigned align = fieldFromInstruction(Insn, 4, 1);
2536 unsigned size = fieldFromInstruction(Insn, 6, 2);
2537
2538 if (size == 0 && align == 1)
2539 return MCDisassembler::Fail;
2540 align *= (1 << size);
2541
2542 switch (Inst.getOpcode()) {
2543 case ARM::VLD1DUPq16: case ARM::VLD1DUPq32: case ARM::VLD1DUPq8:
2544 case ARM::VLD1DUPq16wb_fixed: case ARM::VLD1DUPq16wb_register:
2545 case ARM::VLD1DUPq32wb_fixed: case ARM::VLD1DUPq32wb_register:
2546 case ARM::VLD1DUPq8wb_fixed: case ARM::VLD1DUPq8wb_register:
2547 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder)))
2548 return MCDisassembler::Fail;
2549 break;
2550 default:
2551 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2552 return MCDisassembler::Fail;
2553 break;
2554 }
2555 if (Rm != 0xF) {
2556 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2557 return MCDisassembler::Fail;
2558 }
2559
2560 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2561 return MCDisassembler::Fail;
2562 Inst.addOperand(MCOperand::createImm(align));
2563
2564 // The fixed offset post-increment encodes Rm == 0xd. The no-writeback
2565 // variant encodes Rm == 0xf. Anything else is a register offset post-
2566 // increment and we need to add the register operand to the instruction.
2567 if (Rm != 0xD && Rm != 0xF &&
2568 !Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2569 return MCDisassembler::Fail;
2570
2571 return S;
2572}
2573
2575 uint64_t Address,
2576 const MCDisassembler *Decoder) {
2578
2579 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
2580 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
2581 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
2582 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
2583 unsigned align = fieldFromInstruction(Insn, 4, 1);
2584 unsigned size = 1 << fieldFromInstruction(Insn, 6, 2);
2585 align *= 2*size;
2586
2587 switch (Inst.getOpcode()) {
2588 case ARM::VLD2DUPd16: case ARM::VLD2DUPd32: case ARM::VLD2DUPd8:
2589 case ARM::VLD2DUPd16wb_fixed: case ARM::VLD2DUPd16wb_register:
2590 case ARM::VLD2DUPd32wb_fixed: case ARM::VLD2DUPd32wb_register:
2591 case ARM::VLD2DUPd8wb_fixed: case ARM::VLD2DUPd8wb_register:
2592 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder)))
2593 return MCDisassembler::Fail;
2594 break;
2595 case ARM::VLD2DUPd16x2: case ARM::VLD2DUPd32x2: case ARM::VLD2DUPd8x2:
2596 case ARM::VLD2DUPd16x2wb_fixed: case ARM::VLD2DUPd16x2wb_register:
2597 case ARM::VLD2DUPd32x2wb_fixed: case ARM::VLD2DUPd32x2wb_register:
2598 case ARM::VLD2DUPd8x2wb_fixed: case ARM::VLD2DUPd8x2wb_register:
2599 if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder)))
2600 return MCDisassembler::Fail;
2601 break;
2602 default:
2603 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2604 return MCDisassembler::Fail;
2605 break;
2606 }
2607
2608 if (Rm != 0xF)
2610
2611 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2612 return MCDisassembler::Fail;
2613 Inst.addOperand(MCOperand::createImm(align));
2614
2615 if (Rm != 0xD && Rm != 0xF) {
2616 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2617 return MCDisassembler::Fail;
2618 }
2619
2620 return S;
2621}
2622
2624 uint64_t Address,
2625 const MCDisassembler *Decoder) {
2627
2628 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
2629 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
2630 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
2631 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
2632 unsigned inc = fieldFromInstruction(Insn, 5, 1) + 1;
2633
2634 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2635 return MCDisassembler::Fail;
2636 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder)))
2637 return MCDisassembler::Fail;
2638 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder)))
2639 return MCDisassembler::Fail;
2640 if (Rm != 0xF) {
2641 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2642 return MCDisassembler::Fail;
2643 }
2644
2645 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2646 return MCDisassembler::Fail;
2648
2649 if (Rm == 0xD)
2651 else if (Rm != 0xF) {
2652 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2653 return MCDisassembler::Fail;
2654 }
2655
2656 return S;
2657}
2658
2660 uint64_t Address,
2661 const MCDisassembler *Decoder) {
2663
2664 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
2665 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
2666 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
2667 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
2668 unsigned size = fieldFromInstruction(Insn, 6, 2);
2669 unsigned inc = fieldFromInstruction(Insn, 5, 1) + 1;
2670 unsigned align = fieldFromInstruction(Insn, 4, 1);
2671
2672 if (size == 0x3) {
2673 if (align == 0)
2674 return MCDisassembler::Fail;
2675 align = 16;
2676 } else {
2677 if (size == 2) {
2678 align *= 8;
2679 } else {
2680 size = 1 << size;
2681 align *= 4*size;
2682 }
2683 }
2684
2685 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2686 return MCDisassembler::Fail;
2687 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder)))
2688 return MCDisassembler::Fail;
2689 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder)))
2690 return MCDisassembler::Fail;
2691 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3*inc)%32, Address, Decoder)))
2692 return MCDisassembler::Fail;
2693 if (Rm != 0xF) {
2694 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2695 return MCDisassembler::Fail;
2696 }
2697
2698 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2699 return MCDisassembler::Fail;
2700 Inst.addOperand(MCOperand::createImm(align));
2701
2702 if (Rm == 0xD)
2704 else if (Rm != 0xF) {
2705 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2706 return MCDisassembler::Fail;
2707 }
2708
2709 return S;
2710}
2711
2713 uint64_t Address,
2714 const MCDisassembler *Decoder) {
2716
2717 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
2718 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
2719 unsigned imm = fieldFromInstruction(Insn, 0, 4);
2720 imm |= fieldFromInstruction(Insn, 16, 3) << 4;
2721 imm |= fieldFromInstruction(Insn, 24, 1) << 7;
2722 imm |= fieldFromInstruction(Insn, 8, 4) << 8;
2723 imm |= fieldFromInstruction(Insn, 5, 1) << 12;
2724 unsigned Q = fieldFromInstruction(Insn, 6, 1);
2725
2726 if (Q) {
2727 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)))
2728 return MCDisassembler::Fail;
2729 } else {
2730 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2731 return MCDisassembler::Fail;
2732 }
2733
2735
2736 switch (Inst.getOpcode()) {
2737 case ARM::VORRiv4i16:
2738 case ARM::VORRiv2i32:
2739 case ARM::VBICiv4i16:
2740 case ARM::VBICiv2i32:
2741 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2742 return MCDisassembler::Fail;
2743 break;
2744 case ARM::VORRiv8i16:
2745 case ARM::VORRiv4i32:
2746 case ARM::VBICiv8i16:
2747 case ARM::VBICiv4i32:
2748 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)))
2749 return MCDisassembler::Fail;
2750 break;
2751 default:
2752 break;
2753 }
2754
2755 return S;
2756}
2757
2759 uint64_t Address,
2760 const MCDisassembler *Decoder) {
2762
2763 unsigned Qd = ((fieldFromInstruction(Insn, 22, 1) << 3) |
2764 fieldFromInstruction(Insn, 13, 3));
2765 unsigned cmode = fieldFromInstruction(Insn, 8, 4);
2766 unsigned imm = fieldFromInstruction(Insn, 0, 4);
2767 imm |= fieldFromInstruction(Insn, 16, 3) << 4;
2768 imm |= fieldFromInstruction(Insn, 28, 1) << 7;
2769 imm |= cmode << 8;
2770 imm |= fieldFromInstruction(Insn, 5, 1) << 12;
2771
2772 if (cmode == 0xF && Inst.getOpcode() == ARM::MVE_VMVNimmi32)
2773 return MCDisassembler::Fail;
2774
2775 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qd, Address, Decoder)))
2776 return MCDisassembler::Fail;
2777
2779
2780 return S;
2781}
2782
2784 uint64_t Address,
2785 const MCDisassembler *Decoder) {
2787
2788 unsigned Qd = fieldFromInstruction(Insn, 13, 3);
2789 Qd |= fieldFromInstruction(Insn, 22, 1) << 3;
2790 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qd, Address, Decoder)))
2791 return MCDisassembler::Fail;
2792 Inst.addOperand(MCOperand::createReg(ARM::FPSCR_NZCV));
2793
2794 unsigned Qn = fieldFromInstruction(Insn, 17, 3);
2795 Qn |= fieldFromInstruction(Insn, 7, 1) << 3;
2796 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qn, Address, Decoder)))
2797 return MCDisassembler::Fail;
2798 unsigned Qm = fieldFromInstruction(Insn, 1, 3);
2799 Qm |= fieldFromInstruction(Insn, 5, 1) << 3;
2800 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qm, Address, Decoder)))
2801 return MCDisassembler::Fail;
2802 if (!fieldFromInstruction(Insn, 12, 1)) // I bit clear => need input FPSCR
2803 Inst.addOperand(MCOperand::createReg(ARM::FPSCR_NZCV));
2804
2805 return S;
2806}
2807
2809 uint64_t Address,
2810 const MCDisassembler *Decoder) {
2812
2813 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
2814 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
2815 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
2816 Rm |= fieldFromInstruction(Insn, 5, 1) << 4;
2817 unsigned size = fieldFromInstruction(Insn, 18, 2);
2818
2819 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)))
2820 return MCDisassembler::Fail;
2821 if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder)))
2822 return MCDisassembler::Fail;
2824
2825 return S;
2826}
2827
2828static DecodeStatus DecodeShiftRight8Imm(MCInst &Inst, unsigned Val,
2829 uint64_t Address,
2830 const MCDisassembler *Decoder) {
2831 Inst.addOperand(MCOperand::createImm(8 - Val));
2833}
2834
2835static DecodeStatus DecodeShiftRight16Imm(MCInst &Inst, unsigned Val,
2836 uint64_t Address,
2837 const MCDisassembler *Decoder) {
2838 Inst.addOperand(MCOperand::createImm(16 - Val));
2840}
2841
2842static DecodeStatus DecodeShiftRight32Imm(MCInst &Inst, unsigned Val,
2843 uint64_t Address,
2844 const MCDisassembler *Decoder) {
2845 Inst.addOperand(MCOperand::createImm(32 - Val));
2847}
2848
2849static DecodeStatus DecodeShiftRight64Imm(MCInst &Inst, unsigned Val,
2850 uint64_t Address,
2851 const MCDisassembler *Decoder) {
2852 Inst.addOperand(MCOperand::createImm(64 - Val));
2854}
2855
2856static DecodeStatus DecodeTBLInstruction(MCInst &Inst, unsigned Insn,
2857 uint64_t Address,
2858 const MCDisassembler *Decoder) {
2860
2861 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
2862 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
2863 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
2864 Rn |= fieldFromInstruction(Insn, 7, 1) << 4;
2865 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
2866 Rm |= fieldFromInstruction(Insn, 5, 1) << 4;
2867 unsigned op = fieldFromInstruction(Insn, 6, 1);
2868
2869 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2870 return MCDisassembler::Fail;
2871 if (op) {
2872 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2873 return MCDisassembler::Fail; // Writeback
2874 }
2875
2876 switch (Inst.getOpcode()) {
2877 case ARM::VTBL2:
2878 case ARM::VTBX2:
2879 if (!Check(S, DecodeDPairRegisterClass(Inst, Rn, Address, Decoder)))
2880 return MCDisassembler::Fail;
2881 break;
2882 default:
2883 if (!Check(S, DecodeDPRRegisterClass(Inst, Rn, Address, Decoder)))
2884 return MCDisassembler::Fail;
2885 }
2886
2887 if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder)))
2888 return MCDisassembler::Fail;
2889
2890 return S;
2891}
2892
2894 uint64_t Address,
2895 const MCDisassembler *Decoder) {
2897
2898 unsigned dst = fieldFromInstruction(Insn, 8, 3);
2899 unsigned imm = fieldFromInstruction(Insn, 0, 8);
2900
2901 if (!Check(S, DecodetGPRRegisterClass(Inst, dst, Address, Decoder)))
2902 return MCDisassembler::Fail;
2903
2904 switch(Inst.getOpcode()) {
2905 default:
2906 return MCDisassembler::Fail;
2907 case ARM::tADR:
2908 break; // tADR does not explicitly represent the PC as an operand.
2909 case ARM::tADDrSPi:
2910 Inst.addOperand(MCOperand::createReg(ARM::SP));
2911 break;
2912 }
2913
2915 return S;
2916}
2917
2918static DecodeStatus DecodeThumbBROperand(MCInst &Inst, unsigned Val,
2919 uint64_t Address,
2920 const MCDisassembler *Decoder) {
2921 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<12>(Val<<1) + 4,
2922 true, 2, Inst, Decoder))
2925}
2926
2927static DecodeStatus DecodeT2BROperand(MCInst &Inst, unsigned Val,
2928 uint64_t Address,
2929 const MCDisassembler *Decoder) {
2930 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<21>(Val) + 4,
2931 true, 4, Inst, Decoder))
2934}
2935
2937 uint64_t Address,
2938 const MCDisassembler *Decoder) {
2939 if (!tryAddingSymbolicOperand(Address, Address + (Val<<1) + 4,
2940 true, 2, Inst, Decoder))
2941 Inst.addOperand(MCOperand::createImm(Val << 1));
2943}
2944
2945static DecodeStatus DecodeThumbAddrModeRR(MCInst &Inst, unsigned Val,
2946 uint64_t Address,
2947 const MCDisassembler *Decoder) {
2949
2950 unsigned Rn = fieldFromInstruction(Val, 0, 3);
2951 unsigned Rm = fieldFromInstruction(Val, 3, 3);
2952
2953 if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder)))
2954 return MCDisassembler::Fail;
2955 if (!Check(S, DecodetGPRRegisterClass(Inst, Rm, Address, Decoder)))
2956 return MCDisassembler::Fail;
2957
2958 return S;
2959}
2960
2961static DecodeStatus DecodeThumbAddrModeIS(MCInst &Inst, unsigned Val,
2962 uint64_t Address,
2963 const MCDisassembler *Decoder) {
2965
2966 unsigned Rn = fieldFromInstruction(Val, 0, 3);
2967 unsigned imm = fieldFromInstruction(Val, 3, 5);
2968
2969 if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder)))
2970 return MCDisassembler::Fail;
2972
2973 return S;
2974}
2975
2976static DecodeStatus DecodeThumbAddrModePC(MCInst &Inst, unsigned Val,
2977 uint64_t Address,
2978 const MCDisassembler *Decoder) {
2979 unsigned imm = Val << 2;
2980
2982 tryAddingPcLoadReferenceComment(Address, (Address & ~2u) + imm + 4, Decoder);
2983
2985}
2986
2987static DecodeStatus DecodeThumbAddrModeSP(MCInst &Inst, unsigned Val,
2988 uint64_t Address,
2989 const MCDisassembler *Decoder) {
2990 Inst.addOperand(MCOperand::createReg(ARM::SP));
2992
2994}
2995
2996static DecodeStatus DecodeT2AddrModeSOReg(MCInst &Inst, unsigned Val,
2997 uint64_t Address,
2998 const MCDisassembler *Decoder) {
3000
3001 unsigned Rn = fieldFromInstruction(Val, 6, 4);
3002 unsigned Rm = fieldFromInstruction(Val, 2, 4);
3003 unsigned imm = fieldFromInstruction(Val, 0, 2);
3004
3005 // Thumb stores cannot use PC as dest register.
3006 switch (Inst.getOpcode()) {
3007 case ARM::t2STRHs:
3008 case ARM::t2STRBs:
3009 case ARM::t2STRs:
3010 if (Rn == 15)
3011 return MCDisassembler::Fail;
3012 break;
3013 default:
3014 break;
3015 }
3016
3017 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3018 return MCDisassembler::Fail;
3019 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder)))
3020 return MCDisassembler::Fail;
3022
3023 return S;
3024}
3025
3026static DecodeStatus DecodeT2LoadLabel(MCInst &Inst, unsigned Insn,
3027 uint64_t Address,
3028 const MCDisassembler *Decoder) {
3030
3031 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
3032 unsigned U = fieldFromInstruction(Insn, 23, 1);
3033 int imm = fieldFromInstruction(Insn, 0, 12);
3034
3035 const FeatureBitset &featureBits =
3036 Decoder->getSubtargetInfo().getFeatureBits();
3037
3038 bool hasV7Ops = featureBits[ARM::HasV7Ops];
3039
3040 if (Rt == 15) {
3041 switch (Inst.getOpcode()) {
3042 case ARM::t2LDRBpci:
3043 case ARM::t2LDRHpci:
3044 Inst.setOpcode(ARM::t2PLDpci);
3045 break;
3046 case ARM::t2LDRSBpci:
3047 Inst.setOpcode(ARM::t2PLIpci);
3048 break;
3049 case ARM::t2LDRSHpci:
3050 return MCDisassembler::Fail;
3051 default:
3052 break;
3053 }
3054 }
3055
3056 switch(Inst.getOpcode()) {
3057 case ARM::t2PLDpci:
3058 break;
3059 case ARM::t2PLIpci:
3060 if (!hasV7Ops)
3061 return MCDisassembler::Fail;
3062 break;
3063 default:
3064 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3065 return MCDisassembler::Fail;
3066 }
3067
3068 if (!U) {
3069 // Special case for #-0.
3070 if (imm == 0)
3071 imm = INT32_MIN;
3072 else
3073 imm = -imm;
3074 }
3076
3077 return S;
3078}
3079
3080static DecodeStatus DecodeT2LoadShift(MCInst &Inst, unsigned Insn,
3081 uint64_t Address,
3082 const MCDisassembler *Decoder) {
3084
3085 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
3086 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3087
3088 const FeatureBitset &featureBits =
3089 Decoder->getSubtargetInfo().getFeatureBits();
3090
3091 bool hasMP = featureBits[ARM::FeatureMP];
3092 bool hasV7Ops = featureBits[ARM::HasV7Ops];
3093
3094 if (Rn == 15) {
3095 switch (Inst.getOpcode()) {
3096 case ARM::t2LDRBs:
3097 Inst.setOpcode(ARM::t2LDRBpci);
3098 break;
3099 case ARM::t2LDRHs:
3100 Inst.setOpcode(ARM::t2LDRHpci);
3101 break;
3102 case ARM::t2LDRSHs:
3103 Inst.setOpcode(ARM::t2LDRSHpci);
3104 break;
3105 case ARM::t2LDRSBs:
3106 Inst.setOpcode(ARM::t2LDRSBpci);
3107 break;
3108 case ARM::t2LDRs:
3109 Inst.setOpcode(ARM::t2LDRpci);
3110 break;
3111 case ARM::t2PLDs:
3112 Inst.setOpcode(ARM::t2PLDpci);
3113 break;
3114 case ARM::t2PLIs:
3115 Inst.setOpcode(ARM::t2PLIpci);
3116 break;
3117 default:
3118 return MCDisassembler::Fail;
3119 }
3120
3121 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder);
3122 }
3123
3124 if (Rt == 15) {
3125 switch (Inst.getOpcode()) {
3126 case ARM::t2LDRSHs:
3127 return MCDisassembler::Fail;
3128 case ARM::t2LDRHs:
3129 Inst.setOpcode(ARM::t2PLDWs);
3130 break;
3131 case ARM::t2LDRSBs:
3132 Inst.setOpcode(ARM::t2PLIs);
3133 break;
3134 default:
3135 break;
3136 }
3137 }
3138
3139 switch (Inst.getOpcode()) {
3140 case ARM::t2PLDs:
3141 break;
3142 case ARM::t2PLIs:
3143 if (!hasV7Ops)
3144 return MCDisassembler::Fail;
3145 break;
3146 case ARM::t2PLDWs:
3147 if (!hasV7Ops || !hasMP)
3148 return MCDisassembler::Fail;
3149 break;
3150 default:
3151 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3152 return MCDisassembler::Fail;
3153 }
3154
3155 unsigned addrmode = fieldFromInstruction(Insn, 4, 2);
3156 addrmode |= fieldFromInstruction(Insn, 0, 4) << 2;
3157 addrmode |= fieldFromInstruction(Insn, 16, 4) << 6;
3158 if (!Check(S, DecodeT2AddrModeSOReg(Inst, addrmode, Address, Decoder)))
3159 return MCDisassembler::Fail;
3160
3161 return S;
3162}
3163
3164static DecodeStatus DecodeT2Imm8(MCInst &Inst, unsigned Val, uint64_t Address,
3165 const MCDisassembler *Decoder) {
3166 int imm = Val & 0xFF;
3167 if (Val == 0)
3168 imm = INT32_MIN;
3169 else if (!(Val & 0x100))
3170 imm *= -1;
3172
3174}
3175
3176static DecodeStatus DecodeT2AddrModeImm8(MCInst &Inst, unsigned Val,
3177 uint64_t Address,
3178 const MCDisassembler *Decoder) {
3180
3181 unsigned Rn = fieldFromInstruction(Val, 9, 4);
3182 unsigned imm = fieldFromInstruction(Val, 0, 9);
3183
3184 // Thumb stores cannot use PC as dest register.
3185 switch (Inst.getOpcode()) {
3186 case ARM::t2STRT:
3187 case ARM::t2STRBT:
3188 case ARM::t2STRHT:
3189 case ARM::t2STRi8:
3190 case ARM::t2STRHi8:
3191 case ARM::t2STRBi8:
3192 if (Rn == 15)
3193 return MCDisassembler::Fail;
3194 break;
3195 default:
3196 break;
3197 }
3198
3199 // Some instructions always use an additive offset.
3200 switch (Inst.getOpcode()) {
3201 case ARM::t2LDRT:
3202 case ARM::t2LDRBT:
3203 case ARM::t2LDRHT:
3204 case ARM::t2LDRSBT:
3205 case ARM::t2LDRSHT:
3206 case ARM::t2STRT:
3207 case ARM::t2STRBT:
3208 case ARM::t2STRHT:
3209 imm |= 0x100;
3210 break;
3211 default:
3212 break;
3213 }
3214
3215 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3216 return MCDisassembler::Fail;
3217 if (!Check(S, DecodeT2Imm8(Inst, imm, Address, Decoder)))
3218 return MCDisassembler::Fail;
3219
3220 return S;
3221}
3222
3223static DecodeStatus DecodeT2LoadImm8(MCInst &Inst, unsigned Insn,
3224 uint64_t Address,
3225 const MCDisassembler *Decoder) {
3227
3228 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3229 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
3230 unsigned U = fieldFromInstruction(Insn, 9, 1);
3231 unsigned imm = fieldFromInstruction(Insn, 0, 8);
3232 imm |= (U << 8);
3233 imm |= (Rn << 9);
3234 unsigned add = fieldFromInstruction(Insn, 9, 1);
3235
3236 const FeatureBitset &featureBits =
3237 Decoder->getSubtargetInfo().getFeatureBits();
3238
3239 bool hasMP = featureBits[ARM::FeatureMP];
3240 bool hasV7Ops = featureBits[ARM::HasV7Ops];
3241
3242 if (Rn == 15) {
3243 switch (Inst.getOpcode()) {
3244 case ARM::t2LDRi8:
3245 Inst.setOpcode(ARM::t2LDRpci);
3246 break;
3247 case ARM::t2LDRBi8:
3248 Inst.setOpcode(ARM::t2LDRBpci);
3249 break;
3250 case ARM::t2LDRSBi8:
3251 Inst.setOpcode(ARM::t2LDRSBpci);
3252 break;
3253 case ARM::t2LDRHi8:
3254 Inst.setOpcode(ARM::t2LDRHpci);
3255 break;
3256 case ARM::t2LDRSHi8:
3257 Inst.setOpcode(ARM::t2LDRSHpci);
3258 break;
3259 case ARM::t2PLDi8:
3260 Inst.setOpcode(ARM::t2PLDpci);
3261 break;
3262 case ARM::t2PLIi8:
3263 Inst.setOpcode(ARM::t2PLIpci);
3264 break;
3265 default:
3266 return MCDisassembler::Fail;
3267 }
3268 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder);
3269 }
3270
3271 if (Rt == 15) {
3272 switch (Inst.getOpcode()) {
3273 case ARM::t2LDRSHi8:
3274 return MCDisassembler::Fail;
3275 case ARM::t2LDRHi8:
3276 if (!add)
3277 Inst.setOpcode(ARM::t2PLDWi8);
3278 break;
3279 case ARM::t2LDRSBi8:
3280 Inst.setOpcode(ARM::t2PLIi8);
3281 break;
3282 default:
3283 break;
3284 }
3285 }
3286
3287 switch (Inst.getOpcode()) {
3288 case ARM::t2PLDi8:
3289 break;
3290 case ARM::t2PLIi8:
3291 if (!hasV7Ops)
3292 return MCDisassembler::Fail;
3293 break;
3294 case ARM::t2PLDWi8:
3295 if (!hasV7Ops || !hasMP)
3296 return MCDisassembler::Fail;
3297 break;
3298 default:
3299 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3300 return MCDisassembler::Fail;
3301 }
3302
3303 if (!Check(S, DecodeT2AddrModeImm8(Inst, imm, Address, Decoder)))
3304 return MCDisassembler::Fail;
3305 return S;
3306}
3307
3308static DecodeStatus DecodeT2AddrModeImm12(MCInst &Inst, unsigned Val,
3309 uint64_t Address,
3310 const MCDisassembler *Decoder) {
3312
3313 unsigned Rn = fieldFromInstruction(Val, 13, 4);
3314 unsigned imm = fieldFromInstruction(Val, 0, 12);
3315
3316 // Thumb stores cannot use PC as dest register.
3317 switch (Inst.getOpcode()) {
3318 case ARM::t2STRi12:
3319 case ARM::t2STRBi12:
3320 case ARM::t2STRHi12:
3321 if (Rn == 15)
3322 return MCDisassembler::Fail;
3323 break;
3324 default:
3325 break;
3326 }
3327
3328 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3329 return MCDisassembler::Fail;
3331
3332 return S;
3333}
3334
3335static DecodeStatus DecodeT2LoadImm12(MCInst &Inst, unsigned Insn,
3336 uint64_t Address,
3337 const MCDisassembler *Decoder) {
3339
3340 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3341 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
3342 unsigned imm = fieldFromInstruction(Insn, 0, 12);
3343 imm |= (Rn << 13);
3344
3345 const FeatureBitset &featureBits =
3346 Decoder->getSubtargetInfo().getFeatureBits();
3347
3348 bool hasMP = featureBits[ARM::FeatureMP];
3349 bool hasV7Ops = featureBits[ARM::HasV7Ops];
3350
3351 if (Rn == 15) {
3352 switch (Inst.getOpcode()) {
3353 case ARM::t2LDRi12:
3354 Inst.setOpcode(ARM::t2LDRpci);
3355 break;
3356 case ARM::t2LDRHi12:
3357 Inst.setOpcode(ARM::t2LDRHpci);
3358 break;
3359 case ARM::t2LDRSHi12:
3360 Inst.setOpcode(ARM::t2LDRSHpci);
3361 break;
3362 case ARM::t2LDRBi12:
3363 Inst.setOpcode(ARM::t2LDRBpci);
3364 break;
3365 case ARM::t2LDRSBi12:
3366 Inst.setOpcode(ARM::t2LDRSBpci);
3367 break;
3368 case ARM::t2PLDi12:
3369 Inst.setOpcode(ARM::t2PLDpci);
3370 break;
3371 case ARM::t2PLIi12:
3372 Inst.setOpcode(ARM::t2PLIpci);
3373 break;
3374 default:
3375 return MCDisassembler::Fail;
3376 }
3377 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder);
3378 }
3379
3380 if (Rt == 15) {
3381 switch (Inst.getOpcode()) {
3382 case ARM::t2LDRSHi12:
3383 return MCDisassembler::Fail;
3384 case ARM::t2LDRHi12:
3385 Inst.setOpcode(ARM::t2PLDWi12);
3386 break;
3387 case ARM::t2LDRSBi12:
3388 Inst.setOpcode(ARM::t2PLIi12);
3389 break;
3390 default:
3391 break;
3392 }
3393 }
3394
3395 switch (Inst.getOpcode()) {
3396 case ARM::t2PLDi12:
3397 break;
3398 case ARM::t2PLIi12:
3399 if (!hasV7Ops)
3400 return MCDisassembler::Fail;
3401 break;
3402 case ARM::t2PLDWi12:
3403 if (!hasV7Ops || !hasMP)
3404 return MCDisassembler::Fail;
3405 break;
3406 default:
3407 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3408 return MCDisassembler::Fail;
3409 }
3410
3411 if (!Check(S, DecodeT2AddrModeImm12(Inst, imm, Address, Decoder)))
3412 return MCDisassembler::Fail;
3413 return S;
3414}
3415
3416static DecodeStatus DecodeT2LoadT(MCInst &Inst, unsigned Insn, uint64_t Address,
3417 const MCDisassembler *Decoder) {
3419
3420 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3421 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
3422 unsigned imm = fieldFromInstruction(Insn, 0, 8);
3423 imm |= (Rn << 9);
3424
3425 if (Rn == 15) {
3426 switch (Inst.getOpcode()) {
3427 case ARM::t2LDRT:
3428 Inst.setOpcode(ARM::t2LDRpci);
3429 break;
3430 case ARM::t2LDRBT:
3431 Inst.setOpcode(ARM::t2LDRBpci);
3432 break;
3433 case ARM::t2LDRHT:
3434 Inst.setOpcode(ARM::t2LDRHpci);
3435 break;
3436 case ARM::t2LDRSBT:
3437 Inst.setOpcode(ARM::t2LDRSBpci);
3438 break;
3439 case ARM::t2LDRSHT:
3440 Inst.setOpcode(ARM::t2LDRSHpci);
3441 break;
3442 default:
3443 return MCDisassembler::Fail;
3444 }
3445 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder);
3446 }
3447
3448 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder)))
3449 return MCDisassembler::Fail;
3450 if (!Check(S, DecodeT2AddrModeImm8(Inst, imm, Address, Decoder)))
3451 return MCDisassembler::Fail;
3452 return S;
3453}
3454
3455static DecodeStatus DecodeT2Imm8S4(MCInst &Inst, unsigned Val, uint64_t Address,
3456 const MCDisassembler *Decoder) {
3457 if (Val == 0)
3458 Inst.addOperand(MCOperand::createImm(INT32_MIN));
3459 else {
3460 int imm = Val & 0xFF;
3461
3462 if (!(Val & 0x100)) imm *= -1;
3463 Inst.addOperand(MCOperand::createImm(imm * 4));
3464 }
3465
3467}
3468
3469static DecodeStatus DecodeT2Imm7S4(MCInst &Inst, unsigned Val, uint64_t Address,
3470 const MCDisassembler *Decoder) {
3471 if (Val == 0)
3472 Inst.addOperand(MCOperand::createImm(INT32_MIN));
3473 else {
3474 int imm = Val & 0x7F;
3475
3476 if (!(Val & 0x80))
3477 imm *= -1;
3478 Inst.addOperand(MCOperand::createImm(imm * 4));
3479 }
3480
3482}
3483
3484static DecodeStatus DecodeT2AddrModeImm8s4(MCInst &Inst, unsigned Val,
3485 uint64_t Address,
3486 const MCDisassembler *Decoder) {
3488
3489 unsigned Rn = fieldFromInstruction(Val, 9, 4);
3490 unsigned imm = fieldFromInstruction(Val, 0, 9);
3491
3492 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3493 return MCDisassembler::Fail;
3494 if (!Check(S, DecodeT2Imm8S4(Inst, imm, Address, Decoder)))
3495 return MCDisassembler::Fail;
3496
3497 return S;
3498}
3499
3500static DecodeStatus DecodeT2AddrModeImm7s4(MCInst &Inst, unsigned Val,
3501 uint64_t Address,
3502 const MCDisassembler *Decoder) {
3504
3505 unsigned Rn = fieldFromInstruction(Val, 8, 4);
3506 unsigned imm = fieldFromInstruction(Val, 0, 8);
3507
3508 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
3509 return MCDisassembler::Fail;
3510 if (!Check(S, DecodeT2Imm7S4(Inst, imm, Address, Decoder)))
3511 return MCDisassembler::Fail;
3512
3513 return S;
3514}
3515
3517 uint64_t Address,
3518 const MCDisassembler *Decoder) {
3520
3521 unsigned Rn = fieldFromInstruction(Val, 8, 4);
3522 unsigned imm = fieldFromInstruction(Val, 0, 8);
3523
3524 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
3525 return MCDisassembler::Fail;
3526
3528
3529 return S;
3530}
3531
3532template <int shift>
3533static DecodeStatus DecodeT2Imm7(MCInst &Inst, unsigned Val, uint64_t Address,
3534 const MCDisassembler *Decoder) {
3535 int imm = Val & 0x7F;
3536 if (Val == 0)
3537 imm = INT32_MIN;
3538 else if (!(Val & 0x80))
3539 imm *= -1;
3540 if (imm != INT32_MIN)
3541 imm *= (1U << shift);
3543
3545}
3546
3547template <int shift>
3548static DecodeStatus DecodeTAddrModeImm7(MCInst &Inst, unsigned Val,
3549 uint64_t Address,
3550 const MCDisassembler *Decoder) {
3552
3553 unsigned Rn = fieldFromInstruction(Val, 8, 3);
3554 unsigned imm = fieldFromInstruction(Val, 0, 8);
3555
3556 if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder)))
3557 return MCDisassembler::Fail;
3558 if (!Check(S, DecodeT2Imm7<shift>(Inst, imm, Address, Decoder)))
3559 return MCDisassembler::Fail;
3560
3561 return S;
3562}
3563
3564template <int shift, int WriteBack>
3565static DecodeStatus DecodeT2AddrModeImm7(MCInst &Inst, unsigned Val,
3566 uint64_t Address,
3567 const MCDisassembler *Decoder) {
3569
3570 unsigned Rn = fieldFromInstruction(Val, 8, 4);
3571 unsigned imm = fieldFromInstruction(Val, 0, 8);
3572 if (WriteBack) {
3573 if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder)))
3574 return MCDisassembler::Fail;
3575 } else if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
3576 return MCDisassembler::Fail;
3577 if (!Check(S, DecodeT2Imm7<shift>(Inst, imm, Address, Decoder)))
3578 return MCDisassembler::Fail;
3579
3580 return S;
3581}
3582
3583static DecodeStatus DecodeT2LdStPre(MCInst &Inst, unsigned Insn,
3584 uint64_t Address,
3585 const MCDisassembler *Decoder) {
3587
3588 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
3589 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3590 unsigned addr = fieldFromInstruction(Insn, 0, 8);
3591 addr |= fieldFromInstruction(Insn, 9, 1) << 8;
3592 addr |= Rn << 9;
3593 unsigned load = fieldFromInstruction(Insn, 20, 1);
3594
3595 if (Rn == 15) {
3596 switch (Inst.getOpcode()) {
3597 case ARM::t2LDR_PRE:
3598 case ARM::t2LDR_POST:
3599 Inst.setOpcode(ARM::t2LDRpci);
3600 break;
3601 case ARM::t2LDRB_PRE:
3602 case ARM::t2LDRB_POST:
3603 Inst.setOpcode(ARM::t2LDRBpci);
3604 break;
3605 case ARM::t2LDRH_PRE:
3606 case ARM::t2LDRH_POST:
3607 Inst.setOpcode(ARM::t2LDRHpci);
3608 break;
3609 case ARM::t2LDRSB_PRE:
3610 case ARM::t2LDRSB_POST:
3611 if (Rt == 15)
3612 Inst.setOpcode(ARM::t2PLIpci);
3613 else
3614 Inst.setOpcode(ARM::t2LDRSBpci);
3615 break;
3616 case ARM::t2LDRSH_PRE:
3617 case ARM::t2LDRSH_POST:
3618 Inst.setOpcode(ARM::t2LDRSHpci);
3619 break;
3620 default:
3621 return MCDisassembler::Fail;
3622 }
3623 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder);
3624 }
3625
3626 if (!load) {
3627 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3628 return MCDisassembler::Fail;
3629 }
3630
3631 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3632 return MCDisassembler::Fail;
3633
3634 if (load) {
3635 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3636 return MCDisassembler::Fail;
3637 }
3638
3639 if (!Check(S, DecodeT2AddrModeImm8(Inst, addr, Address, Decoder)))
3640 return MCDisassembler::Fail;
3641
3642 return S;
3643}
3644
3646 uint64_t Address,
3647 const MCDisassembler *Decoder) {
3648 unsigned imm = fieldFromInstruction(Insn, 0, 7);
3649
3650 Inst.addOperand(MCOperand::createReg(ARM::SP));
3651 Inst.addOperand(MCOperand::createReg(ARM::SP));
3653
3655}
3656
3658 uint64_t Address,
3659 const MCDisassembler *Decoder) {
3661
3662 if (Inst.getOpcode() == ARM::tADDrSP) {
3663 unsigned Rdm = fieldFromInstruction(Insn, 0, 3);
3664 Rdm |= fieldFromInstruction(Insn, 7, 1) << 3;
3665
3666 if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder)))
3667 return MCDisassembler::Fail;
3668 Inst.addOperand(MCOperand::createReg(ARM::SP));
3669 if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder)))
3670 return MCDisassembler::Fail;
3671 } else if (Inst.getOpcode() == ARM::tADDspr) {
3672 unsigned Rm = fieldFromInstruction(Insn, 3, 4);
3673
3674 Inst.addOperand(MCOperand::createReg(ARM::SP));
3675 Inst.addOperand(MCOperand::createReg(ARM::SP));
3676 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3677 return MCDisassembler::Fail;
3678 }
3679
3680 return S;
3681}
3682
3684 uint64_t Address,
3685 const MCDisassembler *Decoder) {
3686 unsigned imod = fieldFromInstruction(Insn, 4, 1) | 0x2;
3687 unsigned flags = fieldFromInstruction(Insn, 0, 3);
3688
3689 Inst.addOperand(MCOperand::createImm(imod));
3690 Inst.addOperand(MCOperand::createImm(flags));
3691
3693}
3694
3695static DecodeStatus DecodePostIdxReg(MCInst &Inst, unsigned Insn,
3696 uint64_t Address,
3697 const MCDisassembler *Decoder) {
3699 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
3700 unsigned add = fieldFromInstruction(Insn, 4, 1);
3701
3702 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
3703 return MCDisassembler::Fail;
3705
3706 return S;
3707}
3708
3709static DecodeStatus DecodeMveAddrModeRQ(MCInst &Inst, unsigned Insn,
3710 uint64_t Address,
3711 const MCDisassembler *Decoder) {
3713 unsigned Rn = fieldFromInstruction(Insn, 3, 4);
3714 unsigned Qm = fieldFromInstruction(Insn, 0, 3);
3715
3716 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
3717 return MCDisassembler::Fail;
3718 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qm, Address, Decoder)))
3719 return MCDisassembler::Fail;
3720
3721 return S;
3722}
3723
3724template <int shift>
3725static DecodeStatus DecodeMveAddrModeQ(MCInst &Inst, unsigned Insn,
3726 uint64_t Address,
3727 const MCDisassembler *Decoder) {
3729 unsigned Qm = fieldFromInstruction(Insn, 8, 3);
3730 int imm = fieldFromInstruction(Insn, 0, 7);
3731
3732 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qm, Address, Decoder)))
3733 return MCDisassembler::Fail;
3734
3735 if(!fieldFromInstruction(Insn, 7, 1)) {
3736 if (imm == 0)
3737 imm = INT32_MIN; // indicate -0
3738 else
3739 imm *= -1;
3740 }
3741 if (imm != INT32_MIN)
3742 imm *= (1U << shift);
3744
3745 return S;
3746}
3747
3748static DecodeStatus DecodeThumbBLXOffset(MCInst &Inst, unsigned Val,
3749 uint64_t Address,
3750 const MCDisassembler *Decoder) {
3751 // Val is passed in as S:J1:J2:imm10H:imm10L:'0'
3752 // Note only one trailing zero not two. Also the J1 and J2 values are from
3753 // the encoded instruction. So here change to I1 and I2 values via:
3754 // I1 = NOT(J1 EOR S);
3755 // I2 = NOT(J2 EOR S);
3756 // and build the imm32 with two trailing zeros as documented:
3757 // imm32 = SignExtend(S:I1:I2:imm10H:imm10L:'00', 32);
3758 unsigned S = (Val >> 23) & 1;
3759 unsigned J1 = (Val >> 22) & 1;
3760 unsigned J2 = (Val >> 21) & 1;
3761 unsigned I1 = !(J1 ^ S);
3762 unsigned I2 = !(J2 ^ S);
3763 unsigned tmp = (Val & ~0x600000) | (I1 << 22) | (I2 << 21);
3764 int imm32 = SignExtend32<25>(tmp << 1);
3765
3766 if (!tryAddingSymbolicOperand(Address,
3767 (Address & ~2u) + imm32 + 4,
3768 true, 4, Inst, Decoder))
3769 Inst.addOperand(MCOperand::createImm(imm32));
3771}
3772
3773static DecodeStatus DecodeCoprocessor(MCInst &Inst, unsigned Val,
3774 uint64_t Address,
3775 const MCDisassembler *Decoder) {
3776 if (Val == 0xA || Val == 0xB)
3777 return MCDisassembler::Fail;
3778
3779 const FeatureBitset &featureBits =
3780 Decoder->getSubtargetInfo().getFeatureBits();
3781
3782 if (!isValidCoprocessorNumber(Val, featureBits))
3783 return MCDisassembler::Fail;
3784
3787}
3788
3789static DecodeStatus DecodeThumbTableBranch(MCInst &Inst, unsigned Insn,
3790 uint64_t Address,
3791 const MCDisassembler *Decoder) {
3792 const FeatureBitset &FeatureBits =
3793 Decoder->getSubtargetInfo().getFeatureBits();
3795
3796 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3797 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
3798
3799 if (Rn == 13 && !FeatureBits[ARM::HasV8Ops]) S = MCDisassembler::SoftFail;
3800 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3801 return MCDisassembler::Fail;
3802 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder)))
3803 return MCDisassembler::Fail;
3804 return S;
3805}
3806
3807static DecodeStatus DecodeMemBarrierOption(MCInst &Inst, unsigned Val,
3808 uint64_t Address,
3809 const MCDisassembler *Decoder) {
3810 if (Val & ~0xf)
3811 return MCDisassembler::Fail;
3812
3815}
3816
3818 uint64_t Address,
3819 const MCDisassembler *Decoder) {
3821
3822 unsigned pred = fieldFromInstruction(Insn, 22, 4);
3823 if (pred == 0xE || pred == 0xF) {
3824 unsigned opc = fieldFromInstruction(Insn, 4, 28);
3825 switch (opc) {
3826 default:
3827 return MCDisassembler::Fail;
3828 case 0xf3bf8f4:
3829 Inst.setOpcode(ARM::t2DSB);
3830 break;
3831 case 0xf3bf8f5:
3832 Inst.setOpcode(ARM::t2DMB);
3833 break;
3834 case 0xf3bf8f6:
3835 Inst.setOpcode(ARM::t2ISB);
3836 break;
3837 }
3838
3839 unsigned imm = fieldFromInstruction(Insn, 0, 4);
3840 return DecodeMemBarrierOption(Inst, imm, Address, Decoder);
3841 }
3842
3843 unsigned brtarget = fieldFromInstruction(Insn, 0, 11) << 1;
3844 brtarget |= fieldFromInstruction(Insn, 11, 1) << 19;
3845 brtarget |= fieldFromInstruction(Insn, 13, 1) << 18;
3846 brtarget |= fieldFromInstruction(Insn, 16, 6) << 12;
3847 brtarget |= fieldFromInstruction(Insn, 26, 1) << 20;
3848
3849 if (!Check(S, DecodeT2BROperand(Inst, brtarget, Address, Decoder)))
3850 return MCDisassembler::Fail;
3851 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
3852 return MCDisassembler::Fail;
3853
3854 return S;
3855}
3856
3857// Decode a shifted immediate operand. These basically consist
3858// of an 8-bit value, and a 4-bit directive that specifies either
3859// a splat operation or a rotation.
3860static DecodeStatus DecodeT2SOImm(MCInst &Inst, unsigned Val, uint64_t Address,
3861 const MCDisassembler *Decoder) {
3862 unsigned ctrl = fieldFromInstruction(Val, 10, 2);
3863 if (ctrl == 0) {
3864 unsigned byte = fieldFromInstruction(Val, 8, 2);
3865 unsigned imm = fieldFromInstruction(Val, 0, 8);
3866 switch (byte) {
3867 case 0:
3869 break;
3870 case 1:
3871 Inst.addOperand(MCOperand::createImm((imm << 16) | imm));
3872 break;
3873 case 2:
3874 Inst.addOperand(MCOperand::createImm((imm << 24) | (imm << 8)));
3875 break;
3876 case 3:
3877 Inst.addOperand(MCOperand::createImm((imm << 24) | (imm << 16) |
3878 (imm << 8) | imm));
3879 break;
3880 }
3881 } else {
3882 unsigned unrot = fieldFromInstruction(Val, 0, 7) | 0x80;
3883 unsigned rot = fieldFromInstruction(Val, 7, 5);
3884 unsigned imm = llvm::rotr<uint32_t>(unrot, rot);
3886 }
3887
3889}
3890
3892 uint64_t Address,
3893 const MCDisassembler *Decoder) {
3894 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<9>(Val<<1) + 4,
3895 true, 2, Inst, Decoder))
3898}
3899
3901 uint64_t Address,
3902 const MCDisassembler *Decoder) {
3903 // Val is passed in as S:J1:J2:imm10:imm11
3904 // Note no trailing zero after imm11. Also the J1 and J2 values are from
3905 // the encoded instruction. So here change to I1 and I2 values via:
3906 // I1 = NOT(J1 EOR S);
3907 // I2 = NOT(J2 EOR S);
3908 // and build the imm32 with one trailing zero as documented:
3909 // imm32 = SignExtend(S:I1:I2:imm10:imm11:'0', 32);
3910 unsigned S = (Val >> 23) & 1;
3911 unsigned J1 = (Val >> 22) & 1;
3912 unsigned J2 = (Val >> 21) & 1;
3913 unsigned I1 = !(J1 ^ S);
3914 unsigned I2 = !(J2 ^ S);
3915 unsigned tmp = (Val & ~0x600000) | (I1 << 22) | (I2 << 21);
3916 int imm32 = SignExtend32<25>(tmp << 1);
3917
3918 if (!tryAddingSymbolicOperand(Address, Address + imm32 + 4,
3919 true, 4, Inst, Decoder))
3920 Inst.addOperand(MCOperand::createImm(imm32));
3922}
3923
3925 uint64_t Address,
3926 const MCDisassembler *Decoder) {
3927 if (Val & ~0xf)
3928 return MCDisassembler::Fail;
3929
3932}
3933
3934static DecodeStatus DecodeMSRMask(MCInst &Inst, unsigned Val, uint64_t Address,
3935 const MCDisassembler *Decoder) {
3937 const FeatureBitset &FeatureBits =
3938 Decoder->getSubtargetInfo().getFeatureBits();
3939
3940 if (FeatureBits[ARM::FeatureMClass]) {
3941 unsigned ValLow = Val & 0xff;
3942
3943 // Validate the SYSm value first.
3944 switch (ValLow) {
3945 case 0: // apsr
3946 case 1: // iapsr
3947 case 2: // eapsr
3948 case 3: // xpsr
3949 case 5: // ipsr
3950 case 6: // epsr
3951 case 7: // iepsr
3952 case 8: // msp
3953 case 9: // psp
3954 case 16: // primask
3955 case 20: // control
3956 break;
3957 case 17: // basepri
3958 case 18: // basepri_max
3959 case 19: // faultmask
3960 if (!(FeatureBits[ARM::HasV7Ops]))
3961 // Values basepri, basepri_max and faultmask are only valid for v7m.
3962 return MCDisassembler::Fail;
3963 break;
3964 case 0x8a: // msplim_ns
3965 case 0x8b: // psplim_ns
3966 case 0x91: // basepri_ns
3967 case 0x93: // faultmask_ns
3968 if (!(FeatureBits[ARM::HasV8MMainlineOps]))
3969 return MCDisassembler::Fail;
3970 [[fallthrough]];
3971 case 10: // msplim
3972 case 11: // psplim
3973 case 0x88: // msp_ns
3974 case 0x89: // psp_ns
3975 case 0x90: // primask_ns
3976 case 0x94: // control_ns
3977 case 0x98: // sp_ns
3978 if (!(FeatureBits[ARM::Feature8MSecExt]))
3979 return MCDisassembler::Fail;
3980 break;
3981 case 0x20: // pac_key_p_0
3982 case 0x21: // pac_key_p_1
3983 case 0x22: // pac_key_p_2
3984 case 0x23: // pac_key_p_3
3985 case 0x24: // pac_key_u_0
3986 case 0x25: // pac_key_u_1
3987 case 0x26: // pac_key_u_2
3988 case 0x27: // pac_key_u_3
3989 case 0xa0: // pac_key_p_0_ns
3990 case 0xa1: // pac_key_p_1_ns
3991 case 0xa2: // pac_key_p_2_ns
3992 case 0xa3: // pac_key_p_3_ns
3993 case 0xa4: // pac_key_u_0_ns
3994 case 0xa5: // pac_key_u_1_ns
3995 case 0xa6: // pac_key_u_2_ns
3996 case 0xa7: // pac_key_u_3_ns
3997 if (!(FeatureBits[ARM::FeaturePACBTI]))
3998 return MCDisassembler::Fail;
3999 break;
4000 default:
4001 // Architecturally defined as unpredictable
4003 break;
4004 }
4005
4006 if (Inst.getOpcode() == ARM::t2MSR_M) {
4007 unsigned Mask = fieldFromInstruction(Val, 10, 2);
4008 if (!(FeatureBits[ARM::HasV7Ops])) {
4009 // The ARMv6-M MSR bits {11-10} can be only 0b10, other values are
4010 // unpredictable.
4011 if (Mask != 2)
4013 }
4014 else {
4015 // The ARMv7-M architecture stores an additional 2-bit mask value in
4016 // MSR bits {11-10}. The mask is used only with apsr, iapsr, eapsr and
4017 // xpsr, it has to be 0b10 in other cases. Bit mask{1} indicates if
4018 // the NZCVQ bits should be moved by the instruction. Bit mask{0}
4019 // indicates the move for the GE{3:0} bits, the mask{0} bit can be set
4020 // only if the processor includes the DSP extension.
4021 if (Mask == 0 || (Mask != 2 && ValLow > 3) ||
4022 (!(FeatureBits[ARM::FeatureDSP]) && (Mask & 1)))
4024 }
4025 }
4026 } else {
4027 // A/R class
4028 if (Val == 0)
4029 return MCDisassembler::Fail;
4030 }
4032 return S;
4033}
4034
4035static DecodeStatus DecodeBankedReg(MCInst &Inst, unsigned Val,
4036 uint64_t Address,
4037 const MCDisassembler *Decoder) {
4038 unsigned R = fieldFromInstruction(Val, 5, 1);
4039 unsigned SysM = fieldFromInstruction(Val, 0, 5);
4040
4041 // The table of encodings for these banked registers comes from B9.2.3 of the
4042 // ARM ARM. There are patterns, but nothing regular enough to make this logic
4043 // neater. So by fiat, these values are UNPREDICTABLE:
4044 if (!ARMBankedReg::lookupBankedRegByEncoding((R << 5) | SysM))
4045 return MCDisassembler::Fail;
4046
4049}
4050
4051static DecodeStatus DecodeDoubleRegLoad(MCInst &Inst, unsigned Insn,
4052 uint64_t Address,
4053 const MCDisassembler *Decoder) {
4055
4056 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4057 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4058 unsigned pred = fieldFromInstruction(Insn, 28, 4);
4059
4060 if (Rn == 0xF)
4062
4063 if (!Check(S, DecodeGPRPairRegisterClass(Inst, Rt, Address, Decoder)))
4064 return MCDisassembler::Fail;
4065 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4066 return MCDisassembler::Fail;
4067 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
4068 return MCDisassembler::Fail;
4069
4070 return S;
4071}
4072
4073static DecodeStatus DecodeDoubleRegStore(MCInst &Inst, unsigned Insn,
4074 uint64_t Address,
4075 const MCDisassembler *Decoder) {
4077
4078 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
4079 unsigned Rt = fieldFromInstruction(Insn, 0, 4);
4080 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4081 unsigned pred = fieldFromInstruction(Insn, 28, 4);
4082
4083 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)))
4084 return MCDisassembler::Fail;
4085
4086 if (Rn == 0xF || Rd == Rn || Rd == Rt || Rd == Rt+1)
4088
4089 if (!Check(S, DecodeGPRPairRegisterClass(Inst, Rt, Address, Decoder)))
4090 return MCDisassembler::Fail;
4091 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4092 return MCDisassembler::Fail;
4093 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
4094 return MCDisassembler::Fail;
4095
4096 return S;
4097}
4098
4099static DecodeStatus DecodeLDRPreImm(MCInst &Inst, unsigned Insn,
4100 uint64_t Address,
4101 const MCDisassembler *Decoder) {
4103
4104 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4105 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4106 unsigned imm = fieldFromInstruction(Insn, 0, 12);
4107 imm |= fieldFromInstruction(Insn, 16, 4) << 13;
4108 imm |= fieldFromInstruction(Insn, 23, 1) << 12;
4109 unsigned pred = fieldFromInstruction(Insn, 28, 4);
4110
4111 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail;
4112
4113 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
4114 return MCDisassembler::Fail;
4115 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4116 return MCDisassembler::Fail;
4117 if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder)))
4118 return MCDisassembler::Fail;
4119 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
4120 return MCDisassembler::Fail;
4121
4122 return S;
4123}
4124
4125static DecodeStatus DecodeLDRPreReg(MCInst &Inst, unsigned Insn,
4126 uint64_t Address,
4127 const MCDisassembler *Decoder) {
4129
4130 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4131 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4132 unsigned imm = fieldFromInstruction(Insn, 0, 12);
4133 imm |= fieldFromInstruction(Insn, 16, 4) << 13;
4134 imm |= fieldFromInstruction(Insn, 23, 1) << 12;
4135 unsigned pred = fieldFromInstruction(Insn, 28, 4);
4136 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
4137
4138 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail;
4139 if (Rm == 0xF) S = MCDisassembler::SoftFail;
4140
4141 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
4142 return MCDisassembler::Fail;
4143 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4144 return MCDisassembler::Fail;
4145 if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder)))
4146 return MCDisassembler::Fail;
4147 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
4148 return MCDisassembler::Fail;
4149
4150 return S;
4151}
4152
4153static DecodeStatus DecodeSTRPreImm(MCInst &Inst, unsigned Insn,
4154 uint64_t Address,
4155 const MCDisassembler *Decoder) {
4157
4158 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4159 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4160 unsigned imm = fieldFromInstruction(Insn, 0, 12);
4161 imm |= fieldFromInstruction(Insn, 16, 4) << 13;
4162 imm |= fieldFromInstruction(Insn, 23, 1) << 12;
4163 unsigned pred = fieldFromInstruction(Insn, 28, 4);
4164
4165 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail;
4166
4167 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4168 return MCDisassembler::Fail;
4169 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
4170 return MCDisassembler::Fail;
4171 if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder)))
4172 return MCDisassembler::Fail;
4173 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
4174 return MCDisassembler::Fail;
4175
4176 return S;
4177}
4178
4179static DecodeStatus DecodeSTRPreReg(MCInst &Inst, unsigned Insn,
4180 uint64_t Address,
4181 const MCDisassembler *Decoder) {
4183
4184 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4185 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4186 unsigned imm = fieldFromInstruction(Insn, 0, 12);
4187 imm |= fieldFromInstruction(Insn, 16, 4) << 13;
4188 imm |= fieldFromInstruction(Insn, 23, 1) << 12;
4189 unsigned pred = fieldFromInstruction(Insn, 28, 4);
4190
4191 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail;
4192
4193 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4194 return MCDisassembler::Fail;
4195 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
4196 return MCDisassembler::Fail;
4197 if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder)))
4198 return MCDisassembler::Fail;
4199 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
4200 return MCDisassembler::Fail;
4201
4202 return S;
4203}
4204
4205static DecodeStatus DecodeVLD1LN(MCInst &Inst, unsigned Insn, uint64_t Address,
4206 const MCDisassembler *Decoder) {
4208
4209 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4210 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
4211 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
4212 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
4213 unsigned size = fieldFromInstruction(Insn, 10, 2);
4214
4215 unsigned align = 0;
4216 unsigned index = 0;
4217 switch (size) {
4218 default:
4219 return MCDisassembler::Fail;
4220 case 0:
4221 if (fieldFromInstruction(Insn, 4, 1))
4222 return MCDisassembler::Fail; // UNDEFINED
4223 index = fieldFromInstruction(Insn, 5, 3);
4224 break;
4225 case 1:
4226 if (fieldFromInstruction(Insn, 5, 1))
4227 return MCDisassembler::Fail; // UNDEFINED
4228 index = fieldFromInstruction(Insn, 6, 2);
4229 if (fieldFromInstruction(Insn, 4, 1))
4230 align = 2;
4231 break;
4232 case 2:
4233 if (fieldFromInstruction(Insn, 6, 1))
4234 return MCDisassembler::Fail; // UNDEFINED
4235 index = fieldFromInstruction(Insn, 7, 1);
4236
4237 switch (fieldFromInstruction(Insn, 4, 2)) {
4238 case 0 :
4239 align = 0; break;
4240 case 3:
4241 align = 4; break;
4242 default:
4243 return MCDisassembler::Fail;
4244 }
4245 break;
4246 }
4247
4248 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4249 return MCDisassembler::Fail;
4250 if (Rm != 0xF) { // Writeback
4251 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4252 return MCDisassembler::Fail;
4253 }
4254 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4255 return MCDisassembler::Fail;
4256 Inst.addOperand(MCOperand::createImm(align));
4257 if (Rm != 0xF) {
4258 if (Rm != 0xD) {
4259 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
4260 return MCDisassembler::Fail;
4261 } else
4263 }
4264
4265 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4266 return MCDisassembler::Fail;
4267 Inst.addOperand(MCOperand::createImm(index));
4268
4269 return S;
4270}
4271
4272static DecodeStatus DecodeVST1LN(MCInst &Inst, unsigned Insn, uint64_t Address,
4273 const MCDisassembler *Decoder) {
4275
4276 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4277 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
4278 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
4279 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
4280 unsigned size = fieldFromInstruction(Insn, 10, 2);
4281
4282 unsigned align = 0;
4283 unsigned index = 0;
4284 switch (size) {
4285 default:
4286 return MCDisassembler::Fail;
4287 case 0:
4288 if (fieldFromInstruction(Insn, 4, 1))
4289 return MCDisassembler::Fail; // UNDEFINED
4290 index = fieldFromInstruction(Insn, 5, 3);
4291 break;
4292 case 1:
4293 if (fieldFromInstruction(Insn, 5, 1))
4294 return MCDisassembler::Fail; // UNDEFINED
4295 index = fieldFromInstruction(Insn, 6, 2);
4296 if (fieldFromInstruction(Insn, 4, 1))
4297 align = 2;
4298 break;
4299 case 2:
4300 if (fieldFromInstruction(Insn, 6, 1))
4301 return MCDisassembler::Fail; // UNDEFINED
4302 index = fieldFromInstruction(Insn, 7, 1);
4303
4304 switch (fieldFromInstruction(Insn, 4, 2)) {
4305 case 0:
4306 align = 0; break;
4307 case 3:
4308 align = 4; break;
4309 default:
4310 return MCDisassembler::Fail;
4311 }
4312 break;
4313 }
4314
4315 if (Rm != 0xF) { // Writeback
4316 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4317 return MCDisassembler::Fail;
4318 }
4319 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4320 return MCDisassembler::Fail;
4321 Inst.addOperand(MCOperand::createImm(align));
4322 if (Rm != 0xF) {
4323 if (Rm != 0xD) {
4324 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
4325 return MCDisassembler::Fail;
4326 } else
4328 }
4329
4330 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4331 return MCDisassembler::Fail;
4332 Inst.addOperand(MCOperand::createImm(index));
4333
4334 return S;
4335}
4336
4337static DecodeStatus DecodeVLD2LN(MCInst &Inst, unsigned Insn, uint64_t Address,
4338 const MCDisassembler *Decoder) {
4340
4341 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4342 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
4343 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
4344 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
4345 unsigned size = fieldFromInstruction(Insn, 10, 2);
4346
4347 unsigned align = 0;
4348 unsigned index = 0;
4349 unsigned inc = 1;
4350 switch (size) {
4351 default:
4352 return MCDisassembler::Fail;
4353 case 0:
4354 index = fieldFromInstruction(Insn, 5, 3);
4355 if (fieldFromInstruction(Insn, 4, 1))
4356 align = 2;
4357 break;
4358 case 1:
4359 index = fieldFromInstruction(Insn, 6, 2);
4360 if (fieldFromInstruction(Insn, 4, 1))
4361 align = 4;
4362 if (fieldFromInstruction(Insn, 5, 1))
4363 inc = 2;
4364 break;
4365 case 2:
4366 if (fieldFromInstruction(Insn, 5, 1))
4367 return MCDisassembler::Fail; // UNDEFINED
4368 index = fieldFromInstruction(Insn, 7, 1);
4369 if (fieldFromInstruction(Insn, 4, 1) != 0)
4370 align = 8;
4371 if (fieldFromInstruction(Insn, 6, 1))
4372 inc = 2;
4373 break;
4374 }
4375
4376 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4377 return MCDisassembler::Fail;
4378 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
4379 return MCDisassembler::Fail;
4380 if (Rm != 0xF) { // Writeback
4381 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4382 return MCDisassembler::Fail;
4383 }
4384 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4385 return MCDisassembler::Fail;
4386 Inst.addOperand(MCOperand::createImm(align));
4387 if (Rm != 0xF) {
4388 if (Rm != 0xD) {
4389 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
4390 return MCDisassembler::Fail;
4391 } else
4393 }
4394
4395 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4396 return MCDisassembler::Fail;
4397 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
4398 return MCDisassembler::Fail;
4399 Inst.addOperand(MCOperand::createImm(index));
4400
4401 return S;
4402}
4403
4404static DecodeStatus DecodeVST2LN(MCInst &Inst, unsigned Insn, uint64_t Address,
4405 const MCDisassembler *Decoder) {
4407
4408 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4409 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
4410 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
4411 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
4412 unsigned size = fieldFromInstruction(Insn, 10, 2);
4413
4414 unsigned align = 0;
4415 unsigned index = 0;
4416 unsigned inc = 1;
4417 switch (size) {
4418 default:
4419 return MCDisassembler::Fail;
4420 case 0:
4421 index = fieldFromInstruction(Insn, 5, 3);
4422 if (fieldFromInstruction(Insn, 4, 1))
4423 align = 2;
4424 break;
4425 case 1:
4426 index = fieldFromInstruction(Insn, 6, 2);
4427 if (fieldFromInstruction(Insn, 4, 1))
4428 align = 4;
4429 if (fieldFromInstruction(Insn, 5, 1))
4430 inc = 2;
4431 break;
4432 case 2:
4433 if (fieldFromInstruction(Insn, 5, 1))
4434 return MCDisassembler::Fail; // UNDEFINED
4435 index = fieldFromInstruction(Insn, 7, 1);
4436 if (fieldFromInstruction(Insn, 4, 1) != 0)
4437 align = 8;
4438 if (fieldFromInstruction(Insn, 6, 1))
4439 inc = 2;
4440 break;
4441 }
4442
4443 if (Rm != 0xF) { // Writeback
4444 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4445 return MCDisassembler::Fail;
4446 }
4447 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4448 return MCDisassembler::Fail;
4449 Inst.addOperand(MCOperand::createImm(align));
4450 if (Rm != 0xF) {
4451 if (Rm != 0xD) {
4452 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
4453 return MCDisassembler::Fail;
4454 } else
4456 }
4457
4458 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4459 return MCDisassembler::Fail;
4460 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
4461 return MCDisassembler::Fail;
4462 Inst.addOperand(MCOperand::createImm(index));
4463
4464 return S;
4465}
4466
4467static DecodeStatus DecodeVLD3LN(MCInst &Inst, unsigned Insn, uint64_t Address,
4468 const MCDisassembler *Decoder) {
4470
4471 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4472 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
4473 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
4474 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
4475 unsigned size = fieldFromInstruction(Insn, 10, 2);
4476
4477 unsigned align = 0;
4478 unsigned index = 0;
4479 unsigned inc = 1;
4480 switch (size) {
4481 default:
4482 return MCDisassembler::Fail;
4483 case 0:
4484 if (fieldFromInstruction(Insn, 4, 1))
4485 return MCDisassembler::Fail; // UNDEFINED
4486 index = fieldFromInstruction(Insn, 5, 3);
4487 break;
4488 case 1:
4489 if (fieldFromInstruction(Insn, 4, 1))
4490 return MCDisassembler::Fail; // UNDEFINED
4491 index = fieldFromInstruction(Insn, 6, 2);
4492 if (fieldFromInstruction(Insn, 5, 1))
4493 inc = 2;
4494 break;
4495 case 2:
4496 if (fieldFromInstruction(Insn, 4, 2))
4497 return MCDisassembler::Fail; // UNDEFINED
4498 index = fieldFromInstruction(Insn, 7, 1);
4499 if (fieldFromInstruction(Insn, 6, 1))
4500 inc = 2;
4501 break;
4502 }
4503
4504 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4505 return MCDisassembler::Fail;
4506 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
4507 return MCDisassembler::Fail;
4508 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
4509 return MCDisassembler::Fail;
4510
4511 if (Rm != 0xF) { // Writeback
4512 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4513 return MCDisassembler::Fail;
4514 }
4515 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4516 return MCDisassembler::Fail;
4517 Inst.addOperand(MCOperand::createImm(align));
4518 if (Rm != 0xF) {
4519 if (Rm != 0xD) {
4520 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
4521 return MCDisassembler::Fail;
4522 } else
4524 }
4525
4526 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4527 return MCDisassembler::Fail;
4528 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
4529 return MCDisassembler::Fail;
4530 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
4531 return MCDisassembler::Fail;
4532 Inst.addOperand(MCOperand::createImm(index));
4533
4534 return S;
4535}
4536
4537static DecodeStatus DecodeVST3LN(MCInst &Inst, unsigned Insn, uint64_t Address,
4538 const MCDisassembler *Decoder) {
4540
4541 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4542 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
4543 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
4544 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
4545 unsigned size = fieldFromInstruction(Insn, 10, 2);
4546
4547 unsigned align = 0;
4548 unsigned index = 0;
4549 unsigned inc = 1;
4550 switch (size) {
4551 default:
4552 return MCDisassembler::Fail;
4553 case 0:
4554 if (fieldFromInstruction(Insn, 4, 1))
4555 return MCDisassembler::Fail; // UNDEFINED
4556 index = fieldFromInstruction(Insn, 5, 3);
4557 break;
4558 case 1:
4559 if (fieldFromInstruction(Insn, 4, 1))
4560 return MCDisassembler::Fail; // UNDEFINED
4561 index = fieldFromInstruction(Insn, 6, 2);
4562 if (fieldFromInstruction(Insn, 5, 1))
4563 inc = 2;
4564 break;
4565 case 2:
4566 if (fieldFromInstruction(Insn, 4, 2))
4567 return MCDisassembler::Fail; // UNDEFINED
4568 index = fieldFromInstruction(Insn, 7, 1);
4569 if (fieldFromInstruction(Insn, 6, 1))
4570 inc = 2;
4571 break;
4572 }
4573
4574 if (Rm != 0xF) { // Writeback
4575 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4576 return MCDisassembler::Fail;
4577 }
4578 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4579 return MCDisassembler::Fail;
4580 Inst.addOperand(MCOperand::createImm(align));
4581 if (Rm != 0xF) {
4582 if (Rm != 0xD) {
4583 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
4584 return MCDisassembler::Fail;
4585 } else
4587 }
4588
4589 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4590 return MCDisassembler::Fail;
4591 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
4592 return MCDisassembler::Fail;
4593 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
4594 return MCDisassembler::Fail;
4595 Inst.addOperand(MCOperand::createImm(index));
4596
4597 return S;
4598}
4599
4600static DecodeStatus DecodeVLD4LN(MCInst &Inst, unsigned Insn, uint64_t Address,
4601 const MCDisassembler *Decoder) {
4603
4604 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4605 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
4606 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
4607 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
4608 unsigned size = fieldFromInstruction(Insn, 10, 2);
4609
4610 unsigned align = 0;
4611 unsigned index = 0;
4612 unsigned inc = 1;
4613 switch (size) {
4614 default:
4615 return MCDisassembler::Fail;
4616 case 0:
4617 if (fieldFromInstruction(Insn, 4, 1))
4618 align = 4;
4619 index = fieldFromInstruction(Insn, 5, 3);
4620 break;
4621 case 1:
4622 if (fieldFromInstruction(Insn, 4, 1))
4623 align = 8;
4624 index = fieldFromInstruction(Insn, 6, 2);
4625 if (fieldFromInstruction(Insn, 5, 1))
4626 inc = 2;
4627 break;
4628 case 2:
4629 switch (fieldFromInstruction(Insn, 4, 2)) {
4630 case 0:
4631 align = 0; break;
4632 case 3:
4633 return MCDisassembler::Fail;
4634 default:
4635 align = 4 << fieldFromInstruction(Insn, 4, 2); break;
4636 }
4637
4638 index = fieldFromInstruction(Insn, 7, 1);
4639 if (fieldFromInstruction(Insn, 6, 1))
4640 inc = 2;
4641 break;
4642 }
4643
4644 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4645 return MCDisassembler::Fail;
4646 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
4647 return MCDisassembler::Fail;
4648 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
4649 return MCDisassembler::Fail;
4650 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)))
4651 return MCDisassembler::Fail;
4652
4653 if (Rm != 0xF) { // Writeback
4654 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4655 return MCDisassembler::Fail;
4656 }
4657 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4658 return MCDisassembler::Fail;
4659 Inst.addOperand(MCOperand::createImm(align));
4660 if (Rm != 0xF) {
4661 if (Rm != 0xD) {
4662 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
4663 return MCDisassembler::Fail;
4664 } else
4666 }
4667
4668 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4669 return MCDisassembler::Fail;
4670 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
4671 return MCDisassembler::Fail;
4672 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
4673 return MCDisassembler::Fail;
4674 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)))
4675 return MCDisassembler::Fail;
4676 Inst.addOperand(MCOperand::createImm(index));
4677
4678 return S;
4679}
4680
4681static DecodeStatus DecodeVST4LN(MCInst &Inst, unsigned Insn, uint64_t Address,
4682 const MCDisassembler *Decoder) {
4684
4685 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4686 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
4687 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
4688 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
4689 unsigned size = fieldFromInstruction(Insn, 10, 2);
4690
4691 unsigned align = 0;
4692 unsigned index = 0;
4693 unsigned inc = 1;
4694 switch (size) {
4695 default:
4696 return MCDisassembler::Fail;
4697 case 0:
4698 if (fieldFromInstruction(Insn, 4, 1))
4699 align = 4;
4700 index = fieldFromInstruction(Insn, 5, 3);
4701 break;
4702 case 1:
4703 if (fieldFromInstruction(Insn, 4, 1))
4704 align = 8;
4705 index = fieldFromInstruction(Insn, 6, 2);
4706 if (fieldFromInstruction(Insn, 5, 1))
4707 inc = 2;
4708 break;
4709 case 2:
4710 switch (fieldFromInstruction(Insn, 4, 2)) {
4711 case 0:
4712 align = 0; break;
4713 case 3:
4714 return MCDisassembler::Fail;
4715 default:
4716 align = 4 << fieldFromInstruction(Insn, 4, 2); break;
4717 }
4718
4719 index = fieldFromInstruction(Insn, 7, 1);
4720 if (fieldFromInstruction(Insn, 6, 1))
4721 inc = 2;
4722 break;
4723 }
4724
4725 if (Rm != 0xF) { // Writeback
4726 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4727 return MCDisassembler::Fail;
4728 }
4729 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4730 return MCDisassembler::Fail;
4731 Inst.addOperand(MCOperand::createImm(align));
4732 if (Rm != 0xF) {
4733 if (Rm != 0xD) {
4734 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
4735 return MCDisassembler::Fail;
4736 } else
4738 }
4739
4740 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4741 return MCDisassembler::Fail;
4742 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
4743 return MCDisassembler::Fail;
4744 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
4745 return MCDisassembler::Fail;
4746 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)))
4747 return MCDisassembler::Fail;
4748 Inst.addOperand(MCOperand::createImm(index));
4749
4750 return S;
4751}
4752
4753static DecodeStatus DecodeVMOVSRR(MCInst &Inst, unsigned Insn, uint64_t Address,
4754 const MCDisassembler *Decoder) {
4756 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4757 unsigned Rt2 = fieldFromInstruction(Insn, 16, 4);
4758 unsigned Rm = fieldFromInstruction(Insn, 5, 1);
4759 unsigned pred = fieldFromInstruction(Insn, 28, 4);
4760 Rm |= fieldFromInstruction(Insn, 0, 4) << 1;
4761
4762 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F)
4764
4765 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder)))
4766 return MCDisassembler::Fail;
4767 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder)))
4768 return MCDisassembler::Fail;
4769 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder)))
4770 return MCDisassembler::Fail;
4771 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder)))
4772 return MCDisassembler::Fail;
4773 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
4774 return MCDisassembler::Fail;
4775
4776 return S;
4777}
4778
4779static DecodeStatus DecodeVMOVRRS(MCInst &Inst, unsigned Insn, uint64_t Address,
4780 const MCDisassembler *Decoder) {
4782 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4783 unsigned Rt2 = fieldFromInstruction(Insn, 16, 4);
4784 unsigned Rm = fieldFromInstruction(Insn, 5, 1);
4785 unsigned pred = fieldFromInstruction(Insn, 28, 4);
4786 Rm |= fieldFromInstruction(Insn, 0, 4) << 1;
4787
4788 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F)
4790
4791 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder)))
4792 return MCDisassembler::Fail;
4793 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder)))
4794 return MCDisassembler::Fail;
4795 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder)))
4796 return MCDisassembler::Fail;
4797 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder)))
4798 return MCDisassembler::Fail;
4799 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
4800 return MCDisassembler::Fail;
4801
4802 return S;
4803}
4804
4805static DecodeStatus DecodeIT(MCInst &Inst, unsigned Insn, uint64_t Address,
4806 const MCDisassembler *Decoder) {
4808 unsigned pred = fieldFromInstruction(Insn, 4, 4);
4809 unsigned mask = fieldFromInstruction(Insn, 0, 4);
4810
4811 if (pred == 0xF) {
4812 pred = 0xE;
4814 }
4815
4816 if (mask == 0x0)
4817 return MCDisassembler::Fail;
4818
4819 // IT masks are encoded as a sequence of replacement low-order bits
4820 // for the condition code. So if the low bit of the starting
4821 // condition code is 1, then we have to flip all the bits above the
4822 // terminating bit (which is the lowest 1 bit).
4823 if (pred & 1) {
4824 unsigned LowBit = mask & -mask;
4825 unsigned BitsAboveLowBit = 0xF & (-LowBit << 1);
4826 mask ^= BitsAboveLowBit;
4827 }
4828
4829 Inst.addOperand(MCOperand::createImm(pred));
4830 Inst.addOperand(MCOperand::createImm(mask));
4831 return S;
4832}
4833
4835 uint64_t Address,
4836 const MCDisassembler *Decoder) {
4838
4839 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4840 unsigned Rt2 = fieldFromInstruction(Insn, 8, 4);
4841 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4842 unsigned addr = fieldFromInstruction(Insn, 0, 8);
4843 unsigned W = fieldFromInstruction(Insn, 21, 1);
4844 unsigned U = fieldFromInstruction(Insn, 23, 1);
4845 unsigned P = fieldFromInstruction(Insn, 24, 1);
4846 bool writeback = (W == 1) | (P == 0);
4847
4848 addr |= (U << 8) | (Rn << 9);
4849
4850 if (writeback && (Rn == Rt || Rn == Rt2))
4852 if (Rt == Rt2)
4854
4855 // Rt
4856 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder)))
4857 return MCDisassembler::Fail;
4858 // Rt2
4859 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder)))
4860 return MCDisassembler::Fail;
4861 // Writeback operand
4862 if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder)))
4863 return MCDisassembler::Fail;
4864 // addr
4865 if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder)))
4866 return MCDisassembler::Fail;
4867
4868 return S;
4869}
4870
4872 uint64_t Address,
4873 const MCDisassembler *Decoder) {
4875
4876 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4877 unsigned Rt2 = fieldFromInstruction(Insn, 8, 4);
4878 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4879 unsigned addr = fieldFromInstruction(Insn, 0, 8);
4880 unsigned W = fieldFromInstruction(Insn, 21, 1);
4881 unsigned U = fieldFromInstruction(Insn, 23, 1);
4882 unsigned P = fieldFromInstruction(Insn, 24, 1);
4883 bool writeback = (W == 1) | (P == 0);
4884
4885 addr |= (U << 8) | (Rn << 9);
4886
4887 if (writeback && (Rn == Rt || Rn == Rt2))
4889
4890 // Writeback operand
4891 if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder)))
4892 return MCDisassembler::Fail;
4893 // Rt
4894 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder)))
4895 return MCDisassembler::Fail;
4896 // Rt2
4897 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder)))
4898 return MCDisassembler::Fail;
4899 // addr
4900 if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder)))
4901 return MCDisassembler::Fail;
4902
4903 return S;
4904}
4905
4907 const MCDisassembler *Decoder) {
4908 unsigned sign1 = fieldFromInstruction(Insn, 21, 1);
4909 unsigned sign2 = fieldFromInstruction(Insn, 23, 1);
4910 if (sign1 != sign2) return MCDisassembler::Fail;
4911 const unsigned Rd = fieldFromInstruction(Insn, 8, 4);
4912 assert(Inst.getNumOperands() == 0 && "We should receive an empty Inst");
4913 DecodeStatus S = DecoderGPRRegisterClass(Inst, Rd, Address, Decoder);
4914
4915 unsigned Val = fieldFromInstruction(Insn, 0, 8);
4916 Val |= fieldFromInstruction(Insn, 12, 3) << 8;
4917 Val |= fieldFromInstruction(Insn, 26, 1) << 11;
4918 // If sign, then it is decreasing the address.
4919 if (sign1) {
4920 // Following ARMv7 Architecture Manual, when the offset
4921 // is zero, it is decoded as a subw, not as a adr.w
4922 if (!Val) {
4923 Inst.setOpcode(ARM::t2SUBri12);
4924 Inst.addOperand(MCOperand::createReg(ARM::PC));
4925 } else
4926 Val = -Val;
4927 }
4929 return S;
4930}
4931
4933 uint64_t Address,
4934 const MCDisassembler *Decoder) {
4936
4937 // Shift of "asr #32" is not allowed in Thumb2 mode.
4938 if (Val == 0x20) S = MCDisassembler::Fail;
4940 return S;
4941}
4942
4943static DecodeStatus DecodeSwap(MCInst &Inst, unsigned Insn, uint64_t Address,
4944 const MCDisassembler *Decoder) {
4945 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4946 unsigned Rt2 = fieldFromInstruction(Insn, 0, 4);
4947 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4948 unsigned pred = fieldFromInstruction(Insn, 28, 4);
4949
4950 if (pred == 0xF)
4951 return DecodeCPSInstruction(Inst, Insn, Address, Decoder);
4952
4954
4955 if (Rt == Rn || Rn == Rt2)
4957
4958 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder)))
4959 return MCDisassembler::Fail;
4960 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder)))
4961 return MCDisassembler::Fail;
4962 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
4963 return MCDisassembler::Fail;
4964 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
4965 return MCDisassembler::Fail;
4966
4967 return S;
4968}
4969
4970static DecodeStatus DecodeVCVTD(MCInst &Inst, unsigned Insn, uint64_t Address,
4971 const MCDisassembler *Decoder) {
4972 const FeatureBitset &featureBits =
4973 Decoder->getSubtargetInfo().getFeatureBits();
4974 bool hasFullFP16 = featureBits[ARM::FeatureFullFP16];
4975
4976 unsigned Vd = (fieldFromInstruction(Insn, 12, 4) << 0);
4977 Vd |= (fieldFromInstruction(Insn, 22, 1) << 4);
4978 unsigned Vm = (fieldFromInstruction(Insn, 0, 4) << 0);
4979 Vm |= (fieldFromInstruction(Insn, 5, 1) << 4);
4980 unsigned imm = fieldFromInstruction(Insn, 16, 6);
4981 unsigned cmode = fieldFromInstruction(Insn, 8, 4);
4982 unsigned op = fieldFromInstruction(Insn, 5, 1);
4983
4985
4986 // If the top 3 bits of imm are clear, this is a VMOV (immediate)
4987 if (!(imm & 0x38)) {
4988 if (cmode == 0xF) {
4989 if (op == 1) return MCDisassembler::Fail;
4990 Inst.setOpcode(ARM::VMOVv2f32);
4991 }
4992 if (hasFullFP16) {
4993 if (cmode == 0xE) {
4994 if (op == 1) {
4995 Inst.setOpcode(ARM::VMOVv1i64);
4996 } else {
4997 Inst.setOpcode(ARM::VMOVv8i8);
4998 }
4999 }
5000 if (cmode == 0xD) {
5001 if (op == 1) {
5002 Inst.setOpcode(ARM::VMVNv2i32);
5003 } else {
5004 Inst.setOpcode(ARM::VMOVv2i32);
5005 }
5006 }
5007 if (cmode == 0xC) {
5008 if (op == 1) {
5009 Inst.setOpcode(ARM::VMVNv2i32);
5010 } else {
5011 Inst.setOpcode(ARM::VMOVv2i32);
5012 }
5013 }
5014 }
5015 return DecodeVMOVModImmInstruction(Inst, Insn, Address, Decoder);
5016 }
5017
5018 if (!(imm & 0x20)) return MCDisassembler::Fail;
5019
5020 if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder)))
5021 return MCDisassembler::Fail;
5022 if (!Check(S, DecodeDPRRegisterClass(Inst, Vm, Address, Decoder)))
5023 return MCDisassembler::Fail;
5024 Inst.addOperand(MCOperand::createImm(64 - imm));
5025
5026 return S;
5027}
5028
5029static DecodeStatus DecodeVCVTQ(MCInst &Inst, unsigned Insn, uint64_t Address,
5030 const MCDisassembler *Decoder) {
5031 const FeatureBitset &featureBits =
5032 Decoder->getSubtargetInfo().getFeatureBits();
5033 bool hasFullFP16 = featureBits[ARM::FeatureFullFP16];
5034
5035 unsigned Vd = (fieldFromInstruction(Insn, 12, 4) << 0);
5036 Vd |= (fieldFromInstruction(Insn, 22, 1) << 4);
5037 unsigned Vm = (fieldFromInstruction(Insn, 0, 4) << 0);
5038 Vm |= (fieldFromInstruction(Insn, 5, 1) << 4);
5039 unsigned imm = fieldFromInstruction(Insn, 16, 6);
5040 unsigned cmode = fieldFromInstruction(Insn, 8, 4);
5041 unsigned op = fieldFromInstruction(Insn, 5, 1);
5042
5044
5045 // If the top 3 bits of imm are clear, this is a VMOV (immediate)
5046 if (!(imm & 0x38)) {
5047 if (cmode == 0xF) {
5048 if (op == 1) return MCDisassembler::Fail;
5049 Inst.setOpcode(ARM::VMOVv4f32);
5050 }
5051 if (hasFullFP16) {
5052 if (cmode == 0xE) {
5053 if (op == 1) {
5054 Inst.setOpcode(ARM::VMOVv2i64);
5055 } else {
5056 Inst.setOpcode(ARM::VMOVv16i8);
5057 }
5058 }
5059 if (cmode == 0xD) {
5060 if (op == 1) {
5061 Inst.setOpcode(ARM::VMVNv4i32);
5062 } else {
5063 Inst.setOpcode(ARM::VMOVv4i32);
5064 }
5065 }
5066 if (cmode == 0xC) {
5067 if (op == 1) {
5068 Inst.setOpcode(ARM::VMVNv4i32);
5069 } else {
5070 Inst.setOpcode(ARM::VMOVv4i32);
5071 }
5072 }
5073 }
5074 return DecodeVMOVModImmInstruction(Inst, Insn, Address, Decoder);
5075 }
5076
5077 if (!(imm & 0x20)) return MCDisassembler::Fail;
5078
5079 if (!Check(S, DecodeQPRRegisterClass(Inst, Vd, Address, Decoder)))
5080 return MCDisassembler::Fail;
5081 if (!Check(S, DecodeQPRRegisterClass(Inst, Vm, Address, Decoder)))
5082 return MCDisassembler::Fail;
5083 Inst.addOperand(MCOperand::createImm(64 - imm));
5084
5085 return S;
5086}
5087
5088static DecodeStatus
5090 uint64_t Address,
5091 const MCDisassembler *Decoder) {
5092 unsigned Vd = (fieldFromInstruction(Insn, 12, 4) << 0);
5093 Vd |= (fieldFromInstruction(Insn, 22, 1) << 4);
5094 unsigned Vn = (fieldFromInstruction(Insn, 16, 4) << 0);
5095 Vn |= (fieldFromInstruction(Insn, 7, 1) << 4);
5096 unsigned Vm = (fieldFromInstruction(Insn, 0, 4) << 0);
5097 Vm |= (fieldFromInstruction(Insn, 5, 1) << 4);
5098 unsigned q = (fieldFromInstruction(Insn, 6, 1) << 0);
5099 unsigned rotate = (fieldFromInstruction(Insn, 20, 2) << 0);
5100
5102
5103 auto DestRegDecoder = q ? DecodeQPRRegisterClass : DecodeDPRRegisterClass;
5104
5105 if (!Check(S, DestRegDecoder(Inst, Vd, Address, Decoder)))
5106 return MCDisassembler::Fail;
5107 if (!Check(S, DestRegDecoder(Inst, Vd, Address, Decoder)))
5108 return MCDisassembler::Fail;
5109 if (!Check(S, DestRegDecoder(Inst, Vn, Address, Decoder)))
5110 return MCDisassembler::Fail;
5111 if (!Check(S, DecodeDPRRegisterClass(Inst, Vm, Address, Decoder)))
5112 return MCDisassembler::Fail;
5113 // The lane index does not have any bits in the encoding, because it can only
5114 // be 0.
5116 Inst.addOperand(MCOperand::createImm(rotate));
5117
5118 return S;
5119}
5120
5121static DecodeStatus DecodeLDR(MCInst &Inst, unsigned Val, uint64_t Address,
5122 const MCDisassembler *Decoder) {
5124
5125 unsigned Rn = fieldFromInstruction(Val, 16, 4);
5126 unsigned Rt = fieldFromInstruction(Val, 12, 4);
5127 unsigned Rm = fieldFromInstruction(Val, 0, 4);
5128 Rm |= (fieldFromInstruction(Val, 23, 1) << 4);
5129 unsigned Cond = fieldFromInstruction(Val, 28, 4);
5130
5131 if (fieldFromInstruction(Val, 8, 4) != 0 || Rn == Rt)
5133
5134 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder)))
5135 return MCDisassembler::Fail;
5136 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
5137 return MCDisassembler::Fail;
5138 if (!Check(S, DecodeAddrMode7Operand(Inst, Rn, Address, Decoder)))
5139 return MCDisassembler::Fail;
5140 if (!Check(S, DecodePostIdxReg(Inst, Rm, Address, Decoder)))
5141 return MCDisassembler::Fail;
5142 if (!Check(S, DecodePredicateOperand(Inst, Cond, Address, Decoder)))
5143 return MCDisassembler::Fail;
5144
5145 return S;
5146}
5147
5149 uint64_t Address,
5150 const MCDisassembler *Decoder) {
5152
5153 unsigned CRm = fieldFromInstruction(Val, 0, 4);
5154 unsigned opc1 = fieldFromInstruction(Val, 4, 4);
5155 unsigned cop = fieldFromInstruction(Val, 8, 4);
5156 unsigned Rt = fieldFromInstruction(Val, 12, 4);
5157 unsigned Rt2 = fieldFromInstruction(Val, 16, 4);
5158
5159 if ((cop & ~0x1) == 0xa)
5160 return MCDisassembler::Fail;
5161
5162 if (Rt == Rt2)
5164
5165 // We have to check if the instruction is MRRC2
5166 // or MCRR2 when constructing the operands for
5167 // Inst. Reason is because MRRC2 stores to two
5168 // registers so it's tablegen desc has two
5169 // outputs whereas MCRR doesn't store to any
5170 // registers so all of it's operands are listed
5171 // as inputs, therefore the operand order for
5172 // MRRC2 needs to be [Rt, Rt2, cop, opc1, CRm]
5173 // and MCRR2 operand order is [cop, opc1, Rt, Rt2, CRm]
5174
5175 if (Inst.getOpcode() == ARM::MRRC2) {
5176 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder)))
5177 return MCDisassembler::Fail;
5178 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder)))
5179 return MCDisassembler::Fail;
5180 }
5182 Inst.addOperand(MCOperand::createImm(opc1));
5183 if (Inst.getOpcode() == ARM::MCRR2) {
5184 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder)))
5185 return MCDisassembler::Fail;
5186 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder)))
5187 return MCDisassembler::Fail;
5188 }
5190
5191 return S;
5192}
5193
5194static DecodeStatus DecodeForVMRSandVMSR(MCInst &Inst, unsigned Val,
5195 uint64_t Address,
5196 const MCDisassembler *Decoder) {
5197 const FeatureBitset &featureBits =
5198 Decoder->getSubtargetInfo().getFeatureBits();
5200
5201 // Add explicit operand for the destination sysreg, for cases where
5202 // we have to model it for code generation purposes.
5203 switch (Inst.getOpcode()) {
5204 case ARM::VMSR_FPSCR_NZCVQC:
5205 Inst.addOperand(MCOperand::createReg(ARM::FPSCR_NZCV));
5206 break;
5207 case ARM::VMSR_P0:
5208 Inst.addOperand(MCOperand::createReg(ARM::VPR));
5209 break;
5210 }
5211
5212 if (Inst.getOpcode() != ARM::FMSTAT) {
5213 unsigned Rt = fieldFromInstruction(Val, 12, 4);
5214
5215 if (featureBits[ARM::ModeThumb] && !featureBits[ARM::HasV8Ops]) {
5216 if (Rt == 13 || Rt == 15)
5218 Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder));
5219 } else
5220 Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder));
5221 }
5222
5223 // Add explicit operand for the source sysreg, similarly to above.
5224 switch (Inst.getOpcode()) {
5225 case ARM::VMRS_FPSCR_NZCVQC:
5226 Inst.addOperand(MCOperand::createReg(ARM::FPSCR_NZCV));
5227 break;
5228 case ARM::VMRS_P0:
5229 Inst.addOperand(MCOperand::createReg(ARM::VPR));
5230 break;
5231 }
5232
5233 if (featureBits[ARM::ModeThumb]) {
5236 } else {
5237 unsigned pred = fieldFromInstruction(Val, 28, 4);
5238 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
5239 return MCDisassembler::Fail;
5240 }
5241
5242 return S;
5243}
5244
5245template <bool isSigned, bool isNeg, bool zeroPermitted, int size>
5246static DecodeStatus DecodeBFLabelOperand(MCInst &Inst, unsigned Val,
5247 uint64_t Address,
5248 const MCDisassembler *Decoder) {
5250 if (Val == 0 && !zeroPermitted)
5252
5253 uint64_t DecVal;
5254 if (isSigned)
5255 DecVal = SignExtend32<size + 1>(Val << 1);
5256 else
5257 DecVal = (Val << 1);
5258
5259 if (!tryAddingSymbolicOperand(Address, Address + DecVal + 4, true, 4, Inst,
5260 Decoder))
5261 Inst.addOperand(MCOperand::createImm(isNeg ? -DecVal : DecVal));
5262 return S;
5263}
5264
5266 uint64_t Address,
5267 const MCDisassembler *Decoder) {
5268
5269 uint64_t LocImm = Inst.getOperand(0).getImm();
5270 Val = LocImm + (2 << Val);
5271 if (!tryAddingSymbolicOperand(Address, Address + Val + 4, true, 4, Inst,
5272 Decoder))
5275}
5276
5277static DecodeStatus DecodePredNoALOperand(MCInst &Inst, unsigned Val,
5278 uint64_t Address,
5279 const MCDisassembler *Decoder) {
5280 if (Val >= ARMCC::AL) // also exclude the non-condition NV
5281 return MCDisassembler::Fail;
5284}
5285
5286static DecodeStatus DecodeLOLoop(MCInst &Inst, unsigned Insn, uint64_t Address,
5287 const MCDisassembler *Decoder) {
5289
5290 if (Inst.getOpcode() == ARM::MVE_LCTP)
5291 return S;
5292
5293 unsigned Imm = fieldFromInstruction(Insn, 11, 1) |
5294 fieldFromInstruction(Insn, 1, 10) << 1;
5295 switch (Inst.getOpcode()) {
5296 case ARM::t2LEUpdate:
5297 case ARM::MVE_LETP:
5298 Inst.addOperand(MCOperand::createReg(ARM::LR));
5299 Inst.addOperand(MCOperand::createReg(ARM::LR));
5300 [[fallthrough]];
5301 case ARM::t2LE:
5303 Inst, Imm, Address, Decoder)))
5304 return MCDisassembler::Fail;
5305 break;
5306 case ARM::t2WLS:
5307 case ARM::MVE_WLSTP_8:
5308 case ARM::MVE_WLSTP_16:
5309 case ARM::MVE_WLSTP_32:
5310 case ARM::MVE_WLSTP_64:
5311 Inst.addOperand(MCOperand::createReg(ARM::LR));
5312 if (!Check(S,
5314 Address, Decoder)) ||
5316 Inst, Imm, Address, Decoder)))
5317 return MCDisassembler::Fail;
5318 break;
5319 case ARM::t2DLS:
5320 case ARM::MVE_DLSTP_8:
5321 case ARM::MVE_DLSTP_16:
5322 case ARM::MVE_DLSTP_32:
5323 case ARM::MVE_DLSTP_64:
5324 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
5325 if (Rn == 0xF) {
5326 // Enforce all the rest of the instruction bits in LCTP, which
5327 // won't have been reliably checked based on LCTP's own tablegen
5328 // record, because we came to this decode by a roundabout route.
5329 uint32_t CanonicalLCTP = 0xF00FE001, SBZMask = 0x00300FFE;
5330 if ((Insn & ~SBZMask) != CanonicalLCTP)
5331 return MCDisassembler::Fail; // a mandatory bit is wrong: hard fail
5332 if (Insn != CanonicalLCTP)
5333 Check(S, MCDisassembler::SoftFail); // an SBZ bit is wrong: soft fail
5334
5335 Inst.setOpcode(ARM::MVE_LCTP);
5336 } else {
5337 Inst.addOperand(MCOperand::createReg(ARM::LR));
5338 if (!Check(S, DecoderGPRRegisterClass(Inst,
5339 fieldFromInstruction(Insn, 16, 4),
5340 Address, Decoder)))
5341 return MCDisassembler::Fail;
5342 }
5343 break;
5344 }
5345 return S;
5346}
5347
5348static DecodeStatus DecodeLongShiftOperand(MCInst &Inst, unsigned Val,
5349 uint64_t Address,
5350 const MCDisassembler *Decoder) {
5352
5353 if (Val == 0)
5354 Val = 32;
5355
5357
5358 return S;
5359}
5360
5362 uint64_t Address,
5363 const MCDisassembler *Decoder) {
5364 if ((RegNo) + 1 > 11)
5365 return MCDisassembler::Fail;
5366
5367 unsigned Register = GPRDecoderTable[(RegNo) + 1];
5370}
5371
5373 uint64_t Address,
5374 const MCDisassembler *Decoder) {
5375 if ((RegNo) > 14)
5376 return MCDisassembler::Fail;
5377
5378 unsigned Register = GPRDecoderTable[(RegNo)];
5381}
5382
5383static DecodeStatus
5385 uint64_t Address,
5386 const MCDisassembler *Decoder) {
5387 if (RegNo == 15) {
5388 Inst.addOperand(MCOperand::createReg(ARM::APSR_NZCV));
5390 }
5391
5392 unsigned Register = GPRDecoderTable[RegNo];
5394
5395 if (RegNo == 13)
5397
5399}
5400
5401static DecodeStatus DecodeVSCCLRM(MCInst &Inst, unsigned Insn, uint64_t Address,
5402 const MCDisassembler *Decoder) {
5404
5407 unsigned regs = fieldFromInstruction(Insn, 0, 8);
5408 if (regs == 0) {
5409 // Register list contains only VPR
5410 } else if (Inst.getOpcode() == ARM::VSCCLRMD) {
5411 unsigned reglist = regs | (fieldFromInstruction(Insn, 12, 4) << 8) |
5412 (fieldFromInstruction(Insn, 22, 1) << 12);
5413 if (!Check(S, DecodeDPRRegListOperand(Inst, reglist, Address, Decoder))) {
5414 return MCDisassembler::Fail;
5415 }
5416 } else {
5417 unsigned Vd = (fieldFromInstruction(Insn, 12, 4) << 1) |
5418 fieldFromInstruction(Insn, 22, 1);
5419 // Registers past s31 are permitted and treated as being half of a d
5420 // register, though both halves of each d register must be present.
5421 unsigned max_reg = Vd + regs;
5422 if (max_reg > 64 || (max_reg > 32 && (max_reg & 1)))
5424 unsigned max_sreg = std::min(32u, max_reg);
5425 unsigned max_dreg = std::min(32u, max_reg / 2);
5426 for (unsigned i = Vd; i < max_sreg; ++i)
5427 if (!Check(S, DecodeSPRRegisterClass(Inst, i, Address, Decoder)))
5428 return MCDisassembler::Fail;
5429 for (unsigned i = 16; i < max_dreg; ++i)
5430 if (!Check(S, DecodeDPRRegisterClass(Inst, i, Address, Decoder)))
5431 return MCDisassembler::Fail;
5432 }
5433 Inst.addOperand(MCOperand::createReg(ARM::VPR));
5434
5435 return S;
5436}
5437
5438static DecodeStatus DecodeVPTMaskOperand(MCInst &Inst, unsigned Val,
5439 uint64_t Address,
5440 const MCDisassembler *Decoder) {
5442
5443 // Parse VPT mask and encode it in the MCInst as an immediate with the same
5444 // format as the it_mask. That is, from the second 'e|t' encode 'e' as 1 and
5445 // 't' as 0 and finish with a 1.
5446 unsigned Imm = 0;
5447 // We always start with a 't'.
5448 unsigned CurBit = 0;
5449 for (int i = 3; i >= 0; --i) {
5450 // If the bit we are looking at is not the same as last one, invert the
5451 // CurBit, if it is the same leave it as is.
5452 CurBit ^= (Val >> i) & 1U;
5453
5454 // Encode the CurBit at the right place in the immediate.
5455 Imm |= (CurBit << i);
5456
5457 // If we are done, finish the encoding with a 1.
5458 if ((Val & ~(~0U << i)) == 0) {
5459 Imm |= 1U << i;
5460 break;
5461 }
5462 }
5463
5465
5466 return S;
5467}
5468
5469static DecodeStatus DecodeVpredROperand(MCInst &Inst, unsigned RegNo,
5470 uint64_t Address,
5471 const MCDisassembler *Decoder) {
5472 // The vpred_r operand type includes an MQPR register field derived
5473 // from the encoding. But we don't actually want to add an operand
5474 // to the MCInst at this stage, because AddThumbPredicate will do it
5475 // later, and will infer the register number from the TIED_TO
5476 // constraint. So this is a deliberately empty decoder method that
5477 // will inhibit the auto-generated disassembly code from adding an
5478 // operand at all.
5480}
5481
5482[[maybe_unused]] static DecodeStatus
5483DecodeVpredNOperand(MCInst &Inst, unsigned RegNo, uint64_t Address,
5484 const MCDisassembler *Decoder) {
5485 // Similar to above, we want to ensure that no operands are added for the
5486 // vpred operands. (This is marked "maybe_unused" for the moment; because
5487 // DecoderEmitter currently (wrongly) omits operands with no instruction bits,
5488 // the decoder doesn't actually call it yet. That will be addressed in a
5489 // future change.)
5491}
5492
5493static DecodeStatus
5495 const MCDisassembler *Decoder) {
5496 Inst.addOperand(MCOperand::createImm((Val & 0x1) == 0 ? ARMCC::EQ : ARMCC::NE));
5498}
5499
5500static DecodeStatus
5502 const MCDisassembler *Decoder) {
5503 unsigned Code;
5504 switch (Val & 0x3) {
5505 case 0:
5506 Code = ARMCC::GE;
5507 break;
5508 case 1:
5509 Code = ARMCC::LT;
5510 break;
5511 case 2:
5512 Code = ARMCC::GT;
5513 break;
5514 case 3:
5515 Code = ARMCC::LE;
5516 break;
5517 }
5518 Inst.addOperand(MCOperand::createImm(Code));
5520}
5521
5522static DecodeStatus
5524 const MCDisassembler *Decoder) {
5525 Inst.addOperand(MCOperand::createImm((Val & 0x1) == 0 ? ARMCC::HS : ARMCC::HI));
5527}
5528
5529static DecodeStatus
5531 const MCDisassembler *Decoder) {
5532 unsigned Code;
5533 switch (Val) {
5534 default:
5535 return MCDisassembler::Fail;
5536 case 0:
5537 Code = ARMCC::EQ;
5538 break;
5539 case 1:
5540 Code = ARMCC::NE;
5541 break;
5542 case 4:
5543 Code = ARMCC::GE;
5544 break;
5545 case 5:
5546 Code = ARMCC::LT;
5547 break;
5548 case 6:
5549 Code = ARMCC::GT;
5550 break;
5551 case 7:
5552 Code = ARMCC::LE;
5553 break;
5554 }
5555
5556 Inst.addOperand(MCOperand::createImm(Code));
5558}
5559
5560static DecodeStatus DecodeVCVTImmOperand(MCInst &Inst, unsigned Val,
5561 uint64_t Address,
5562 const MCDisassembler *Decoder) {
5564
5565 unsigned DecodedVal = 64 - Val;
5566
5567 switch (Inst.getOpcode()) {
5568 case ARM::MVE_VCVTf16s16_fix:
5569 case ARM::MVE_VCVTs16f16_fix:
5570 case ARM::MVE_VCVTf16u16_fix:
5571 case ARM::MVE_VCVTu16f16_fix:
5572 if (DecodedVal > 16)
5573 return MCDisassembler::Fail;
5574 break;
5575 case ARM::MVE_VCVTf32s32_fix:
5576 case ARM::MVE_VCVTs32f32_fix:
5577 case ARM::MVE_VCVTf32u32_fix:
5578 case ARM::MVE_VCVTu32f32_fix:
5579 if (DecodedVal > 32)
5580 return MCDisassembler::Fail;
5581 break;
5582 }
5583
5584 Inst.addOperand(MCOperand::createImm(64 - Val));
5585
5586 return S;
5587}
5588
5589static unsigned FixedRegForVSTRVLDR_SYSREG(unsigned Opcode) {
5590 switch (Opcode) {
5591 case ARM::VSTR_P0_off:
5592 case ARM::VSTR_P0_pre:
5593 case ARM::VSTR_P0_post:
5594 case ARM::VLDR_P0_off:
5595 case ARM::VLDR_P0_pre:
5596 case ARM::VLDR_P0_post:
5597 return ARM::P0;
5598 case ARM::VSTR_FPSCR_NZCVQC_off:
5599 case ARM::VSTR_FPSCR_NZCVQC_pre:
5600 case ARM::VSTR_FPSCR_NZCVQC_post:
5601 case ARM::VLDR_FPSCR_NZCVQC_off:
5602 case ARM::VLDR_FPSCR_NZCVQC_pre:
5603 case ARM::VLDR_FPSCR_NZCVQC_post:
5604 return ARM::FPSCR;
5605 default:
5606 return 0;
5607 }
5608}
5609
5610template <bool Writeback>
5611static DecodeStatus DecodeVSTRVLDR_SYSREG(MCInst &Inst, unsigned Val,
5612 uint64_t Address,
5613 const MCDisassembler *Decoder) {
5614 switch (Inst.getOpcode()) {
5615 case ARM::VSTR_FPSCR_pre:
5616 case ARM::VSTR_FPSCR_NZCVQC_pre:
5617 case ARM::VLDR_FPSCR_pre:
5618 case ARM::VLDR_FPSCR_NZCVQC_pre:
5619 case ARM::VSTR_FPSCR_off:
5620 case ARM::VSTR_FPSCR_NZCVQC_off:
5621 case ARM::VLDR_FPSCR_off:
5622 case ARM::VLDR_FPSCR_NZCVQC_off:
5623 case ARM::VSTR_FPSCR_post:
5624 case ARM::VSTR_FPSCR_NZCVQC_post:
5625 case ARM::VLDR_FPSCR_post:
5626 case ARM::VLDR_FPSCR_NZCVQC_post:
5627 const FeatureBitset &featureBits =
5628 Decoder->getSubtargetInfo().getFeatureBits();
5629
5630 if (!featureBits[ARM::HasMVEIntegerOps] && !featureBits[ARM::FeatureVFP2])
5631 return MCDisassembler::Fail;
5632 }
5633
5635 if (unsigned Sysreg = FixedRegForVSTRVLDR_SYSREG(Inst.getOpcode()))
5636 Inst.addOperand(MCOperand::createReg(Sysreg));
5637 unsigned Rn = fieldFromInstruction(Val, 16, 4);
5638 unsigned addr = fieldFromInstruction(Val, 0, 7) |
5639 (fieldFromInstruction(Val, 23, 1) << 7) | (Rn << 8);
5640
5641 if (Writeback) {
5642 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
5643 return MCDisassembler::Fail;
5644 }
5645 if (!Check(S, DecodeT2AddrModeImm7s4(Inst, addr, Address, Decoder)))
5646 return MCDisassembler::Fail;
5647
5650
5651 return S;
5652}
5653
5654static inline DecodeStatus
5655DecodeMVE_MEM_pre(MCInst &Inst, unsigned Val, uint64_t Address,
5656 const MCDisassembler *Decoder, unsigned Rn,
5657 OperandDecoder RnDecoder, OperandDecoder AddrDecoder) {
5659
5660 unsigned Qd = fieldFromInstruction(Val, 13, 3);
5661 unsigned addr = fieldFromInstruction(Val, 0, 7) |
5662 (fieldFromInstruction(Val, 23, 1) << 7) | (Rn << 8);
5663
5664 if (!Check(S, RnDecoder(Inst, Rn, Address, Decoder)))
5665 return MCDisassembler::Fail;
5666 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qd, Address, Decoder)))
5667 return MCDisassembler::Fail;
5668 if (!Check(S, AddrDecoder(Inst, addr, Address, Decoder)))
5669 return MCDisassembler::Fail;
5670
5671 return S;
5672}
5673
5674template <int shift>
5675static DecodeStatus DecodeMVE_MEM_1_pre(MCInst &Inst, unsigned Val,
5676 uint64_t Address,
5677 const MCDisassembler *Decoder) {
5678 return DecodeMVE_MEM_pre(Inst, Val, Address, Decoder,
5679 fieldFromInstruction(Val, 16, 3),
5682}
5683
5684template <int shift>
5685static DecodeStatus DecodeMVE_MEM_2_pre(MCInst &Inst, unsigned Val,
5686 uint64_t Address,
5687 const MCDisassembler *Decoder) {
5688 return DecodeMVE_MEM_pre(Inst, Val, Address, Decoder,
5689 fieldFromInstruction(Val, 16, 4),
5692}
5693
5694template <int shift>
5695static DecodeStatus DecodeMVE_MEM_3_pre(MCInst &Inst, unsigned Val,
5696 uint64_t Address,
5697 const MCDisassembler *Decoder) {
5698 return DecodeMVE_MEM_pre(Inst, Val, Address, Decoder,
5699 fieldFromInstruction(Val, 17, 3),
5702}
5703
5704template <unsigned MinLog, unsigned MaxLog>
5705static DecodeStatus DecodePowerTwoOperand(MCInst &Inst, unsigned Val,
5706 uint64_t Address,
5707 const MCDisassembler *Decoder) {
5709
5710 if (Val < MinLog || Val > MaxLog)
5711 return MCDisassembler::Fail;
5712
5713 Inst.addOperand(MCOperand::createImm(1LL << Val));
5714 return S;
5715}
5716
5717template <unsigned start>
5718static DecodeStatus
5720 const MCDisassembler *Decoder) {
5722
5723 Inst.addOperand(MCOperand::createImm(start + Val));
5724
5725 return S;
5726}
5727
5728static DecodeStatus DecodeMVEVMOVQtoDReg(MCInst &Inst, unsigned Insn,
5729 uint64_t Address,
5730 const MCDisassembler *Decoder) {
5732 unsigned Rt = fieldFromInstruction(Insn, 0, 4);
5733 unsigned Rt2 = fieldFromInstruction(Insn, 16, 4);
5734 unsigned Qd = ((fieldFromInstruction(Insn, 22, 1) << 3) |
5735 fieldFromInstruction(Insn, 13, 3));
5736 unsigned index = fieldFromInstruction(Insn, 4, 1);
5737
5738 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
5739 return MCDisassembler::Fail;
5740 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2, Address, Decoder)))
5741 return MCDisassembler::Fail;
5742 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qd, Address, Decoder)))
5743 return MCDisassembler::Fail;
5744 if (!Check(S, DecodeMVEPairVectorIndexOperand<2>(Inst, index, Address, Decoder)))
5745 return MCDisassembler::Fail;
5746 if (!Check(S, DecodeMVEPairVectorIndexOperand<0>(Inst, index, Address, Decoder)))
5747 return MCDisassembler::Fail;
5748
5749 return S;
5750}
5751
5752static DecodeStatus DecodeMVEVMOVDRegtoQ(MCInst &Inst, unsigned Insn,
5753 uint64_t Address,
5754 const MCDisassembler *Decoder) {
5756 unsigned Rt = fieldFromInstruction(Insn, 0, 4);
5757 unsigned Rt2 = fieldFromInstruction(Insn, 16, 4);
5758 unsigned Qd = ((fieldFromInstruction(Insn, 22, 1) << 3) |
5759 fieldFromInstruction(Insn, 13, 3));
5760 unsigned index = fieldFromInstruction(Insn, 4, 1);
5761
5762 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qd, Address, Decoder)))
5763 return MCDisassembler::Fail;
5764 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qd, Address, Decoder)))
5765 return MCDisassembler::Fail;
5766 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
5767 return MCDisassembler::Fail;
5768 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2, Address, Decoder)))
5769 return MCDisassembler::Fail;
5770 if (!Check(S, DecodeMVEPairVectorIndexOperand<2>(Inst, index, Address, Decoder)))
5771 return MCDisassembler::Fail;
5772 if (!Check(S, DecodeMVEPairVectorIndexOperand<0>(Inst, index, Address, Decoder)))
5773 return MCDisassembler::Fail;
5774
5775 return S;
5776}
5777
5778static DecodeStatus
5779DecodeMVEOverlappingLongShift(MCInst &Inst, unsigned Insn, uint64_t Address,
5780 const MCDisassembler *Decoder) {
5782
5783 unsigned RdaLo = fieldFromInstruction(Insn, 17, 3) << 1;
5784 unsigned RdaHi = fieldFromInstruction(Insn, 9, 3) << 1;
5785 unsigned Rm = fieldFromInstruction(Insn, 12, 4);
5786
5787 if (RdaHi == 14) {
5788 // This value of RdaHi (really indicating pc, because RdaHi has to
5789 // be an odd-numbered register, so the low bit will be set by the
5790 // decode function below) indicates that we must decode as SQRSHR
5791 // or UQRSHL, which both have a single Rda register field with all
5792 // four bits.
5793 unsigned Rda = fieldFromInstruction(Insn, 16, 4);
5794
5795 switch (Inst.getOpcode()) {
5796 case ARM::MVE_ASRLr:
5797 case ARM::MVE_SQRSHRL:
5798 Inst.setOpcode(ARM::MVE_SQRSHR);
5799 break;
5800 case ARM::MVE_LSLLr:
5801 case ARM::MVE_UQRSHLL:
5802 Inst.setOpcode(ARM::MVE_UQRSHL);
5803 break;
5804 default:
5805 llvm_unreachable("Unexpected starting opcode!");
5806 }
5807
5808 // Rda as output parameter
5809 if (!Check(S, DecoderGPRRegisterClass(Inst, Rda, Address, Decoder)))
5810 return MCDisassembler::Fail;
5811
5812 // Rda again as input parameter
5813 if (!Check(S, DecoderGPRRegisterClass(Inst, Rda, Address, Decoder)))
5814 return MCDisassembler::Fail;
5815
5816 // Rm, the amount to shift by
5817 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder)))
5818 return MCDisassembler::Fail;
5819
5820 if (fieldFromInstruction (Insn, 6, 3) != 4)
5822
5823 if (Rda == Rm)
5825
5826 return S;
5827 }
5828
5829 // Otherwise, we decode as whichever opcode our caller has already
5830 // put into Inst. Those all look the same:
5831
5832 // RdaLo,RdaHi as output parameters
5833 if (!Check(S, DecodetGPREvenRegisterClass(Inst, RdaLo, Address, Decoder)))
5834 return MCDisassembler::Fail;
5835 if (!Check(S, DecodetGPROddRegisterClass(Inst, RdaHi, Address, Decoder)))
5836 return MCDisassembler::Fail;
5837
5838 // RdaLo,RdaHi again as input parameters
5839 if (!Check(S, DecodetGPREvenRegisterClass(Inst, RdaLo, Address, Decoder)))
5840 return MCDisassembler::Fail;
5841 if (!Check(S, DecodetGPROddRegisterClass(Inst, RdaHi, Address, Decoder)))
5842 return MCDisassembler::Fail;
5843
5844 // Rm, the amount to shift by
5845 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder)))
5846 return MCDisassembler::Fail;
5847
5848 if (Inst.getOpcode() == ARM::MVE_SQRSHRL ||
5849 Inst.getOpcode() == ARM::MVE_UQRSHLL) {
5850 unsigned Saturate = fieldFromInstruction(Insn, 7, 1);
5851 // Saturate, the bit position for saturation
5852 Inst.addOperand(MCOperand::createImm(Saturate));
5853 }
5854
5855 return S;
5856}
5857
5858static DecodeStatus DecodeMVEVCVTt1fp(MCInst &Inst, unsigned Insn,
5859 uint64_t Address,
5860 const MCDisassembler *Decoder) {
5862 unsigned Qd = ((fieldFromInstruction(Insn, 22, 1) << 3) |
5863 fieldFromInstruction(Insn, 13, 3));
5864 unsigned Qm = ((fieldFromInstruction(Insn, 5, 1) << 3) |
5865 fieldFromInstruction(Insn, 1, 3));
5866 unsigned imm6 = fieldFromInstruction(Insn, 16, 6);
5867
5868 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qd, Address, Decoder)))
5869 return MCDisassembler::Fail;
5870 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qm, Address, Decoder)))
5871 return MCDisassembler::Fail;
5872 if (!Check(S, DecodeVCVTImmOperand(Inst, imm6, Address, Decoder)))
5873 return MCDisassembler::Fail;
5874
5875 return S;
5876}
5877
5878template <bool scalar, OperandDecoder predicate_decoder>
5879static DecodeStatus DecodeMVEVCMP(MCInst &Inst, unsigned Insn, uint64_t Address,
5880 const MCDisassembler *Decoder) {
5882 Inst.addOperand(MCOperand::createReg(ARM::VPR));
5883 unsigned Qn = fieldFromInstruction(Insn, 17, 3);
5884 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qn, Address, Decoder)))
5885 return MCDisassembler::Fail;
5886
5887 unsigned fc;
5888
5889 if (scalar) {
5890 fc = fieldFromInstruction(Insn, 12, 1) << 2 |
5891 fieldFromInstruction(Insn, 7, 1) |
5892 fieldFromInstruction(Insn, 5, 1) << 1;
5893 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
5894 if (!Check(S, DecodeGPRwithZRRegisterClass(Inst, Rm, Address, Decoder)))
5895 return MCDisassembler::Fail;
5896 } else {
5897 fc = fieldFromInstruction(Insn, 12, 1) << 2 |
5898 fieldFromInstruction(Insn, 7, 1) |
5899 fieldFromInstruction(Insn, 0, 1) << 1;
5900 unsigned Qm = fieldFromInstruction(Insn, 5, 1) << 4 |
5901 fieldFromInstruction(Insn, 1, 3);
5902 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qm, Address, Decoder)))
5903 return MCDisassembler::Fail;
5904 }
5905
5906 if (!Check(S, predicate_decoder(Inst, fc, Address, Decoder)))
5907 return MCDisassembler::Fail;
5908
5909 return S;
5910}
5911
5912static DecodeStatus DecodeMveVCTP(MCInst &Inst, unsigned Insn, uint64_t Address,
5913 const MCDisassembler *Decoder) {
5915 Inst.addOperand(MCOperand::createReg(ARM::VPR));
5916 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
5917 if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder)))
5918 return MCDisassembler::Fail;
5919 return S;
5920}
5921
5922static DecodeStatus DecodeMVEVPNOT(MCInst &Inst, unsigned Insn,
5923 uint64_t Address,
5924 const MCDisassembler *Decoder) {
5926 Inst.addOperand(MCOperand::createReg(ARM::VPR));
5927 Inst.addOperand(MCOperand::createReg(ARM::VPR));
5928 return S;
5929}
5930
5931static DecodeStatus DecodeT2AddSubSPImm(MCInst &Inst, unsigned Insn,
5932 uint64_t Address,
5933 const MCDisassembler *Decoder) {
5934 const unsigned Rd = fieldFromInstruction(Insn, 8, 4);
5935 const unsigned Rn = fieldFromInstruction(Insn, 16, 4);
5936 const unsigned Imm12 = fieldFromInstruction(Insn, 26, 1) << 11 |
5937 fieldFromInstruction(Insn, 12, 3) << 8 |
5938 fieldFromInstruction(Insn, 0, 8);
5939 const unsigned TypeT3 = fieldFromInstruction(Insn, 25, 1);
5940 unsigned sign1 = fieldFromInstruction(Insn, 21, 1);
5941 unsigned sign2 = fieldFromInstruction(Insn, 23, 1);
5942 unsigned S = fieldFromInstruction(Insn, 20, 1);
5943 if (sign1 != sign2)
5944 return MCDisassembler::Fail;
5945
5946 // T3 does a zext of imm12, where T2 does a ThumbExpandImm (T2SOImm)
5948 if ((!Check(DS,
5949 DecodeGPRspRegisterClass(Inst, Rd, Address, Decoder))) || // dst
5950 (!Check(DS, DecodeGPRspRegisterClass(Inst, Rn, Address, Decoder))))
5951 return MCDisassembler::Fail;
5952 if (TypeT3) {
5953 Inst.setOpcode(sign1 ? ARM::t2SUBspImm12 : ARM::t2ADDspImm12);
5954 Inst.addOperand(MCOperand::createImm(Imm12)); // zext imm12
5955 } else {
5956 Inst.setOpcode(sign1 ? ARM::t2SUBspImm : ARM::t2ADDspImm);
5957 if (!Check(DS, DecodeT2SOImm(Inst, Imm12, Address, Decoder))) // imm12
5958 return MCDisassembler::Fail;
5959 if (!Check(DS, DecodeCCOutOperand(Inst, S, Address, Decoder))) // cc_out
5960 return MCDisassembler::Fail;
5961 }
5962
5963 return DS;
5964}
5965
5966static DecodeStatus DecodeLazyLoadStoreMul(MCInst &Inst, unsigned Insn,
5967 uint64_t Address,
5968 const MCDisassembler *Decoder) {
5970
5971 const unsigned Rn = fieldFromInstruction(Insn, 16, 4);
5972 // Adding Rn, holding memory location to save/load to/from, the only argument
5973 // that is being encoded.
5974 // '$Rn' in the assembly.
5975 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
5976 return MCDisassembler::Fail;
5977 // An optional predicate, '$p' in the assembly.
5978 DecodePredicateOperand(Inst, ARMCC::AL, Address, Decoder);
5979 // An immediate that represents a floating point registers list. '$regs' in
5980 // the assembly.
5981 Inst.addOperand(MCOperand::createImm(0)); // Arbitrary value, has no effect.
5982
5983 return S;
5984}
5985
5986#include "ARMGenDisassemblerTables.inc"
5987
5988// Post-decoding checks
5990 uint64_t Address, raw_ostream &CS,
5991 uint32_t Insn,
5992 DecodeStatus Result) {
5993 switch (MI.getOpcode()) {
5994 case ARM::HVC: {
5995 // HVC is undefined if condition = 0xf otherwise upredictable
5996 // if condition != 0xe
5997 uint32_t Cond = (Insn >> 28) & 0xF;
5998 if (Cond == 0xF)
5999 return MCDisassembler::Fail;
6000 if (Cond != 0xE)
6002 return Result;
6003 }
6004 case ARM::t2ADDri:
6005 case ARM::t2ADDri12:
6006 case ARM::t2ADDrr:
6007 case ARM::t2ADDrs:
6008 case ARM::t2SUBri:
6009 case ARM::t2SUBri12:
6010 case ARM::t2SUBrr:
6011 case ARM::t2SUBrs:
6012 if (MI.getOperand(0).getReg() == ARM::SP &&
6013 MI.getOperand(1).getReg() != ARM::SP)
6015 return Result;
6016 default: return Result;
6017 }
6018}
6019
6020uint64_t ARMDisassembler::suggestBytesToSkip(ArrayRef<uint8_t> Bytes,
6021 uint64_t Address) const {
6022 // In Arm state, instructions are always 4 bytes wide, so there's no
6023 // point in skipping any smaller number of bytes if an instruction
6024 // can't be decoded.
6025 if (!STI.hasFeature(ARM::ModeThumb))
6026 return 4;
6027
6028 // In a Thumb instruction stream, a halfword is a standalone 2-byte
6029 // instruction if and only if its value is less than 0xE800.
6030 // Otherwise, it's the first halfword of a 4-byte instruction.
6031 //
6032 // So, if we can see the upcoming halfword, we can judge on that
6033 // basis, and maybe skip a whole 4-byte instruction that we don't
6034 // know how to decode, without accidentally trying to interpret its
6035 // second half as something else.
6036 //
6037 // If we don't have the instruction data available, we just have to
6038 // recommend skipping the minimum sensible distance, which is 2
6039 // bytes.
6040 if (Bytes.size() < 2)
6041 return 2;
6042
6043 uint16_t Insn16 = llvm::support::endian::read<uint16_t>(
6044 Bytes.data(), InstructionEndianness);
6045 return Insn16 < 0xE800 ? 2 : 4;
6046}
6047
6048DecodeStatus ARMDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
6049 ArrayRef<uint8_t> Bytes,
6050 uint64_t Address,
6051 raw_ostream &CS) const {
6052 DecodeStatus S;
6053 if (STI.hasFeature(ARM::ModeThumb))
6054 S = getThumbInstruction(MI, Size, Bytes, Address, CS);
6055 else
6056 S = getARMInstruction(MI, Size, Bytes, Address, CS);
6057 if (S == DecodeStatus::Fail)
6058 return S;
6059
6060 // Verify that the decoded instruction has the correct number of operands.
6061 const MCInstrDesc &MCID = MCII->get(MI.getOpcode());
6062 if (!MCID.isVariadic() && MI.getNumOperands() != MCID.getNumOperands()) {
6063 reportFatalInternalError(MCII->getName(MI.getOpcode()) + ": expected " +
6064 Twine(MCID.getNumOperands()) + " operands, got " +
6065 Twine(MI.getNumOperands()) + "\n");
6066 }
6067
6068 return S;
6069}
6070
6071DecodeStatus ARMDisassembler::getARMInstruction(MCInst &MI, uint64_t &Size,
6072 ArrayRef<uint8_t> Bytes,
6073 uint64_t Address,
6074 raw_ostream &CS) const {
6075 CommentStream = &CS;
6076
6077 assert(!STI.hasFeature(ARM::ModeThumb) &&
6078 "Asked to disassemble an ARM instruction but Subtarget is in Thumb "
6079 "mode!");
6080
6081 // We want to read exactly 4 bytes of data.
6082 if (Bytes.size() < 4) {
6083 Size = 0;
6084 return MCDisassembler::Fail;
6085 }
6086
6087 // Encoded as a 32-bit word in the stream.
6088 uint32_t Insn = llvm::support::endian::read<uint32_t>(Bytes.data(),
6089 InstructionEndianness);
6090
6091 // Calling the auto-generated decoder function.
6093 decodeInstruction(DecoderTableARM32, MI, Insn, Address, this, STI);
6094 if (Result != MCDisassembler::Fail) {
6095 Size = 4;
6096 return checkDecodedInstruction(MI, Size, Address, CS, Insn, Result);
6097 }
6098
6099 struct DecodeTable {
6100 const uint8_t *P;
6101 bool DecodePred;
6102 };
6103
6104 const DecodeTable Tables[] = {
6105 {DecoderTableVFP32, false}, {DecoderTableVFPV832, false},
6106 {DecoderTableNEONData32, true}, {DecoderTableNEONLoadStore32, true},
6107 {DecoderTableNEONDup32, false}, {DecoderTablev8NEON32, false},
6108 {DecoderTablev8Crypto32, false},
6109 };
6110
6111 for (auto Table : Tables) {
6112 Result = decodeInstruction(Table.P, MI, Insn, Address, this, STI);
6113 if (Result != MCDisassembler::Fail) {
6114 Size = 4;
6115 // Add a fake predicate operand, because we share these instruction
6116 // definitions with Thumb2 where these instructions are predicable.
6117 if (Table.DecodePred && MCII->get(MI.getOpcode()).isPredicable()) {
6118 MI.addOperand(MCOperand::createImm(ARMCC::AL));
6119 MI.addOperand(MCOperand::createReg(ARM::NoRegister));
6120 }
6121 return Result;
6122 }
6123 }
6124
6125 Result =
6126 decodeInstruction(DecoderTableCoProc32, MI, Insn, Address, this, STI);
6127 if (Result != MCDisassembler::Fail) {
6128 Size = 4;
6129 return checkDecodedInstruction(MI, Size, Address, CS, Insn, Result);
6130 }
6131
6132 Size = 4;
6133 return MCDisassembler::Fail;
6134}
6135
6136bool ARMDisassembler::isVectorPredicable(const MCInst &MI) const {
6137 const MCInstrDesc &MCID = MCII->get(MI.getOpcode());
6138 for (unsigned i = 0; i < MCID.NumOperands; ++i) {
6139 if (ARM::isVpred(MCID.operands()[i].OperandType))
6140 return true;
6141 }
6142 return false;
6143}
6144
6145// Most Thumb instructions don't have explicit predicates in the
6146// encoding, but rather get their predicates from IT context. We need
6147// to fix up the predicate operands using this context information as a
6148// post-pass.
6150ARMDisassembler::AddThumbPredicate(MCInst &MI) const {
6152
6153 const FeatureBitset &FeatureBits = getSubtargetInfo().getFeatureBits();
6154
6155 // A few instructions actually have predicates encoded in them. Don't
6156 // try to overwrite it if we're seeing one of those.
6157 switch (MI.getOpcode()) {
6158 case ARM::tBcc:
6159 case ARM::t2Bcc:
6160 case ARM::tCBZ:
6161 case ARM::tCBNZ:
6162 case ARM::tCPS:
6163 case ARM::t2CPS3p:
6164 case ARM::t2CPS2p:
6165 case ARM::t2CPS1p:
6166 case ARM::t2CSEL:
6167 case ARM::t2CSINC:
6168 case ARM::t2CSINV:
6169 case ARM::t2CSNEG:
6170 case ARM::tMOVSr:
6171 case ARM::tSETEND:
6172 // Some instructions (mostly conditional branches) are not
6173 // allowed in IT blocks.
6174 if (ITBlock.instrInITBlock())
6175 S = SoftFail;
6176 else
6177 return Success;
6178 break;
6179 case ARM::t2HINT:
6180 if (MI.getOperand(0).getImm() == 0x10 && (FeatureBits[ARM::FeatureRAS]) != 0)
6181 S = SoftFail;
6182 break;
6183 case ARM::tB:
6184 case ARM::t2B:
6185 case ARM::t2TBB:
6186 case ARM::t2TBH:
6187 // Some instructions (mostly unconditional branches) can
6188 // only appears at the end of, or outside of, an IT.
6189 if (ITBlock.instrInITBlock() && !ITBlock.instrLastInITBlock())
6190 S = SoftFail;
6191 break;
6192 default:
6193 break;
6194 }
6195
6196 // Warn on non-VPT predicable instruction in a VPT block and a VPT
6197 // predicable instruction in an IT block
6198 if ((!isVectorPredicable(MI) && VPTBlock.instrInVPTBlock()) ||
6199 (isVectorPredicable(MI) && ITBlock.instrInITBlock()))
6200 S = SoftFail;
6201
6202 // If we're in an IT/VPT block, base the predicate on that. Otherwise,
6203 // assume a predicate of AL.
6204 unsigned CC = ARMCC::AL;
6205 unsigned VCC = ARMVCC::None;
6206 if (ITBlock.instrInITBlock()) {
6207 CC = ITBlock.getITCC();
6208 ITBlock.advanceITState();
6209 } else if (VPTBlock.instrInVPTBlock()) {
6210 VCC = VPTBlock.getVPTPred();
6211 VPTBlock.advanceVPTState();
6212 }
6213
6214 const MCInstrDesc &MCID = MCII->get(MI.getOpcode());
6215
6216 MCInst::iterator CCI = MI.begin();
6217 for (unsigned i = 0; i < MCID.NumOperands; ++i, ++CCI) {
6218 if (MCID.operands()[i].isPredicate() || CCI == MI.end())
6219 break;
6220 }
6221
6222 if (MCID.isPredicable()) {
6223 CCI = MI.insert(CCI, MCOperand::createImm(CC));
6224 ++CCI;
6225 if (CC == ARMCC::AL)
6226 MI.insert(CCI, MCOperand::createReg(ARM::NoRegister));
6227 else
6228 MI.insert(CCI, MCOperand::createReg(ARM::CPSR));
6229 } else if (CC != ARMCC::AL) {
6230 Check(S, SoftFail);
6231 }
6232
6233 MCInst::iterator VCCI = MI.begin();
6234 unsigned VCCPos;
6235 for (VCCPos = 0; VCCPos < MCID.NumOperands; ++VCCPos, ++VCCI) {
6236 if (ARM::isVpred(MCID.operands()[VCCPos].OperandType) || VCCI == MI.end())
6237 break;
6238 }
6239
6240 if (isVectorPredicable(MI)) {
6241 VCCI = MI.insert(VCCI, MCOperand::createImm(VCC));
6242 ++VCCI;
6243 if (VCC == ARMVCC::None)
6244 VCCI = MI.insert(VCCI, MCOperand::createReg(0));
6245 else
6246 VCCI = MI.insert(VCCI, MCOperand::createReg(ARM::P0));
6247 ++VCCI;
6248 VCCI = MI.insert(VCCI, MCOperand::createReg(0));
6249 ++VCCI;
6250 if (MCID.operands()[VCCPos].OperandType == ARM::OPERAND_VPRED_R) {
6251 int TiedOp = MCID.getOperandConstraint(VCCPos + 3, MCOI::TIED_TO);
6252 assert(TiedOp >= 0 &&
6253 "Inactive register in vpred_r is not tied to an output!");
6254 // Copy the operand to ensure it's not invalidated when MI grows.
6255 MI.insert(VCCI, MCOperand(MI.getOperand(TiedOp)));
6256 }
6257 } else if (VCC != ARMVCC::None) {
6258 Check(S, SoftFail);
6259 }
6260
6261 return S;
6262}
6263
6264// Thumb VFP and some NEON instructions are a special case. Because we share
6265// their encodings between ARM and Thumb modes, and they are predicable in ARM
6266// mode, the auto-generated decoder will give them an (incorrect)
6267// predicate operand. We need to rewrite these operands based on the IT
6268// context as a post-pass.
6269void ARMDisassembler::UpdateThumbPredicate(DecodeStatus &S, MCInst &MI) const {
6270 unsigned CC;
6271 CC = ITBlock.getITCC();
6272 if (CC == 0xF)
6273 CC = ARMCC::AL;
6274 if (ITBlock.instrInITBlock())
6275 ITBlock.advanceITState();
6276 else if (VPTBlock.instrInVPTBlock()) {
6277 CC = VPTBlock.getVPTPred();
6278 VPTBlock.advanceVPTState();
6279 }
6280
6281 const MCInstrDesc &MCID = MCII->get(MI.getOpcode());
6282 ArrayRef<MCOperandInfo> OpInfo = MCID.operands();
6283 MCInst::iterator I = MI.begin();
6284 unsigned short NumOps = MCID.NumOperands;
6285 for (unsigned i = 0; i < NumOps; ++i, ++I) {
6286 if (OpInfo[i].isPredicate() ) {
6287 if (CC != ARMCC::AL && !MCID.isPredicable())
6288 Check(S, SoftFail);
6289 I->setImm(CC);
6290 ++I;
6291 if (CC == ARMCC::AL)
6292 I->setReg(ARM::NoRegister);
6293 else
6294 I->setReg(ARM::CPSR);
6295 return;
6296 }
6297 }
6298}
6299
6300DecodeStatus ARMDisassembler::getThumbInstruction(MCInst &MI, uint64_t &Size,
6301 ArrayRef<uint8_t> Bytes,
6302 uint64_t Address,
6303 raw_ostream &CS) const {
6304 CommentStream = &CS;
6305
6306 assert(STI.hasFeature(ARM::ModeThumb) &&
6307 "Asked to disassemble in Thumb mode but Subtarget is in ARM mode!");
6308
6309 // We want to read exactly 2 bytes of data.
6310 if (Bytes.size() < 2) {
6311 Size = 0;
6312 return MCDisassembler::Fail;
6313 }
6314
6315 uint16_t Insn16 = llvm::support::endian::read<uint16_t>(
6316 Bytes.data(), InstructionEndianness);
6318 decodeInstruction(DecoderTableThumb16, MI, Insn16, Address, this, STI);
6319 if (Result != MCDisassembler::Fail) {
6320 Size = 2;
6321 Check(Result, AddThumbPredicate(MI));
6322 return Result;
6323 }
6324
6325 Result = decodeInstruction(DecoderTableThumbSBit16, MI, Insn16, Address, this,
6326 STI);
6327 if (Result) {
6328 Size = 2;
6329 Check(Result, AddThumbPredicate(MI));
6330 return Result;
6331 }
6332
6333 Result =
6334 decodeInstruction(DecoderTableThumb216, MI, Insn16, Address, this, STI);
6335 if (Result != MCDisassembler::Fail) {
6336 Size = 2;
6337
6338 // Nested IT blocks are UNPREDICTABLE. Must be checked before we add
6339 // the Thumb predicate.
6340 if (MI.getOpcode() == ARM::t2IT && ITBlock.instrInITBlock())
6342
6343 Check(Result, AddThumbPredicate(MI));
6344
6345 // If we find an IT instruction, we need to parse its condition
6346 // code and mask operands so that we can apply them correctly
6347 // to the subsequent instructions.
6348 if (MI.getOpcode() == ARM::t2IT) {
6349 unsigned Firstcond = MI.getOperand(0).getImm();
6350 unsigned Mask = MI.getOperand(1).getImm();
6351 ITBlock.setITState(Firstcond, Mask);
6352
6353 // An IT instruction that would give a 'NV' predicate is unpredictable.
6354 if (Firstcond == ARMCC::AL && !isPowerOf2_32(Mask))
6355 CS << "unpredictable IT predicate sequence";
6356 }
6357
6358 return Result;
6359 }
6360
6361 // We want to read exactly 4 bytes of data.
6362 if (Bytes.size() < 4) {
6363 Size = 0;
6364 return MCDisassembler::Fail;
6365 }
6366
6367 uint32_t Insn32 =
6368 (uint32_t(Insn16) << 16) | llvm::support::endian::read<uint16_t>(
6369 Bytes.data() + 2, InstructionEndianness);
6370
6371 Result =
6372 decodeInstruction(DecoderTableMVE32, MI, Insn32, Address, this, STI);
6373 if (Result != MCDisassembler::Fail) {
6374 Size = 4;
6375
6376 // Nested VPT blocks are UNPREDICTABLE. Must be checked before we add
6377 // the VPT predicate.
6378 if (isVPTOpcode(MI.getOpcode()) && VPTBlock.instrInVPTBlock())
6380
6381 Check(Result, AddThumbPredicate(MI));
6382
6383 if (isVPTOpcode(MI.getOpcode())) {
6384 unsigned Mask = MI.getOperand(0).getImm();
6385 VPTBlock.setVPTState(Mask);
6386 }
6387
6388 return Result;
6389 }
6390
6391 Result =
6392 decodeInstruction(DecoderTableThumb32, MI, Insn32, Address, this, STI);
6393 if (Result != MCDisassembler::Fail) {
6394 Size = 4;
6395 Check(Result, AddThumbPredicate(MI));
6396 return Result;
6397 }
6398
6399 Result =
6400 decodeInstruction(DecoderTableThumb232, MI, Insn32, Address, this, STI);
6401 if (Result != MCDisassembler::Fail) {
6402 Size = 4;
6403 Check(Result, AddThumbPredicate(MI));
6404 return checkDecodedInstruction(MI, Size, Address, CS, Insn32, Result);
6405 }
6406
6407 if (fieldFromInstruction(Insn32, 28, 4) == 0xE) {
6408 Result =
6409 decodeInstruction(DecoderTableVFP32, MI, Insn32, Address, this, STI);
6410 if (Result != MCDisassembler::Fail) {
6411 Size = 4;
6412 UpdateThumbPredicate(Result, MI);
6413 return Result;
6414 }
6415 }
6416
6417 Result =
6418 decodeInstruction(DecoderTableVFPV832, MI, Insn32, Address, this, STI);
6419 if (Result != MCDisassembler::Fail) {
6420 Size = 4;
6421 return Result;
6422 }
6423
6424 if (fieldFromInstruction(Insn32, 28, 4) == 0xE) {
6425 Result = decodeInstruction(DecoderTableNEONDup32, MI, Insn32, Address, this,
6426 STI);
6427 if (Result != MCDisassembler::Fail) {
6428 Size = 4;
6429 UpdateThumbPredicate(Result, MI);
6430 return Result;
6431 }
6432 }
6433
6434 if (fieldFromInstruction(Insn32, 24, 8) == 0xF9) {
6435 uint32_t NEONLdStInsn = Insn32;
6436 NEONLdStInsn &= 0xF0FFFFFF;
6437 NEONLdStInsn |= 0x04000000;
6438 Result = decodeInstruction(DecoderTableNEONLoadStore32, MI, NEONLdStInsn,
6439 Address, this, STI);
6440 if (Result != MCDisassembler::Fail) {
6441 Size = 4;
6442 Check(Result, AddThumbPredicate(MI));
6443 return Result;
6444 }
6445 }
6446
6447 if (fieldFromInstruction(Insn32, 24, 4) == 0xF) {
6448 uint32_t NEONDataInsn = Insn32;
6449 NEONDataInsn &= 0xF0FFFFFF; // Clear bits 27-24
6450 NEONDataInsn |= (NEONDataInsn & 0x10000000) >> 4; // Move bit 28 to bit 24
6451 NEONDataInsn |= 0x12000000; // Set bits 28 and 25
6452 Result = decodeInstruction(DecoderTableNEONData32, MI, NEONDataInsn,
6453 Address, this, STI);
6454 if (Result != MCDisassembler::Fail) {
6455 Size = 4;
6456 Check(Result, AddThumbPredicate(MI));
6457 return Result;
6458 }
6459
6460 uint32_t NEONCryptoInsn = Insn32;
6461 NEONCryptoInsn &= 0xF0FFFFFF; // Clear bits 27-24
6462 NEONCryptoInsn |= (NEONCryptoInsn & 0x10000000) >> 4; // Move bit 28 to bit 24
6463 NEONCryptoInsn |= 0x12000000; // Set bits 28 and 25
6464 Result = decodeInstruction(DecoderTablev8Crypto32, MI, NEONCryptoInsn,
6465 Address, this, STI);
6466 if (Result != MCDisassembler::Fail) {
6467 Size = 4;
6468 return Result;
6469 }
6470
6471 uint32_t NEONv8Insn = Insn32;
6472 NEONv8Insn &= 0xF3FFFFFF; // Clear bits 27-26
6473 Result = decodeInstruction(DecoderTablev8NEON32, MI, NEONv8Insn, Address,
6474 this, STI);
6475 if (Result != MCDisassembler::Fail) {
6476 Size = 4;
6477 return Result;
6478 }
6479 }
6480
6481 uint32_t Coproc = fieldFromInstruction(Insn32, 8, 4);
6482 const uint8_t *DecoderTable = ARM::isCDECoproc(Coproc, STI)
6483 ? DecoderTableThumb2CDE32
6484 : DecoderTableThumb2CoProc32;
6485 Result =
6486 decodeInstruction(DecoderTable, MI, Insn32, Address, this, STI);
6487 if (Result != MCDisassembler::Fail) {
6488 Size = 4;
6489 Check(Result, AddThumbPredicate(MI));
6490 return Result;
6491 }
6492
6493 // Advance IT state to prevent next instruction inheriting
6494 // the wrong IT state.
6495 if (ITBlock.instrInITBlock())
6496 ITBlock.advanceITState();
6497 Size = 0;
6498 return MCDisassembler::Fail;
6499}
6500
6502 const MCSubtargetInfo &STI,
6503 MCContext &Ctx) {
6504 return new ARMDisassembler(STI, Ctx, T.createMCInstrInfo());
6505}
6506
6507extern "C" LLVM_ABI LLVM_EXTERNAL_VISIBILITY void
#define SoftFail
MCDisassembler::DecodeStatus DecodeStatus
#define Success
assert(UImm &&(UImm !=~static_cast< T >(0)) &&"Invalid immediate!")
AMDGPU Mark last scratch load
static bool isVectorPredicable(const MCInstrDesc &MCID)
static DecodeStatus DecodeDPairSpacedRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeCCOutOperand(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeAddrMode2IdxInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeT2AddrModeImm0_1020s4(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeT2AddrModeImm12(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)
static const uint16_t GPRPairDecoderTable[]
static DecodeStatus DecodeLDRPreReg(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeGPRPairnospRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeDoubleRegStore(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeT2SOImm(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeT2LoadT(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeAddrMode6Operand(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeMVEVPNOT(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeMVEVCMP(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeMVEVMOVDRegtoQ(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeShiftRight16Imm(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeAddrMode5FP16Operand(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)
static const MCPhysReg QQPRDecoderTable[]
static DecodeStatus DecodeT2LoadLabel(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeQPRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeShiftRight64Imm(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeVLD4LN(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeDPRRegListOperand(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecoderForMRRC2AndMCRR2(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeThumbAddrModePC(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeMVEPairVectorIndexOperand(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeGPRnopcRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeArmMOVTWInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeT2AddrModeImm8(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecoderGPRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeTAddrModeImm7(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeBranchImmInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeT2AddrModeImm7s4(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)
static void tryAddingPcLoadReferenceComment(uint64_t Address, int Value, const MCDisassembler *Decoder)
tryAddingPcLoadReferenceComment - trys to add a comment as to what is being referenced by a load inst...
static DecodeStatus DecodeGPRwithAPSRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeSORegImmOperand(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeShiftRight32Imm(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeVLD1DupInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
LLVM_ABI LLVM_EXTERNAL_VISIBILITY void LLVMInitializeARMDisassembler()
static DecodeStatus DecodeT2MOVTWInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeT2LdStPre(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static const MCPhysReg DPairDecoderTable[]
static DecodeStatus DecodeTSBInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeMVE_MEM_1_pre(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeDoubleRegLoad(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeThumbAddrModeIS(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodePowerTwoOperand(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeT2Imm7S4(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeQADDInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static const MCPhysReg DPairSpacedDecoderTable[]
static DecodeStatus DecodeThumbBROperand(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeRestrictedIPredicateOperand(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeSTRPreReg(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeSPRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeSETPANInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeThumbAddSPReg(MCInst &Inst, uint16_t Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeMQQQQPRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeVLD2LN(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeT2AddSubSPImm(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static MCDisassembler * createARMDisassembler(const Target &T, const MCSubtargetInfo &STI, MCContext &Ctx)
static DecodeStatus DecodeT2LoadImm12(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static unsigned FixedRegForVSTRVLDR_SYSREG(unsigned Opcode)
static DecodeStatus DecodeVST1LN(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeLDR(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)
static const MCPhysReg QPRDecoderTable[]
static DecodeStatus DecodeVST3LN(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static const MCPhysReg SPRDecoderTable[]
static DecodeStatus DecodeBFAfterTargetOperand(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeRestrictedUPredicateOperand(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeSORegMemOperand(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodetGPRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeCLRMGPRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeAddrMode5Operand(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeMQQPRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeVMOVRRS(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeGPRwithAPSR_NZCVnospRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
DecodeStatus OperandDecoder(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeThumbBLTargetOperand(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeCoprocessor(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeAddrMode3Instruction(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeSMLAInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeSwap(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeGPRwithZRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeVCVTD(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeVSTInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeCopMemInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeDPR_VFP2RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeT2CPSInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeThumbBCCTargetOperand(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeMVE_MEM_3_pre(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeAddrMode7Operand(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeThumbAddrModeSP(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeT2STRDPreInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeVLD1LN(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static bool PermitsD32(const MCInst &Inst, const MCDisassembler *Decoder)
static DecodeStatus DecodeT2Imm8(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)
static const uint16_t CLRMGPRDecoderTable[]
static const MCPhysReg DPRDecoderTable[]
static DecodeStatus DecodePostIdxReg(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeVLD3LN(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeT2LDRDPreInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeT2ShifterImmOperand(MCInst &Inst, uint32_t Val, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeT2Imm8S4(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeVpredROperand(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeThumbCPS(MCInst &Inst, uint16_t Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeCPSInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeThumbAddSpecialReg(MCInst &Inst, uint16_t Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeRestrictedSPredicateOperand(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeVCVTQ(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeSPRRegListOperand(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeGPRPairRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeMSRMask(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeVSHLMaxInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeMQPRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
static bool tryAddingSymbolicOperand(uint64_t Address, int32_t Value, bool isBranch, uint64_t InstSize, MCInst &MI, const MCDisassembler *Decoder)
tryAddingSymbolicOperand - trys to add a symbolic operand in place of the immediate Value in the MCIn...
static DecodeStatus DecodeT2LoadImm8(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeVLDST3Instruction(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeGPRwithZRnospRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
static const uint16_t GPRDecoderTable[]
static DecodeStatus DecodeMveAddrModeQ(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeT2Imm7(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeDPRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeThumbCmpBROperand(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeVpredNOperand(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeMVE_MEM_2_pre(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeMVEVCVTt1fp(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeVCVTImmOperand(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeMVEVMOVQtoDReg(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static const MCPhysReg QQQQPRDecoderTable[]
static DecodeStatus DecodeLongShiftOperand(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeMveAddrModeRQ(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeMVEModImmInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeIT(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeGPRspRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeSORegRegOperand(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeVLDST4Instruction(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeMVE_MEM_pre(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder, unsigned Rn, OperandDecoder RnDecoder, OperandDecoder AddrDecoder)
static DecodeStatus DecodeBitfieldMaskOperand(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeVLD4DupInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeT2AddrModeImm8s4(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeThumbTableBranch(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeMveVCTP(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus checkDecodedInstruction(MCInst &MI, uint64_t &Size, uint64_t Address, raw_ostream &CS, uint32_t Insn, DecodeStatus Result)
static DecodeStatus DecodeVSTRVLDR_SYSREG(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeVST4LN(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeMemBarrierOption(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeVLD2DupInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeNEONComplexLane64Instruction(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeSTRPreImm(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodetcGPRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodePredNoALOperand(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeVST2LN(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeVPTMaskOperand(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeMVEOverlappingLongShift(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeVLDInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodePredicateOperand(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeT2AddrModeSOReg(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeShiftRight8Imm(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeT2AddrModeImm7(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeVLDST2Instruction(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeTSTInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeAddrModeImm12Operand(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeTBLInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeLDRPreImm(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeT2HintSpaceInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeThumbAddSPImm(MCInst &Inst, uint16_t Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeBFLabelOperand(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeHPRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeDPairRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeVMOVModImmInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeRestrictedFPPredicateOperand(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeHINTInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeVSCCLRM(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeT2BROperand(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeMVEVADCInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeRFEInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeVLD3DupInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeT2BInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeThumb2BCCInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeT2Adr(MCInst &Inst, uint32_t Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeDPR_8RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodetGPREvenRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeThumbAddrModeRR(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeBankedReg(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodetGPROddRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeMemMultipleWritebackInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeThumbBLXOffset(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeGPRnospRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeVLDST1Instruction(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeSPR_8RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeVMOVSRR(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeLazyLoadStoreMul(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeT2LoadShift(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeForVMRSandVMSR(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeInstSyncBarrierOption(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeLOLoop(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static GCRegistry::Add< StatepointGC > D("statepoint-example", "an example strategy for statepoint")
#define LLVM_ABI
Definition Compiler.h:213
#define LLVM_EXTERNAL_VISIBILITY
Definition Compiler.h:132
static bool isNeg(Value *V)
Returns true if the operation is a negation of V, and it works for both integers and floats.
static bool isSigned(unsigned int Opcode)
#define Check(C,...)
#define op(i)
amode Optimize addressing mode
IRTranslator LLVM IR MI
const size_t AbstractManglingParser< Derived, Alloc >::NumOps
#define I(x, y, z)
Definition MD5.cpp:58
#define T
#define P(N)
static bool isBranch(unsigned Opcode)
const SmallVectorImpl< MachineOperand > & Cond
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition ArrayRef.h:41
size_t size() const
size - Get the array size.
Definition ArrayRef.h:147
const T * data() const
Definition ArrayRef.h:144
Container class for subtarget features.
Context object for machine code objects.
Definition MCContext.h:83
Superclass for all disassemblers.
bool tryAddingSymbolicOperand(MCInst &Inst, int64_t Value, uint64_t Address, bool IsBranch, uint64_t Offset, uint64_t OpSize, uint64_t InstSize) const
const MCSubtargetInfo & getSubtargetInfo() const
void tryAddingPcLoadReferenceComment(int64_t Value, uint64_t Address) const
DecodeStatus
Ternary decode status.
Instances of this class represent a single low-level machine instruction.
Definition MCInst.h:188
unsigned getNumOperands() const
Definition MCInst.h:212
SmallVectorImpl< MCOperand >::iterator iterator
Definition MCInst.h:220
unsigned getOpcode() const
Definition MCInst.h:202
void addOperand(const MCOperand Op)
Definition MCInst.h:215
iterator end()
Definition MCInst.h:229
void setOpcode(unsigned Op)
Definition MCInst.h:201
const MCOperand & getOperand(unsigned i) const
Definition MCInst.h:210
unsigned getNumOperands() const
Return the number of declared MachineOperands for this MachineInstruction.
ArrayRef< MCOperandInfo > operands() const
unsigned short NumOperands
int getOperandConstraint(unsigned OpNum, MCOI::OperandConstraint Constraint) const
Returns the value of the specified operand constraint if it is present.
bool isPredicable() const
Return true if this instruction has a predicate operand that controls execution.
bool isVariadic() const
Return true if this instruction can have a variable number of operands.
Interface to description of machine instruction set.
Definition MCInstrInfo.h:27
const MCInstrDesc & get(unsigned Opcode) const
Return the machine instruction descriptor that corresponds to the specified instruction opcode.
Definition MCInstrInfo.h:90
int64_t getImm() const
Definition MCInst.h:84
static MCOperand createReg(MCRegister Reg)
Definition MCInst.h:138
static MCOperand createImm(int64_t Val)
Definition MCInst.h:145
MCRegister getReg() const
Returns the register number.
Definition MCInst.h:73
Wrapper class representing physical registers. Should be passed by value.
Definition MCRegister.h:33
Generic base class for all target subtargets.
bool hasFeature(unsigned Feature) const
const FeatureBitset & getFeatureBits() const
Wrapper class representing virtual and physical registers.
Definition Register.h:19
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Target - Wrapper for Target specific information.
LLVM Value Representation.
Definition Value.h:75
This class implements an extremely fast bulk output stream that can only output to a stream.
Definition raw_ostream.h:53
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
unsigned getAM2Opc(AddrOpc Opc, unsigned Imm12, ShiftOpc SO, unsigned IdxMode=0)
unsigned getAM5Opc(AddrOpc Opc, unsigned char Offset)
getAM5Opc - This function encodes the addrmode5 opc field.
unsigned getAM5FP16Opc(AddrOpc Opc, unsigned char Offset)
getAM5FP16Opc - This function encodes the addrmode5fp16 opc field.
bool isVpred(OperandType op)
bool isCDECoproc(size_t Coproc, const MCSubtargetInfo &STI)
@ D16
Only 16 D registers.
constexpr std::underlying_type_t< E > Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
std::enable_if_t< std::is_integral_v< IntType >, IntType > fieldFromInstruction(const IntType &Insn, unsigned StartBit, unsigned NumBits)
Definition MCDecoder.h:37
value_type read(const void *memory, endianness endian)
Read a value of a particular endianness from memory.
Definition Endian.h:58
This is an optimization pass for GlobalISel generic memory operations.
constexpr T rotr(T V, int R)
Definition bit.h:340
auto size(R &&Range, std::enable_if_t< std::is_base_of< std::random_access_iterator_tag, typename std::iterator_traits< decltype(Range.begin())>::iterator_category >::value, void > *=nullptr)
Get the size of a range.
Definition STLExtras.h:1657
Target & getTheThumbBETarget()
static bool isVPTOpcode(int Opc)
LLVM_ABI void reportFatalInternalError(Error Err)
Report a fatal error that indicates a bug in LLVM.
Definition Error.cpp:177
int countr_zero(T Val)
Count number of 0's from the least significant bit to the most stopping at the first 1.
Definition bit.h:186
constexpr bool isPowerOf2_32(uint32_t Value)
Return true if the argument is a power of two > 0.
Definition MathExtras.h:288
static bool isValidCoprocessorNumber(unsigned Num, const FeatureBitset &featureBits)
isValidCoprocessorNumber - decide whether an explicit coprocessor number is legal in generic instruct...
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
Definition MCRegister.h:21
DWARFExpression::Operation Op
ArrayRef(const T &OneElt) -> ArrayRef< T >
constexpr int32_t SignExtend32(uint32_t X)
Sign-extend the number in the bottom B bits of X to a 32-bit integer.
Definition MathExtras.h:565
endianness
Definition bit.h:71
Target & getTheARMLETarget()
Target & getTheARMBETarget()
Target & getTheThumbLETarget()
static void RegisterMCDisassembler(Target &T, Target::MCDisassemblerCtorTy Fn)
RegisterMCDisassembler - Register a MCDisassembler implementation for the given target.