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LLVM 22.0.0git
LoongArchDisassembler.cpp
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1//===-- LoongArchDisassembler.cpp - Disassembler for LoongArch ------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file implements the LoongArchDisassembler class.
10//
11//===----------------------------------------------------------------------===//
12
15#include "llvm/MC/MCContext.h"
16#include "llvm/MC/MCDecoder.h"
19#include "llvm/MC/MCInst.h"
20#include "llvm/MC/MCInstrInfo.h"
24#include "llvm/Support/Endian.h"
25
26using namespace llvm;
27using namespace llvm::MCD;
28
29#define DEBUG_TYPE "loongarch-disassembler"
30
32
33namespace {
34class LoongArchDisassembler : public MCDisassembler {
35public:
36 LoongArchDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx)
37 : MCDisassembler(STI, Ctx) {}
38
39 DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size,
40 ArrayRef<uint8_t> Bytes, uint64_t Address,
41 raw_ostream &CStream) const override;
42};
43} // end namespace
44
46 const MCSubtargetInfo &STI,
47 MCContext &Ctx) {
48 return new LoongArchDisassembler(STI, Ctx);
49}
50
59
61 uint64_t Address,
62 const MCDisassembler *Decoder) {
63 if (RegNo >= 32)
65 Inst.addOperand(MCOperand::createReg(LoongArch::R0 + RegNo));
67}
68
69static DecodeStatus
71 const MCDisassembler *Decoder) {
72 if (RegNo <= 1)
74 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder);
75}
76
78 uint64_t Address,
79 const MCDisassembler *Decoder) {
80 if (RegNo >= 32)
82 Inst.addOperand(MCOperand::createReg(LoongArch::F0 + RegNo));
84}
85
87 uint64_t Address,
88 const MCDisassembler *Decoder) {
89 if (RegNo >= 32)
91 Inst.addOperand(MCOperand::createReg(LoongArch::F0_64 + RegNo));
93}
94
96 uint64_t Address,
97 const MCDisassembler *Decoder) {
98 if (RegNo >= 8)
100 Inst.addOperand(MCOperand::createReg(LoongArch::FCC0 + RegNo));
102}
103
105 uint64_t Address,
106 const MCDisassembler *Decoder) {
107 if (RegNo >= 4)
109 Inst.addOperand(MCOperand::createReg(LoongArch::FCSR0 + RegNo));
111}
112
114 uint64_t Address,
115 const MCDisassembler *Decoder) {
116 if (RegNo >= 32)
118 Inst.addOperand(MCOperand::createReg(LoongArch::VR0 + RegNo));
120}
121
123 uint64_t Address,
124 const MCDisassembler *Decoder) {
125 if (RegNo >= 32)
127 Inst.addOperand(MCOperand::createReg(LoongArch::XR0 + RegNo));
129}
130
132 uint64_t Address,
133 const MCDisassembler *Decoder) {
134 if (RegNo >= 4)
136 Inst.addOperand(MCOperand::createReg(LoongArch::SCR0 + RegNo));
138}
139
140template <unsigned N, int P = 0>
142 int64_t Address,
143 const MCDisassembler *Decoder) {
144 assert(isUInt<N>(Imm) && "Invalid immediate");
145 Inst.addOperand(MCOperand::createImm(Imm + P));
147}
148
149template <unsigned N, unsigned S = 0>
151 int64_t Address,
152 const MCDisassembler *Decoder) {
153 assert(isUInt<N>(Imm) && "Invalid immediate");
154 // Shift left Imm <S> bits, then sign-extend the number in the bottom <N+S>
155 // bits.
158}
159
160#include "LoongArchGenDisassemblerTables.inc"
161
162DecodeStatus LoongArchDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
163 ArrayRef<uint8_t> Bytes,
164 uint64_t Address,
165 raw_ostream &CS) const {
166 uint32_t Insn;
168
169 // We want to read exactly 4 bytes of data because all LoongArch instructions
170 // are fixed 32 bits.
171 if (Bytes.size() < 4) {
172 Size = 0;
174 }
175
176 Insn = support::endian::read32le(Bytes.data());
177 // Calling the auto-generated decoder function.
178 Result = decodeInstruction(DecoderTable32, MI, Insn, Address, this, STI);
179 Size = 4;
180
181 return Result;
182}
MCDisassembler::DecodeStatus DecodeStatus
assert(UImm &&(UImm !=~static_cast< T >(0)) &&"Invalid immediate!")
#define LLVM_ABI
Definition Compiler.h:213
#define LLVM_EXTERNAL_VISIBILITY
Definition Compiler.h:132
IRTranslator LLVM IR MI
LLVM_ABI LLVM_EXTERNAL_VISIBILITY void LLVMInitializeLoongArchDisassembler()
static DecodeStatus DecodeSCRRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeCFRRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeLASX256RegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeFPR64RegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus decodeUImmOperand(MCInst &Inst, uint64_t Imm, int64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeFPR32RegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeLSX128RegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeGPRNoR0R1RegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
static MCDisassembler * createLoongArchDisassembler(const Target &T, const MCSubtargetInfo &STI, MCContext &Ctx)
static DecodeStatus decodeSImmOperand(MCInst &Inst, uint64_t Imm, int64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeFCSRRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
#define T
#define P(N)
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition ArrayRef.h:41
size_t size() const
size - Get the array size.
Definition ArrayRef.h:147
const T * data() const
Definition ArrayRef.h:144
Context object for machine code objects.
Definition MCContext.h:83
Superclass for all disassemblers.
DecodeStatus
Ternary decode status.
Instances of this class represent a single low-level machine instruction.
Definition MCInst.h:188
void addOperand(const MCOperand Op)
Definition MCInst.h:215
static MCOperand createReg(MCRegister Reg)
Definition MCInst.h:138
static MCOperand createImm(int64_t Val)
Definition MCInst.h:145
Generic base class for all target subtargets.
Target - Wrapper for Target specific information.
This class implements an extremely fast bulk output stream that can only output to a stream.
Definition raw_ostream.h:53
uint32_t read32le(const void *P)
Definition Endian.h:428
This is an optimization pass for GlobalISel generic memory operations.
Target & getTheLoongArch64Target()
constexpr bool isUInt(uint64_t x)
Checks if an unsigned integer fits into the given bit width.
Definition MathExtras.h:198
Target & getTheLoongArch32Target()
constexpr int64_t SignExtend64(uint64_t x)
Sign-extend the number in the bottom B bits of X to a 64-bit integer.
Definition MathExtras.h:583
static void RegisterMCDisassembler(Target &T, Target::MCDisassemblerCtorTy Fn)
RegisterMCDisassembler - Register a MCDisassembler implementation for the given target.